arch/powerpc/cpu/mpc85xx/ddr-gen3.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/fsl_ddr_sdram.h>
  12 #include <asm/processor.h>
  13
  14 #if (CONFIG_CHIP_SELECTS_PER_CTRL > 4)
  15 #error Invalid setting for CONFIG_CHIP_SELECTS_PER_CTRL
  16 #endif
  17
  18 void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
  19                              unsigned int ctrl_num)
  20 {
  21         unsigned int i;
  22         volatile ccsr_ddr_t *ddr;
  23         u32 temp_sdram_cfg;
  24
  25         switch (ctrl_num) {
  26         case 0:
  27                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  28                 break;
  29         case 1:
  30                 ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
  31                 break;
  32         default:
  33                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
  34                 return;
  35         }
  36
  37         out_be32(&ddr->eor, regs->ddr_eor);
  38
  39         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  40                 if (i == 0) {
  41                         out_be32(&ddr->cs0_bnds, regs->cs[i].bnds);
  42                         out_be32(&ddr->cs0_config, regs->cs[i].config);
  43                         out_be32(&ddr->cs0_config_2, regs->cs[i].config_2);
  44
  45                 } else if (i == 1) {
  46                         out_be32(&ddr->cs1_bnds, regs->cs[i].bnds);
  47                         out_be32(&ddr->cs1_config, regs->cs[i].config);
  48                         out_be32(&ddr->cs1_config_2, regs->cs[i].config_2);
  49
  50                 } else if (i == 2) {
  51                         out_be32(&ddr->cs2_bnds, regs->cs[i].bnds);
  52                         out_be32(&ddr->cs2_config, regs->cs[i].config);
  53                         out_be32(&ddr->cs2_config_2, regs->cs[i].config_2);
  54
  55                 } else if (i == 3) {
  56                         out_be32(&ddr->cs3_bnds, regs->cs[i].bnds);
  57                         out_be32(&ddr->cs3_config, regs->cs[i].config);
  58                         out_be32(&ddr->cs3_config_2, regs->cs[i].config_2);
  59                 }
  60         }
  61
  62         out_be32(&ddr->timing_cfg_3, regs->timing_cfg_3);
  63         out_be32(&ddr->timing_cfg_0, regs->timing_cfg_0);
  64         out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1);
  65         out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
  66         out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
  67         out_be32(&ddr->sdram_mode, regs->ddr_sdram_mode);
  68         out_be32(&ddr->sdram_mode_2, regs->ddr_sdram_mode_2);
  69         out_be32(&ddr->sdram_mode_3, regs->ddr_sdram_mode_3);
  70         out_be32(&ddr->sdram_mode_4, regs->ddr_sdram_mode_4);
  71         out_be32(&ddr->sdram_mode_5, regs->ddr_sdram_mode_5);
  72         out_be32(&ddr->sdram_mode_6, regs->ddr_sdram_mode_6);
  73         out_be32(&ddr->sdram_mode_7, regs->ddr_sdram_mode_7);
  74         out_be32(&ddr->sdram_mode_8, regs->ddr_sdram_mode_8);
  75         out_be32(&ddr->sdram_md_cntl, regs->ddr_sdram_md_cntl);
  76         out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
  77         out_be32(&ddr->sdram_data_init, regs->ddr_data_init);
  78         out_be32(&ddr->sdram_clk_cntl, regs->ddr_sdram_clk_cntl);
  79         out_be32(&ddr->init_addr, regs->ddr_init_addr);
  80         out_be32(&ddr->init_ext_addr, regs->ddr_init_ext_addr);
  81
  82         out_be32(&ddr->timing_cfg_4, regs->timing_cfg_4);
  83         out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5);
  84         out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
  85         out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
  86         out_be32(&ddr->ddr_sr_cntr, regs->ddr_sr_cntr);
  87         out_be32(&ddr->ddr_sdram_rcw_1, regs->ddr_sdram_rcw_1);
  88         out_be32(&ddr->ddr_sdram_rcw_2, regs->ddr_sdram_rcw_2);
  89         out_be32(&ddr->ddr_cdr1, regs->ddr_cdr1);
  90         out_be32(&ddr->ddr_cdr2, regs->ddr_cdr2);
  91         out_be32(&ddr->err_disable, regs->err_disable);
  92         out_be32(&ddr->err_int_en, regs->err_int_en);
  93         for (i = 0; i < 32; i++)
  94                 out_be32(&ddr->debug[i], regs->debug[i]);
  95
  96         /* Set, but do not enable the memory */
  97         temp_sdram_cfg = regs->ddr_sdram_cfg;
  98         temp_sdram_cfg &= ~(SDRAM_CFG_MEM_EN);
  99         out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 100 #ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
 101         if (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 102                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2 & 0xf07fffff);
 103                 out_be32(&ddr->debug[2], 0x00000400);
 104                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl & 0x7fffffff);
 105                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl & 0x7fffffff);
 106                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2 & 0xffffffeb);
 107                 out_be32(&ddr->mtcr, 0);
 108                 out_be32(&ddr->debug[12], 0x00000015);
 109                 out_be32(&ddr->debug[21], 0x24000000);
 110                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval & 0xffff);
 111                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_BI | SDRAM_CFG_MEM_EN);
 112
 113                 asm volatile("sync;isync");
 114                 while (!(in_be32(&ddr->debug[1]) & 0x2))
 115                         ;
 116
 117                 switch (regs->ddr_sdram_rcw_2 & 0x00f00000) {
 118                 case 0x00000000:
 119                         out_be32(&ddr->sdram_md_cntl,
 120                                 MD_CNTL_MD_EN           |
 121                                 MD_CNTL_CS_SEL_CS0_CS1  |
 122                                 0x04000000              |
 123                                 MD_CNTL_WRCW            |
 124                                 MD_CNTL_MD_VALUE(0x02));
 125                         break;
 126                 case 0x00100000:
 127                         out_be32(&ddr->sdram_md_cntl,
 128                                 MD_CNTL_MD_EN           |
 129                                 MD_CNTL_CS_SEL_CS0_CS1  |
 130                                 0x04000000              |
 131                                 MD_CNTL_WRCW            |
 132                                 MD_CNTL_MD_VALUE(0x0a));
 133                         break;
 134                 case 0x00200000:
 135                         out_be32(&ddr->sdram_md_cntl,
 136                                 MD_CNTL_MD_EN           |
 137                                 MD_CNTL_CS_SEL_CS0_CS1  |
 138                                 0x04000000              |
 139                                 MD_CNTL_WRCW            |
 140                                 MD_CNTL_MD_VALUE(0x12));
 141                         break;
 142                 case 0x00300000:
 143                         out_be32(&ddr->sdram_md_cntl,
 144                                 MD_CNTL_MD_EN           |
 145                                 MD_CNTL_CS_SEL_CS0_CS1  |
 146                                 0x04000000              |
 147                                 MD_CNTL_WRCW            |
 148                                 MD_CNTL_MD_VALUE(0x1a));
 149                         break;
 150                 default:
 151                         out_be32(&ddr->sdram_md_cntl,
 152                                 MD_CNTL_MD_EN           |
 153                                 MD_CNTL_CS_SEL_CS0_CS1  |
 154                                 0x04000000              |
 155                                 MD_CNTL_WRCW            |
 156                                 MD_CNTL_MD_VALUE(0x02));
 157                         printf("Unsupported RC10\n");
 158                         break;
 159                 }
 160
 161                 while (in_be32(&ddr->sdram_md_cntl) & 0x80000000)
 162                         ;
 163                 udelay(6);
 164                 out_be32(&ddr->sdram_cfg, temp_sdram_cfg);
 165                 out_be32(&ddr->timing_cfg_2, regs->timing_cfg_2);
 166                 out_be32(&ddr->debug[2], 0x0);
 167                 out_be32(&ddr->ddr_zq_cntl, regs->ddr_zq_cntl);
 168                 out_be32(&ddr->ddr_wrlvl_cntl, regs->ddr_wrlvl_cntl);
 169                 out_be32(&ddr->sdram_cfg_2, regs->ddr_sdram_cfg_2);
 170                 out_be32(&ddr->debug[12], 0x0);
 171                 out_be32(&ddr->debug[21], 0x0);
 172                 out_be32(&ddr->sdram_interval, regs->ddr_sdram_interval);
 173
 174         }
 175 #endif
 176         /*
 177          * For 8572 DDR1 erratum - DDR controller may enter illegal state
 178          * when operatiing in 32-bit bus mode with 4-beat bursts,
 179          * This erratum does not affect DDR3 mode, only for DDR2 mode.
 180          */
 181 #ifdef CONFIG_MPC8572
 182         if ((((in_be32(&ddr->sdram_cfg) >> 24) & 0x7) == SDRAM_TYPE_DDR2)
 183             && in_be32(&ddr->sdram_cfg) & 0x80000) {
 184                 /* set DEBUG_1[31] */
 185                 setbits_be32(&ddr->debug[0], 1);
 186         }
 187 #endif
 188
 189         /*
 190          * 500 painful micro-seconds must elapse between
 191          * the DDR clock setup and the DDR config enable.
 192          * DDR2 need 200 us, and DDR3 need 500 us from spec,
 193          * we choose the max, that is 500 us for all of case.
 194          */
 195         udelay(500);
 196         asm volatile("sync;isync");
 197
 198         /* Let the controller go */
 199         temp_sdram_cfg = in_be32(&ddr->sdram_cfg) & ~SDRAM_CFG_BI;
 200         out_be32(&ddr->sdram_cfg, temp_sdram_cfg | SDRAM_CFG_MEM_EN);
 201         asm volatile("sync;isync");
 202         while (!(in_be32(&ddr->debug[1]) & 0x2))
 203                 ;
 204
 205         /* Poll DDR_SDRAM_CFG_2[D_INIT] bit until auto-data init is done.  */
 206         while (in_be32(&ddr->sdram_cfg_2) & 0x10) {
 207                 udelay(10000);          /* throttle polling rate */
 208         }
 209 }