arch/powerpc/cpu/mpc8xx/i2c.c

   1 /*
   2  * (C) Copyright 2000
   3  * Paolo Scaffardi, AIRVENT SAM s.p.a - RIMINI(ITALY), arsenio@tin.it
   4  *
   5  * (C) Copyright 2000 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   6  * Marius Groeger <mgroeger@sysgo.de>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  *
  10  * Back ported to the 8xx platform (from the 8260 platform) by
  11  * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  12  */
  13
  14 #include <common.h>
  15
  16 #ifdef CONFIG_HARD_I2C
  17
  18 #include <commproc.h>
  19 #include <i2c.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /* tx/rx timeout (we need the i2c early, so we don't use get_timer()) */
  24 #define TOUT_LOOP 1000000
  25
  26 #define NUM_RX_BDS 4
  27 #define NUM_TX_BDS 4
  28 #define MAX_TX_SPACE 256
  29 #define I2C_RXTX_LEN 128        /* maximum tx/rx buffer length */
  30
  31 typedef struct I2C_BD {
  32         unsigned short status;
  33         unsigned short length;
  34         unsigned char *addr;
  35 } I2C_BD;
  36
  37 #define BD_I2C_TX_START 0x0400  /* special status for i2c: Start condition */
  38
  39 #define BD_I2C_TX_CL    0x0001  /* collision error */
  40 #define BD_I2C_TX_UN    0x0002  /* underflow error */
  41 #define BD_I2C_TX_NAK   0x0004  /* no acknowledge error */
  42 #define BD_I2C_TX_ERR   (BD_I2C_TX_NAK|BD_I2C_TX_UN|BD_I2C_TX_CL)
  43
  44 #define BD_I2C_RX_ERR   BD_SC_OV
  45
  46 typedef void (*i2c_ecb_t) (int, int);   /* error callback function */
  47
  48 /* This structure keeps track of the bd and buffer space usage. */
  49 typedef struct i2c_state {
  50         int rx_idx;             /* index   to next free Rx BD */
  51         int tx_idx;             /* index   to next free Tx BD */
  52         void *rxbd;             /* pointer to next free Rx BD */
  53         void *txbd;             /* pointer to next free Tx BD */
  54         int tx_space;           /* number  of Tx bytes left   */
  55         unsigned char *tx_buf;  /* pointer to free Tx area    */
  56         i2c_ecb_t err_cb;       /* error callback function    */
  57 } i2c_state_t;
  58
  59
  60 /* flags for i2c_send() and i2c_receive() */
  61 #define I2CF_ENABLE_SECONDARY   0x01  /* secondary_address is valid           */
  62 #define I2CF_START_COND         0x02  /* tx: generate start condition         */
  63 #define I2CF_STOP_COND          0x04  /* tx: generate stop  condition         */
  64
  65 /* return codes */
  66 #define I2CERR_NO_BUFFERS       0x01  /* no more BDs or buffer space          */
  67 #define I2CERR_MSG_TOO_LONG     0x02  /* tried to send/receive to much data   */
  68 #define I2CERR_TIMEOUT          0x03  /* timeout in i2c_doio()                */
  69 #define I2CERR_QUEUE_EMPTY      0x04  /* i2c_doio called without send/receive */
  70
  71 /* error callback flags */
  72 #define I2CECB_RX_ERR           0x10  /* this is a receive error              */
  73 #define     I2CECB_RX_ERR_OV    0x02  /* receive overrun error                */
  74 #define     I2CECB_RX_MASK      0x0f  /* mask for error bits                  */
  75 #define I2CECB_TX_ERR           0x20  /* this is a transmit error             */
  76 #define     I2CECB_TX_CL        0x01  /* transmit collision error             */
  77 #define     I2CECB_TX_UN        0x02  /* transmit underflow error             */
  78 #define     I2CECB_TX_NAK       0x04  /* transmit no ack error                */
  79 #define     I2CECB_TX_MASK      0x0f  /* mask for error bits                  */
  80 #define I2CECB_TIMEOUT          0x40  /* this is a timeout error              */
  81
  82 /*
  83  * Returns the best value of I2BRG to meet desired clock speed of I2C with
  84  * input parameters (clock speed, filter, and predivider value).
  85  * It returns computer speed value and the difference between it and desired
  86  * speed.
  87  */
  88 static inline int
  89 i2c_roundrate(int hz, int speed, int filter, int modval,
  90               int *brgval, int *totspeed)
  91 {
  92         int moddiv = 1 << (5 - (modval & 3)), brgdiv, div;
  93
  94         debug("\t[I2C] trying hz=%d, speed=%d, filter=%d, modval=%d\n",
  95                 hz, speed, filter, modval);
  96
  97         div = moddiv * speed;
  98         brgdiv = (hz + div - 1) / div;
  99
 100         debug("\t\tmoddiv=%d, brgdiv=%d\n", moddiv, brgdiv);
 101
 102         *brgval = ((brgdiv + 1) / 2) - 3 - (2 * filter);
 103
 104         if ((*brgval < 0) || (*brgval > 255)) {
 105                 debug("\t\trejected brgval=%d\n", *brgval);
 106                 return -1;
 107         }
 108
 109         brgdiv = 2 * (*brgval + 3 + (2 * filter));
 110         div = moddiv * brgdiv;
 111         *totspeed = hz / div;
 112
 113         debug("\t\taccepted brgval=%d, totspeed=%d\n", *brgval, *totspeed);
 114
 115         return 0;
 116 }
 117
 118 /*
 119  * Sets the I2C clock predivider and divider to meet required clock speed.
 120  */
 121 static int i2c_setrate(int hz, int speed)
 122 {
 123         immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 124         volatile i2c8xx_t *i2c = (i2c8xx_t *) & immap->im_i2c;
 125         int     brgval,
 126                 modval, /* 0-3 */
 127                 bestspeed_diff = speed,
 128                 bestspeed_brgval = 0,
 129                 bestspeed_modval = 0,
 130                 bestspeed_filter = 0,
 131                 totspeed,
 132                 filter = 0;     /* Use this fixed value */
 133
 134         for (modval = 0; modval < 4; modval++) {
 135                 if (i2c_roundrate
 136                     (hz, speed, filter, modval, &brgval, &totspeed) == 0) {
 137                         int diff = speed - totspeed;
 138
 139                         if ((diff >= 0) && (diff < bestspeed_diff)) {
 140                                 bestspeed_diff = diff;
 141                                 bestspeed_modval = modval;
 142                                 bestspeed_brgval = brgval;
 143                                 bestspeed_filter = filter;
 144                         }
 145                 }
 146         }
 147
 148         debug("[I2C] Best is:\n");
 149         debug("[I2C] CPU=%dhz RATE=%d F=%d I2MOD=%08x I2BRG=%08x DIFF=%dhz\n",
 150                 hz,
 151                 speed,
 152                 bestspeed_filter,
 153                 bestspeed_modval,
 154                 bestspeed_brgval,
 155                 bestspeed_diff);
 156
 157         i2c->i2c_i2mod |=
 158                 ((bestspeed_modval & 3) << 1) | (bestspeed_filter << 3);
 159         i2c->i2c_i2brg = bestspeed_brgval & 0xff;
 160
 161         debug("[I2C] i2mod=%08x i2brg=%08x\n",
 162                 i2c->i2c_i2mod,
 163                 i2c->i2c_i2brg);
 164
 165         return 1;
 166 }
 167
 168 void i2c_init(int speed, int slaveaddr)
 169 {
 170         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 171         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 172         volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
 173         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 174         ulong rbase, tbase;
 175         volatile I2C_BD *rxbd, *txbd;
 176         uint dpaddr;
 177
 178 #ifdef CONFIG_SYS_I2C_INIT_BOARD
 179         /* call board specific i2c bus reset routine before accessing the   */
 180         /* environment, which might be in a chip on that bus. For details   */
 181         /* about this problem see doc/I2C_Edge_Conditions.                  */
 182         i2c_init_board();
 183 #endif
 184
 185 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 186         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 187 #else
 188         /* Disable relocation */
 189         iip->iic_rpbase = 0;
 190 #endif
 191
 192 #ifdef CONFIG_SYS_ALLOC_DPRAM
 193         dpaddr = iip->iic_rbase;
 194         if (dpaddr == 0) {
 195                 /* need to allocate dual port ram */
 196                 dpaddr = dpram_alloc_align((NUM_RX_BDS * sizeof(I2C_BD)) +
 197                                            (NUM_TX_BDS * sizeof(I2C_BD)) +
 198                                            MAX_TX_SPACE, 8);
 199         }
 200 #else
 201         dpaddr = CPM_I2C_BASE;
 202 #endif
 203
 204         /*
 205          * initialise data in dual port ram:
 206          *
 207          * dpaddr->rbase -> rx BD         (NUM_RX_BDS * sizeof(I2C_BD) bytes)
 208          *         tbase -> tx BD         (NUM_TX_BDS * sizeof(I2C_BD) bytes)
 209          *                  tx buffer     (MAX_TX_SPACE bytes)
 210          */
 211
 212         rbase = dpaddr;
 213         tbase = rbase + NUM_RX_BDS * sizeof(I2C_BD);
 214
 215         /* Initialize Port B I2C pins. */
 216         cp->cp_pbpar |= 0x00000030;
 217         cp->cp_pbdir |= 0x00000030;
 218         cp->cp_pbodr |= 0x00000030;
 219
 220         /* Disable interrupts */
 221         i2c->i2c_i2mod = 0x00;
 222         i2c->i2c_i2cmr = 0x00;
 223         i2c->i2c_i2cer = 0xff;
 224         i2c->i2c_i2add = slaveaddr;
 225
 226         /*
 227          * Set the I2C BRG Clock division factor from desired i2c rate
 228          * and current CPU rate (we assume sccr dfbgr field is 0;
 229          * divide BRGCLK by 1)
 230          */
 231         debug("[I2C] Setting rate...\n");
 232         i2c_setrate(gd->cpu_clk, CONFIG_SYS_I2C_SPEED);
 233
 234         /* Set I2C controller in master mode */
 235         i2c->i2c_i2com = 0x01;
 236
 237         /* Set SDMA bus arbitration level to 5 (SDCR) */
 238         immap->im_siu_conf.sc_sdcr = 0x0001;
 239
 240         /* Initialize Tx/Rx parameters */
 241         iip->iic_rbase = rbase;
 242         iip->iic_tbase = tbase;
 243         rxbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_rbase]);
 244         txbd = (I2C_BD *) ((unsigned char *) &cp->cp_dpmem[iip->iic_tbase]);
 245
 246         debug("[I2C] rbase = %04x\n", iip->iic_rbase);
 247         debug("[I2C] tbase = %04x\n", iip->iic_tbase);
 248         debug("[I2C] rxbd = %08x\n", (int)rxbd);
 249         debug("[I2C] txbd = %08x\n", (int)txbd);
 250
 251         /* Set big endian byte order */
 252         iip->iic_tfcr = 0x10;
 253         iip->iic_rfcr = 0x10;
 254
 255         /* Set maximum receive size. */
 256         iip->iic_mrblr = I2C_RXTX_LEN;
 257
 258 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 259         /*
 260          *  Initialize required parameters if using microcode patch.
 261          */
 262         iip->iic_rbptr = iip->iic_rbase;
 263         iip->iic_tbptr = iip->iic_tbase;
 264         iip->iic_rstate = 0;
 265         iip->iic_tstate = 0;
 266 #else
 267         cp->cp_cpcr = mk_cr_cmd(CPM_CR_CH_I2C, CPM_CR_INIT_TRX) | CPM_CR_FLG;
 268         do {
 269                 __asm__ __volatile__("eieio");
 270         } while (cp->cp_cpcr & CPM_CR_FLG);
 271 #endif
 272
 273         /* Clear events and interrupts */
 274         i2c->i2c_i2cer = 0xff;
 275         i2c->i2c_i2cmr = 0x00;
 276 }
 277
 278 static void i2c_newio(i2c_state_t *state)
 279 {
 280         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 281         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 282         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 283
 284         debug("[I2C] i2c_newio\n");
 285
 286 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 287         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 288 #endif
 289         state->rx_idx = 0;
 290         state->tx_idx = 0;
 291         state->rxbd = (void *)&cp->cp_dpmem[iip->iic_rbase];
 292         state->txbd = (void *)&cp->cp_dpmem[iip->iic_tbase];
 293         state->tx_space = MAX_TX_SPACE;
 294         state->tx_buf = (uchar *)state->txbd + NUM_TX_BDS * sizeof(I2C_BD);
 295         state->err_cb = NULL;
 296
 297         debug("[I2C] rxbd = %08x\n", (int)state->rxbd);
 298         debug("[I2C] txbd = %08x\n", (int)state->txbd);
 299         debug("[I2C] tx_buf = %08x\n", (int)state->tx_buf);
 300
 301         /* clear the buffer memory */
 302         memset((char *)state->tx_buf, 0, MAX_TX_SPACE);
 303 }
 304
 305 static int
 306 i2c_send(i2c_state_t *state,
 307          unsigned char address,
 308          unsigned char secondary_address,
 309          unsigned int flags, unsigned short size, unsigned char *dataout)
 310 {
 311         volatile I2C_BD *txbd;
 312         int i, j;
 313
 314         debug("[I2C] i2c_send add=%02d sec=%02d flag=%02d size=%d\n",
 315                 address, secondary_address, flags, size);
 316
 317         /* trying to send message larger than BD */
 318         if (size > I2C_RXTX_LEN)
 319                 return I2CERR_MSG_TOO_LONG;
 320
 321         /* no more free bds */
 322         if (state->tx_idx >= NUM_TX_BDS || state->tx_space < (2 + size))
 323                 return I2CERR_NO_BUFFERS;
 324
 325         txbd = (I2C_BD *) state->txbd;
 326         txbd->addr = state->tx_buf;
 327
 328         debug("[I2C] txbd = %08x\n", (int)txbd);
 329
 330         if (flags & I2CF_START_COND) {
 331                 debug("[I2C] Formatting addresses...\n");
 332                 if (flags & I2CF_ENABLE_SECONDARY) {
 333                         /* Length of msg + dest addr */
 334                         txbd->length = size + 2;
 335
 336                         txbd->addr[0] = address << 1;
 337                         txbd->addr[1] = secondary_address;
 338                         i = 2;
 339                 } else {
 340                         /* Length of msg + dest addr */
 341                         txbd->length = size + 1;
 342                         /* Write dest addr to BD */
 343                         txbd->addr[0] = address << 1;
 344                         i = 1;
 345                 }
 346         } else {
 347                 txbd->length = size;    /* Length of message */
 348                 i = 0;
 349         }
 350
 351         /* set up txbd */
 352         txbd->status = BD_SC_READY;
 353         if (flags & I2CF_START_COND)
 354                 txbd->status |= BD_I2C_TX_START;
 355         if (flags & I2CF_STOP_COND)
 356                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 357
 358         /* Copy data to send into buffer */
 359         debug("[I2C] copy data...\n");
 360         for(j = 0; j < size; i++, j++)
 361                 txbd->addr[i] = dataout[j];
 362
 363         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 364                 txbd->length,
 365                 txbd->status,
 366                 txbd->addr[0],
 367                 txbd->addr[1]);
 368
 369         /* advance state */
 370         state->tx_buf += txbd->length;
 371         state->tx_space -= txbd->length;
 372         state->tx_idx++;
 373         state->txbd = (void *) (txbd + 1);
 374
 375         return 0;
 376 }
 377
 378 static int
 379 i2c_receive(i2c_state_t *state,
 380             unsigned char address,
 381             unsigned char secondary_address,
 382             unsigned int flags,
 383             unsigned short size_to_expect, unsigned char *datain)
 384 {
 385         volatile I2C_BD *rxbd, *txbd;
 386
 387         debug("[I2C] i2c_receive %02d %02d %02d\n",
 388                 address, secondary_address, flags);
 389
 390         /* Expected to receive too much */
 391         if (size_to_expect > I2C_RXTX_LEN)
 392                 return I2CERR_MSG_TOO_LONG;
 393
 394         /* no more free bds */
 395         if (state->tx_idx >= NUM_TX_BDS || state->rx_idx >= NUM_RX_BDS
 396             || state->tx_space < 2)
 397                 return I2CERR_NO_BUFFERS;
 398
 399         rxbd = (I2C_BD *) state->rxbd;
 400         txbd = (I2C_BD *) state->txbd;
 401
 402         debug("[I2C] rxbd = %08x\n", (int)rxbd);
 403         debug("[I2C] txbd = %08x\n", (int)txbd);
 404
 405         txbd->addr = state->tx_buf;
 406
 407         /* set up TXBD for destination address */
 408         if (flags & I2CF_ENABLE_SECONDARY) {
 409                 txbd->length = 2;
 410                 txbd->addr[0] = address << 1;   /* Write data */
 411                 txbd->addr[1] = secondary_address;      /* Internal address */
 412                 txbd->status = BD_SC_READY;
 413         } else {
 414                 txbd->length = 1 + size_to_expect;
 415                 txbd->addr[0] = (address << 1) | 0x01;
 416                 txbd->status = BD_SC_READY;
 417                 memset(&txbd->addr[1], 0, txbd->length);
 418         }
 419
 420         /* set up rxbd for reception */
 421         rxbd->status = BD_SC_EMPTY;
 422         rxbd->length = size_to_expect;
 423         rxbd->addr = datain;
 424
 425         txbd->status |= BD_I2C_TX_START;
 426         if (flags & I2CF_STOP_COND) {
 427                 txbd->status |= BD_SC_LAST | BD_SC_WRAP;
 428                 rxbd->status |= BD_SC_WRAP;
 429         }
 430
 431         debug("[I2C] txbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 432                 txbd->length,
 433                 txbd->status,
 434                 txbd->addr[0],
 435                 txbd->addr[1]);
 436         debug("[I2C] rxbd: length=0x%04x status=0x%04x addr[0]=0x%02x addr[1]=0x%02x\n",
 437                 rxbd->length,
 438                 rxbd->status,
 439                 rxbd->addr[0],
 440                 rxbd->addr[1]);
 441
 442         /* advance state */
 443         state->tx_buf += txbd->length;
 444         state->tx_space -= txbd->length;
 445         state->tx_idx++;
 446         state->txbd = (void *) (txbd + 1);
 447         state->rx_idx++;
 448         state->rxbd = (void *) (rxbd + 1);
 449
 450         return 0;
 451 }
 452
 453
 454 static int i2c_doio(i2c_state_t *state)
 455 {
 456         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 457         volatile cpm8xx_t *cp = (cpm8xx_t *)&immap->im_cpm;
 458         volatile i2c8xx_t *i2c = (i2c8xx_t *)&immap->im_i2c;
 459         volatile iic_t *iip = (iic_t *)&cp->cp_dparam[PROFF_IIC];
 460         volatile I2C_BD *txbd, *rxbd;
 461         volatile int j = 0;
 462
 463         debug("[I2C] i2c_doio\n");
 464
 465 #ifdef CONFIG_SYS_I2C_UCODE_PATCH
 466         iip = (iic_t *)&cp->cp_dpmem[iip->iic_rpbase];
 467 #endif
 468
 469         if (state->tx_idx <= 0 && state->rx_idx <= 0) {
 470                 debug("[I2C] No I/O is queued\n");
 471                 return I2CERR_QUEUE_EMPTY;
 472         }
 473
 474         iip->iic_rbptr = iip->iic_rbase;
 475         iip->iic_tbptr = iip->iic_tbase;
 476
 477         /* Enable I2C */
 478         debug("[I2C] Enabling I2C...\n");
 479         i2c->i2c_i2mod |= 0x01;
 480
 481         /* Begin transmission */
 482         i2c->i2c_i2com |= 0x80;
 483
 484         /* Loop until transmit & receive completed */
 485
 486         if (state->tx_idx > 0) {
 487                 txbd = ((I2C_BD*)state->txbd) - 1;
 488
 489                 debug("[I2C] Transmitting...(txbd=0x%08lx)\n",
 490                         (ulong)txbd);
 491
 492                 while ((txbd->status & BD_SC_READY) && (j++ < TOUT_LOOP)) {
 493                         if (ctrlc())
 494                                 return (-1);
 495
 496                         __asm__ __volatile__("eieio");
 497                 }
 498         }
 499
 500         if ((state->rx_idx > 0) && (j < TOUT_LOOP)) {
 501                 rxbd = ((I2C_BD*)state->rxbd) - 1;
 502
 503                 debug("[I2C] Receiving...(rxbd=0x%08lx)\n",
 504                         (ulong)rxbd);
 505
 506                 while ((rxbd->status & BD_SC_EMPTY) && (j++ < TOUT_LOOP)) {
 507                         if (ctrlc())
 508                                 return (-1);
 509
 510                         __asm__ __volatile__("eieio");
 511                 }
 512         }
 513
 514         /* Turn off I2C */
 515         i2c->i2c_i2mod &= ~0x01;
 516
 517         if (state->err_cb != NULL) {
 518                 int n, i, b;
 519
 520                 /*
 521                  * if we have an error callback function, look at the
 522                  * error bits in the bd status and pass them back
 523                  */
 524
 525                 if ((n = state->tx_idx) > 0) {
 526                         for (i = 0; i < n; i++) {
 527                                 txbd = ((I2C_BD *) state->txbd) - (n - i);
 528                                 if ((b = txbd->status & BD_I2C_TX_ERR) != 0)
 529                                         (*state->err_cb) (I2CECB_TX_ERR | b,
 530                                                           i);
 531                         }
 532                 }
 533
 534                 if ((n = state->rx_idx) > 0) {
 535                         for (i = 0; i < n; i++) {
 536                                 rxbd = ((I2C_BD *) state->rxbd) - (n - i);
 537                                 if ((b = rxbd->status & BD_I2C_RX_ERR) != 0)
 538                                         (*state->err_cb) (I2CECB_RX_ERR | b,
 539                                                           i);
 540                         }
 541                 }
 542
 543                 if (j >= TOUT_LOOP)
 544                         (*state->err_cb) (I2CECB_TIMEOUT, 0);
 545         }
 546
 547         return (j >= TOUT_LOOP) ? I2CERR_TIMEOUT : 0;
 548 }
 549
 550 static int had_tx_nak;
 551
 552 static void i2c_test_callback(int flags, int xnum)
 553 {
 554         if ((flags & I2CECB_TX_ERR) && (flags & I2CECB_TX_NAK))
 555                 had_tx_nak = 1;
 556 }
 557
 558 int i2c_probe(uchar chip)
 559 {
 560         i2c_state_t state;
 561         int rc;
 562         uchar buf[1];
 563
 564         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 565
 566         i2c_newio(&state);
 567
 568         state.err_cb = i2c_test_callback;
 569         had_tx_nak = 0;
 570
 571         rc = i2c_receive(&state, chip, 0, I2CF_START_COND | I2CF_STOP_COND, 1,
 572                          buf);
 573
 574         if (rc != 0)
 575                 return (rc);
 576
 577         rc = i2c_doio(&state);
 578
 579         if ((rc != 0) && (rc != I2CERR_TIMEOUT))
 580                 return (rc);
 581
 582         return (had_tx_nak);
 583 }
 584
 585 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
 586 {
 587         i2c_state_t state;
 588         uchar xaddr[4];
 589         int rc;
 590
 591         xaddr[0] = (addr >> 24) & 0xFF;
 592         xaddr[1] = (addr >> 16) & 0xFF;
 593         xaddr[2] = (addr >> 8) & 0xFF;
 594         xaddr[3] = addr & 0xFF;
 595
 596 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 597         /*
 598          * EEPROM chips that implement "address overflow" are ones like
 599          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 600          * extra bits end up in the "chip address" bit slots.  This makes
 601          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 602          *
 603          * Note that we consider the length of the address field to still
 604          * be one byte because the extra address bits are hidden in the
 605          * chip address.
 606          */
 607         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 608 #endif
 609
 610         i2c_newio(&state);
 611
 612         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 613                       &xaddr[4 - alen]);
 614         if (rc != 0) {
 615                 printf("i2c_read: i2c_send failed (%d)\n", rc);
 616                 return 1;
 617         }
 618
 619         rc = i2c_receive(&state, chip, 0, I2CF_STOP_COND, len, buffer);
 620         if (rc != 0) {
 621                 printf("i2c_read: i2c_receive failed (%d)\n", rc);
 622                 return 1;
 623         }
 624
 625         rc = i2c_doio(&state);
 626         if (rc != 0) {
 627                 printf("i2c_read: i2c_doio failed (%d)\n", rc);
 628                 return 1;
 629         }
 630         return 0;
 631 }
 632
 633 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
 634 {
 635         i2c_state_t state;
 636         uchar xaddr[4];
 637         int rc;
 638
 639         xaddr[0] = (addr >> 24) & 0xFF;
 640         xaddr[1] = (addr >> 16) & 0xFF;
 641         xaddr[2] = (addr >> 8) & 0xFF;
 642         xaddr[3] = addr & 0xFF;
 643
 644 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 645         /*
 646          * EEPROM chips that implement "address overflow" are ones like
 647          * Catalyst 24WC04/08/16 which has 9/10/11 bits of address and the
 648          * extra bits end up in the "chip address" bit slots.  This makes
 649          * a 24WC08 (1Kbyte) chip look like four 256 byte chips.
 650          *
 651          * Note that we consider the length of the address field to still
 652          * be one byte because the extra address bits are hidden in the
 653          * chip address.
 654          */
 655         chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 656 #endif
 657
 658         i2c_newio(&state);
 659
 660         rc = i2c_send(&state, chip, 0, I2CF_START_COND, alen,
 661                       &xaddr[4 - alen]);
 662         if (rc != 0) {
 663                 printf("i2c_write: first i2c_send failed (%d)\n", rc);
 664                 return 1;
 665         }
 666
 667         rc = i2c_send(&state, 0, 0, I2CF_STOP_COND, len, buffer);
 668         if (rc != 0) {
 669                 printf("i2c_write: second i2c_send failed (%d)\n", rc);
 670                 return 1;
 671         }
 672
 673         rc = i2c_doio(&state);
 674         if (rc != 0) {
 675                 printf("i2c_write: i2c_doio failed (%d)\n", rc);
 676                 return 1;
 677         }
 678         return 0;
 679 }
 680
 681 #endif /* CONFIG_HARD_I2C */