arch/powerpc/cpu/mpc8xxx/ddr/lc_common_dimm_params.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_ddr_sdram.h>
  11
  12 #include "ddr.h"
  13
  14 unsigned int
  15 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
  16                          common_timing_params_t *outpdimm,
  17                          unsigned int number_of_dimms)
  18 {
  19         unsigned int i;
  20         unsigned int tAAmin_ps = 0;
  21         unsigned int tCKmin_X_ps = 0;
  22         unsigned int common_caslat;
  23         unsigned int caslat_actual;
  24         unsigned int retry = 16;
  25         unsigned int tmp;
  26         const unsigned int mclk_ps = get_memory_clk_period_ps();
  27
  28         /* compute the common CAS latency supported between slots */
  29         tmp = dimm_params[0].caslat_X;
  30         for (i = 1; i < number_of_dimms; i++) {
  31                 if (dimm_params[i].n_ranks)
  32                         tmp &= dimm_params[i].caslat_X;
  33         }
  34         common_caslat = tmp;
  35
  36         /* compute the max tAAmin tCKmin between slots */
  37         for (i = 0; i < number_of_dimms; i++) {
  38                 tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
  39                 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
  40         }
  41         /* validate if the memory clk is in the range of dimms */
  42         if (mclk_ps < tCKmin_X_ps) {
  43                 printf("DDR clock (MCLK cycle %u ps) is faster than "
  44                         "the slowest DIMM(s) (tCKmin %u ps) can support.\n",
  45                         mclk_ps, tCKmin_X_ps);
  46                 return 1;
  47         }
  48         /* determine the acutal cas latency */
  49         caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
  50         /* check if the dimms support the CAS latency */
  51         while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
  52                 caslat_actual++;
  53                 retry--;
  54         }
  55         /* once the caculation of caslat_actual is completed
  56          * we must verify that this CAS latency value does not
  57          * exceed tAAmax, which is 20 ns for all DDR3 speed grades
  58          */
  59         if (caslat_actual * mclk_ps > 20000) {
  60                 printf("The choosen cas latency %d is too large\n",
  61                         caslat_actual);
  62                 return 1;
  63         }
  64         outpdimm->lowest_common_SPD_caslat = caslat_actual;
  65
  66         return 0;
  67 }
  68
  69 /*
  70  * compute_lowest_common_dimm_parameters()
  71  *
  72  * Determine the worst-case DIMM timing parameters from the set of DIMMs
  73  * whose parameters have been computed into the array pointed to
  74  * by dimm_params.
  75  */
  76 unsigned int
  77 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
  78                                       common_timing_params_t *outpdimm,
  79                                       unsigned int number_of_dimms)
  80 {
  81         unsigned int i, j;
  82
  83         unsigned int tCKmin_X_ps = 0;
  84         unsigned int tCKmax_ps = 0xFFFFFFFF;
  85         unsigned int tCKmax_max_ps = 0;
  86         unsigned int tRCD_ps = 0;
  87         unsigned int tRP_ps = 0;
  88         unsigned int tRAS_ps = 0;
  89         unsigned int tWR_ps = 0;
  90         unsigned int tWTR_ps = 0;
  91         unsigned int tRFC_ps = 0;
  92         unsigned int tRRD_ps = 0;
  93         unsigned int tRC_ps = 0;
  94         unsigned int refresh_rate_ps = 0;
  95         unsigned int tIS_ps = 0;
  96         unsigned int tIH_ps = 0;
  97         unsigned int tDS_ps = 0;
  98         unsigned int tDH_ps = 0;
  99         unsigned int tRTP_ps = 0;
 100         unsigned int tDQSQ_max_ps = 0;
 101         unsigned int tQHS_ps = 0;
 102
 103         unsigned int temp1, temp2;
 104         unsigned int additive_latency = 0;
 105 #if !defined(CONFIG_FSL_DDR3)
 106         const unsigned int mclk_ps = get_memory_clk_period_ps();
 107         unsigned int lowest_good_caslat;
 108         unsigned int not_ok;
 109
 110         debug("using mclk_ps = %u\n", mclk_ps);
 111 #endif
 112
 113         temp1 = 0;
 114         for (i = 0; i < number_of_dimms; i++) {
 115                 /*
 116                  * If there are no ranks on this DIMM,
 117                  * it probably doesn't exist, so skip it.
 118                  */
 119                 if (dimm_params[i].n_ranks == 0) {
 120                         temp1++;
 121                         continue;
 122                 }
 123                 if (dimm_params[i].n_ranks == 4 && i != 0) {
 124                         printf("Found Quad-rank DIMM in wrong bank, ignored."
 125                                 " Software may not run as expected.\n");
 126                         temp1++;
 127                         continue;
 128                 }
 129                 if (dimm_params[i].n_ranks == 4 && \
 130                   CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
 131                         printf("Found Quad-rank DIMM, not able to support.");
 132                         temp1++;
 133                         continue;
 134                 }
 135
 136                 /*
 137                  * Find minimum tCKmax_ps to find fastest slow speed,
 138                  * i.e., this is the slowest the whole system can go.
 139                  */
 140                 tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
 141
 142                 /* Either find maximum value to determine slowest
 143                  * speed, delay, time, period, etc */
 144                 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
 145                 tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
 146                 tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
 147                 tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
 148                 tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
 149                 tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
 150                 tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
 151                 tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
 152                 tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
 153                 tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
 154                 tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
 155                 tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
 156                 tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
 157                 tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
 158                 tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
 159                 tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
 160                 refresh_rate_ps = max(refresh_rate_ps,
 161                                       dimm_params[i].refresh_rate_ps);
 162
 163                 /*
 164                  * Find maximum tDQSQ_max_ps to find slowest.
 165                  *
 166                  * FIXME: is finding the slowest value the correct
 167                  * strategy for this parameter?
 168                  */
 169                 tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
 170         }
 171
 172         outpdimm->ndimms_present = number_of_dimms - temp1;
 173
 174         if (temp1 == number_of_dimms) {
 175                 debug("no dimms this memory controller\n");
 176                 return 0;
 177         }
 178
 179         outpdimm->tCKmin_X_ps = tCKmin_X_ps;
 180         outpdimm->tCKmax_ps = tCKmax_ps;
 181         outpdimm->tCKmax_max_ps = tCKmax_max_ps;
 182         outpdimm->tRCD_ps = tRCD_ps;
 183         outpdimm->tRP_ps = tRP_ps;
 184         outpdimm->tRAS_ps = tRAS_ps;
 185         outpdimm->tWR_ps = tWR_ps;
 186         outpdimm->tWTR_ps = tWTR_ps;
 187         outpdimm->tRFC_ps = tRFC_ps;
 188         outpdimm->tRRD_ps = tRRD_ps;
 189         outpdimm->tRC_ps = tRC_ps;
 190         outpdimm->refresh_rate_ps = refresh_rate_ps;
 191         outpdimm->tIS_ps = tIS_ps;
 192         outpdimm->tIH_ps = tIH_ps;
 193         outpdimm->tDS_ps = tDS_ps;
 194         outpdimm->tDH_ps = tDH_ps;
 195         outpdimm->tRTP_ps = tRTP_ps;
 196         outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
 197         outpdimm->tQHS_ps = tQHS_ps;
 198
 199         /* Determine common burst length for all DIMMs. */
 200         temp1 = 0xff;
 201         for (i = 0; i < number_of_dimms; i++) {
 202                 if (dimm_params[i].n_ranks) {
 203                         temp1 &= dimm_params[i].burst_lengths_bitmask;
 204                 }
 205         }
 206         outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
 207
 208         /* Determine if all DIMMs registered buffered. */
 209         temp1 = temp2 = 0;
 210         for (i = 0; i < number_of_dimms; i++) {
 211                 if (dimm_params[i].n_ranks) {
 212                         if (dimm_params[i].registered_dimm) {
 213                                 temp1 = 1;
 214                                 printf("Detected RDIMM %s\n",
 215                                         dimm_params[i].mpart);
 216                         } else {
 217                                 temp2 = 1;
 218                                 printf("Detected UDIMM %s\n",
 219                                         dimm_params[i].mpart);
 220                         }
 221                 }
 222         }
 223
 224         outpdimm->all_DIMMs_registered = 0;
 225         outpdimm->all_DIMMs_unbuffered = 0;
 226         if (temp1 && !temp2) {
 227                 outpdimm->all_DIMMs_registered = 1;
 228         } else if (!temp1 && temp2) {
 229                 outpdimm->all_DIMMs_unbuffered = 1;
 230         } else {
 231                 printf("ERROR:  Mix of registered buffered and unbuffered "
 232                                 "DIMMs detected!\n");
 233         }
 234
 235         temp1 = 0;
 236         if (outpdimm->all_DIMMs_registered)
 237                 for (j = 0; j < 16; j++) {
 238                         outpdimm->rcw[j] = dimm_params[0].rcw[j];
 239                         for (i = 1; i < number_of_dimms; i++)
 240                                 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
 241                                         temp1 = 1;
 242                                         break;
 243                                 }
 244                 }
 245
 246         if (temp1 != 0)
 247                 printf("ERROR: Mix different RDIMM detected!\n");
 248
 249 #if defined(CONFIG_FSL_DDR3)
 250         if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
 251                 return 1;
 252 #else
 253         /*
 254          * Compute a CAS latency suitable for all DIMMs
 255          *
 256          * Strategy for SPD-defined latencies: compute only
 257          * CAS latency defined by all DIMMs.
 258          */
 259
 260         /*
 261          * Step 1: find CAS latency common to all DIMMs using bitwise
 262          * operation.
 263          */
 264         temp1 = 0xFF;
 265         for (i = 0; i < number_of_dimms; i++) {
 266                 if (dimm_params[i].n_ranks) {
 267                         temp2 = 0;
 268                         temp2 |= 1 << dimm_params[i].caslat_X;
 269                         temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
 270                         temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
 271                         /*
 272                          * FIXME: If there was no entry for X-2 (X-1) in
 273                          * the SPD, then caslat_X_minus_2
 274                          * (caslat_X_minus_1) contains either 255 or
 275                          * 0xFFFFFFFF because that's what the glorious
 276                          * __ilog2 function returns for an input of 0.
 277                          * On 32-bit PowerPC, left shift counts with bit
 278                          * 26 set (that the value of 255 or 0xFFFFFFFF
 279                          * will have), cause the destination register to
 280                          * be 0.  That is why this works.
 281                          */
 282                         temp1 &= temp2;
 283                 }
 284         }
 285
 286         /*
 287          * Step 2: check each common CAS latency against tCK of each
 288          * DIMM's SPD.
 289          */
 290         lowest_good_caslat = 0;
 291         temp2 = 0;
 292         while (temp1) {
 293                 not_ok = 0;
 294                 temp2 =  __ilog2(temp1);
 295                 debug("checking common caslat = %u\n", temp2);
 296
 297                 /* Check if this CAS latency will work on all DIMMs at tCK. */
 298                 for (i = 0; i < number_of_dimms; i++) {
 299                         if (!dimm_params[i].n_ranks) {
 300                                 continue;
 301                         }
 302                         if (dimm_params[i].caslat_X == temp2) {
 303                                 if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
 304                                         debug("CL = %u ok on DIMM %u at tCK=%u"
 305                                             " ps with its tCKmin_X_ps of %u\n",
 306                                                temp2, i, mclk_ps,
 307                                                dimm_params[i].tCKmin_X_ps);
 308                                         continue;
 309                                 } else {
 310                                         not_ok++;
 311                                 }
 312                         }
 313
 314                         if (dimm_params[i].caslat_X_minus_1 == temp2) {
 315                                 unsigned int tCKmin_X_minus_1_ps
 316                                         = dimm_params[i].tCKmin_X_minus_1_ps;
 317                                 if (mclk_ps >= tCKmin_X_minus_1_ps) {
 318                                         debug("CL = %u ok on DIMM %u at "
 319                                                 "tCK=%u ps with its "
 320                                                 "tCKmin_X_minus_1_ps of %u\n",
 321                                                temp2, i, mclk_ps,
 322                                                tCKmin_X_minus_1_ps);
 323                                         continue;
 324                                 } else {
 325                                         not_ok++;
 326                                 }
 327                         }
 328
 329                         if (dimm_params[i].caslat_X_minus_2 == temp2) {
 330                                 unsigned int tCKmin_X_minus_2_ps
 331                                         = dimm_params[i].tCKmin_X_minus_2_ps;
 332                                 if (mclk_ps >= tCKmin_X_minus_2_ps) {
 333                                         debug("CL = %u ok on DIMM %u at "
 334                                                 "tCK=%u ps with its "
 335                                                 "tCKmin_X_minus_2_ps of %u\n",
 336                                                temp2, i, mclk_ps,
 337                                                tCKmin_X_minus_2_ps);
 338                                         continue;
 339                                 } else {
 340                                         not_ok++;
 341                                 }
 342                         }
 343                 }
 344
 345                 if (!not_ok) {
 346                         lowest_good_caslat = temp2;
 347                 }
 348
 349                 temp1 &= ~(1 << temp2);
 350         }
 351
 352         debug("lowest common SPD-defined CAS latency = %u\n",
 353                lowest_good_caslat);
 354         outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
 355
 356
 357         /*
 358          * Compute a common 'de-rated' CAS latency.
 359          *
 360          * The strategy here is to find the *highest* dereated cas latency
 361          * with the assumption that all of the DIMMs will support a dereated
 362          * CAS latency higher than or equal to their lowest dereated value.
 363          */
 364         temp1 = 0;
 365         for (i = 0; i < number_of_dimms; i++) {
 366                 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
 367         }
 368         outpdimm->highest_common_derated_caslat = temp1;
 369         debug("highest common dereated CAS latency = %u\n", temp1);
 370 #endif /* #if defined(CONFIG_FSL_DDR3) */
 371
 372         /* Determine if all DIMMs ECC capable. */
 373         temp1 = 1;
 374         for (i = 0; i < number_of_dimms; i++) {
 375                 if (dimm_params[i].n_ranks &&
 376                         !(dimm_params[i].edc_config & EDC_ECC)) {
 377                         temp1 = 0;
 378                         break;
 379                 }
 380         }
 381         if (temp1) {
 382                 debug("all DIMMs ECC capable\n");
 383         } else {
 384                 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
 385         }
 386         outpdimm->all_DIMMs_ECC_capable = temp1;
 387
 388 #ifndef CONFIG_FSL_DDR3
 389         /* FIXME: move to somewhere else to validate. */
 390         if (mclk_ps > tCKmax_max_ps) {
 391                 printf("Warning: some of the installed DIMMs "
 392                                 "can not operate this slowly.\n");
 393                 return 1;
 394         }
 395 #endif
 396         /*
 397          * Compute additive latency.
 398          *
 399          * For DDR1, additive latency should be 0.
 400          *
 401          * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
 402          *      which comes from Trcd, and also note that:
 403          *          add_lat + caslat must be >= 4
 404          *
 405          * For DDR3, we use the AL=0
 406          *
 407          * When to use additive latency for DDR2:
 408          *
 409          * I. Because you are using CL=3 and need to do ODT on writes and
 410          *    want functionality.
 411          *    1. Are you going to use ODT? (Does your board not have
 412          *      additional termination circuitry for DQ, DQS, DQS_,
 413          *      DM, RDQS, RDQS_ for x4/x8 configs?)
 414          *    2. If so, is your lowest supported CL going to be 3?
 415          *    3. If so, then you must set AL=1 because
 416          *
 417          *       WL >= 3 for ODT on writes
 418          *       RL = AL + CL
 419          *       WL = RL - 1
 420          *       ->
 421          *       WL = AL + CL - 1
 422          *       AL + CL - 1 >= 3
 423          *       AL + CL >= 4
 424          *  QED
 425          *
 426          *  RL >= 3 for ODT on reads
 427          *  RL = AL + CL
 428          *
 429          *  Since CL aren't usually less than 2, AL=0 is a minimum,
 430          *  so the WL-derived AL should be the  -- FIXME?
 431          *
 432          * II. Because you are using auto-precharge globally and want to
 433          *     use additive latency (posted CAS) to get more bandwidth.
 434          *     1. Are you going to use auto-precharge mode globally?
 435          *
 436          *        Use addtivie latency and compute AL to be 1 cycle less than
 437          *        tRCD, i.e. the READ or WRITE command is in the cycle
 438          *        immediately following the ACTIVATE command..
 439          *
 440          * III. Because you feel like it or want to do some sort of
 441          *      degraded-performance experiment.
 442          *     1.  Do you just want to use additive latency because you feel
 443          *         like it?
 444          *
 445          * Validation:  AL is less than tRCD, and within the other
 446          * read-to-precharge constraints.
 447          */
 448
 449         additive_latency = 0;
 450
 451 #if defined(CONFIG_FSL_DDR2)
 452         if (lowest_good_caslat < 4) {
 453                 additive_latency = (picos_to_mclk(tRCD_ps) > lowest_good_caslat)
 454                         ? picos_to_mclk(tRCD_ps) - lowest_good_caslat : 0;
 455                 if (mclk_to_picos(additive_latency) > tRCD_ps) {
 456                         additive_latency = picos_to_mclk(tRCD_ps);
 457                         debug("setting additive_latency to %u because it was "
 458                                 " greater than tRCD_ps\n", additive_latency);
 459                 }
 460         }
 461
 462 #elif defined(CONFIG_FSL_DDR3)
 463         /*
 464          * The system will not use the global auto-precharge mode.
 465          * However, it uses the page mode, so we set AL=0
 466          */
 467         additive_latency = 0;
 468 #endif
 469
 470         /*
 471          * Validate additive latency
 472          * FIXME: move to somewhere else to validate
 473          *
 474          * AL <= tRCD(min)
 475          */
 476         if (mclk_to_picos(additive_latency) > tRCD_ps) {
 477                 printf("Error: invalid additive latency exceeds tRCD(min).\n");
 478                 return 1;
 479         }
 480
 481         /*
 482          * RL = CL + AL;  RL >= 3 for ODT_RD_CFG to be enabled
 483          * WL = RL - 1;  WL >= 3 for ODT_WL_CFG to be enabled
 484          * ADD_LAT (the register) must be set to a value less
 485          * than ACTTORW if WL = 1, then AL must be set to 1
 486          * RD_TO_PRE (the register) must be set to a minimum
 487          * tRTP + AL if AL is nonzero
 488          */
 489
 490         /*
 491          * Additive latency will be applied only if the memctl option to
 492          * use it.
 493          */
 494         outpdimm->additive_latency = additive_latency;
 495
 496         debug("tCKmin_ps = %u\n", outpdimm->tCKmin_X_ps);
 497         debug("tRCD_ps   = %u\n", outpdimm->tRCD_ps);
 498         debug("tRP_ps    = %u\n", outpdimm->tRP_ps);
 499         debug("tRAS_ps   = %u\n", outpdimm->tRAS_ps);
 500         debug("tWR_ps    = %u\n", outpdimm->tWR_ps);
 501         debug("tWTR_ps   = %u\n", outpdimm->tWTR_ps);
 502         debug("tRFC_ps   = %u\n", outpdimm->tRFC_ps);
 503         debug("tRRD_ps   = %u\n", outpdimm->tRRD_ps);
 504         debug("tRC_ps    = %u\n", outpdimm->tRC_ps);
 505
 506         return 0;
 507 }