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1 /*
2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License
6  * Version 2 as published by the Free Software Foundation.
7  */
8
9 #include <common.h>
10 #include <asm/fsl_ddr_sdram.h>
11
12 #include "ddr.h"
13
14 unsigned int
15 compute_cas_latency_ddr3(const dimm_params_t *dimm_params,
16                          common_timing_params_t *outpdimm,
17                          unsigned int number_of_dimms)
18 {
19         unsigned int i;
20         unsigned int tAAmin_ps = 0;
21         unsigned int tCKmin_X_ps = 0;
22         unsigned int common_caslat;
23         unsigned int caslat_actual;
24         unsigned int retry = 16;
25         unsigned int tmp;
26         const unsigned int mclk_ps = get_memory_clk_period_ps();
27
28         /* compute the common CAS latency supported between slots */
29         tmp = dimm_params[0].caslat_X;
30         for (i = 1; i < number_of_dimms; i++)
31                  tmp &= dimm_params[i].caslat_X;
32         common_caslat = tmp;
33
34         /* compute the max tAAmin tCKmin between slots */
35         for (i = 0; i < number_of_dimms; i++) {
36                 tAAmin_ps = max(tAAmin_ps, dimm_params[i].tAA_ps);
37                 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
38         }
39         /* validate if the memory clk is in the range of dimms */
40         if (mclk_ps < tCKmin_X_ps) {
41                 printf("The DIMM max tCKmin is %d ps,"
42                         "doesn't support the MCLK cycle %d ps\n",
43                         tCKmin_X_ps, mclk_ps);
44                 return 1;
45         }
46         /* determine the acutal cas latency */
47         caslat_actual = (tAAmin_ps + mclk_ps - 1) / mclk_ps;
48         /* check if the dimms support the CAS latency */
49         while (!(common_caslat & (1 << caslat_actual)) && retry > 0) {
50                 caslat_actual++;
51                 retry--;
52         }
53         /* once the caculation of caslat_actual is completed
54          * we must verify that this CAS latency value does not
55          * exceed tAAmax, which is 20 ns for all DDR3 speed grades
56          */
57         if (caslat_actual * mclk_ps > 20000) {
58                 printf("The choosen cas latency %d is too large\n",
59                         caslat_actual);
60                 return 1;
61         }
62         outpdimm->lowest_common_SPD_caslat = caslat_actual;
63
64         return 0;
65 }
66
67 /*
68  * compute_lowest_common_dimm_parameters()
69  *
70  * Determine the worst-case DIMM timing parameters from the set of DIMMs
71  * whose parameters have been computed into the array pointed to
72  * by dimm_params.
73  */
74 unsigned int
75 compute_lowest_common_dimm_parameters(const dimm_params_t *dimm_params,
76                                       common_timing_params_t *outpdimm,
77                                       unsigned int number_of_dimms)
78 {
79         unsigned int i, j;
80
81         unsigned int tCKmin_X_ps = 0;
82         unsigned int tCKmax_ps = 0xFFFFFFFF;
83         unsigned int tCKmax_max_ps = 0;
84         unsigned int tRCD_ps = 0;
85         unsigned int tRP_ps = 0;
86         unsigned int tRAS_ps = 0;
87         unsigned int tWR_ps = 0;
88         unsigned int tWTR_ps = 0;
89         unsigned int tRFC_ps = 0;
90         unsigned int tRRD_ps = 0;
91         unsigned int tRC_ps = 0;
92         unsigned int refresh_rate_ps = 0;
93         unsigned int tIS_ps = 0;
94         unsigned int tIH_ps = 0;
95         unsigned int tDS_ps = 0;
96         unsigned int tDH_ps = 0;
97         unsigned int tRTP_ps = 0;
98         unsigned int tDQSQ_max_ps = 0;
99         unsigned int tQHS_ps = 0;
100
101         unsigned int temp1, temp2;
102         unsigned int additive_latency = 0;
103 #if !defined(CONFIG_FSL_DDR3)
104         const unsigned int mclk_ps = get_memory_clk_period_ps();
105         unsigned int lowest_good_caslat;
106         unsigned int not_ok;
107
108         debug("using mclk_ps = %u\n", mclk_ps);
109 #endif
110
111         temp1 = 0;
112         for (i = 0; i < number_of_dimms; i++) {
113                 /*
114                  * If there are no ranks on this DIMM,
115                  * it probably doesn't exist, so skip it.
116                  */
117                 if (dimm_params[i].n_ranks == 0) {
118                         temp1++;
119                         continue;
120                 }
121                 if (dimm_params[i].n_ranks == 4 && i != 0) {
122                         printf("Found Quad-rank DIMM in wrong bank, ignored."
123                                 " Software may not run as expected.\n");
124                         temp1++;
125                         continue;
126                 }
127                 if (dimm_params[i].n_ranks == 4 && \
128                   CONFIG_CHIP_SELECTS_PER_CTRL/CONFIG_DIMM_SLOTS_PER_CTLR < 4) {
129                         printf("Found Quad-rank DIMM, not able to support.");
130                         temp1++;
131                         continue;
132                 }
133
134                 /*
135                  * Find minimum tCKmax_ps to find fastest slow speed,
136                  * i.e., this is the slowest the whole system can go.
137                  */
138                 tCKmax_ps = min(tCKmax_ps, dimm_params[i].tCKmax_ps);
139
140                 /* Either find maximum value to determine slowest
141                  * speed, delay, time, period, etc */
142                 tCKmin_X_ps = max(tCKmin_X_ps, dimm_params[i].tCKmin_X_ps);
143                 tCKmax_max_ps = max(tCKmax_max_ps, dimm_params[i].tCKmax_ps);
144                 tRCD_ps = max(tRCD_ps, dimm_params[i].tRCD_ps);
145                 tRP_ps = max(tRP_ps, dimm_params[i].tRP_ps);
146                 tRAS_ps = max(tRAS_ps, dimm_params[i].tRAS_ps);
147                 tWR_ps = max(tWR_ps, dimm_params[i].tWR_ps);
148                 tWTR_ps = max(tWTR_ps, dimm_params[i].tWTR_ps);
149                 tRFC_ps = max(tRFC_ps, dimm_params[i].tRFC_ps);
150                 tRRD_ps = max(tRRD_ps, dimm_params[i].tRRD_ps);
151                 tRC_ps = max(tRC_ps, dimm_params[i].tRC_ps);
152                 tIS_ps = max(tIS_ps, dimm_params[i].tIS_ps);
153                 tIH_ps = max(tIH_ps, dimm_params[i].tIH_ps);
154                 tDS_ps = max(tDS_ps, dimm_params[i].tDS_ps);
155                 tDH_ps = max(tDH_ps, dimm_params[i].tDH_ps);
156                 tRTP_ps = max(tRTP_ps, dimm_params[i].tRTP_ps);
157                 tQHS_ps = max(tQHS_ps, dimm_params[i].tQHS_ps);
158                 refresh_rate_ps = max(refresh_rate_ps,
159                                       dimm_params[i].refresh_rate_ps);
160
161                 /*
162                  * Find maximum tDQSQ_max_ps to find slowest.
163                  *
164                  * FIXME: is finding the slowest value the correct
165                  * strategy for this parameter?
166                  */
167                 tDQSQ_max_ps = max(tDQSQ_max_ps, dimm_params[i].tDQSQ_max_ps);
168         }
169
170         outpdimm->ndimms_present = number_of_dimms - temp1;
171
172         if (temp1 == number_of_dimms) {
173                 debug("no dimms this memory controller\n");
174                 return 0;
175         }
176
177         outpdimm->tCKmin_X_ps = tCKmin_X_ps;
178         outpdimm->tCKmax_ps = tCKmax_ps;
179         outpdimm->tCKmax_max_ps = tCKmax_max_ps;
180         outpdimm->tRCD_ps = tRCD_ps;
181         outpdimm->tRP_ps = tRP_ps;
182         outpdimm->tRAS_ps = tRAS_ps;
183         outpdimm->tWR_ps = tWR_ps;
184         outpdimm->tWTR_ps = tWTR_ps;
185         outpdimm->tRFC_ps = tRFC_ps;
186         outpdimm->tRRD_ps = tRRD_ps;
187         outpdimm->tRC_ps = tRC_ps;
188         outpdimm->refresh_rate_ps = refresh_rate_ps;
189         outpdimm->tIS_ps = tIS_ps;
190         outpdimm->tIH_ps = tIH_ps;
191         outpdimm->tDS_ps = tDS_ps;
192         outpdimm->tDH_ps = tDH_ps;
193         outpdimm->tRTP_ps = tRTP_ps;
194         outpdimm->tDQSQ_max_ps = tDQSQ_max_ps;
195         outpdimm->tQHS_ps = tQHS_ps;
196
197         /* Determine common burst length for all DIMMs. */
198         temp1 = 0xff;
199         for (i = 0; i < number_of_dimms; i++) {
200                 if (dimm_params[i].n_ranks) {
201                         temp1 &= dimm_params[i].burst_lengths_bitmask;
202                 }
203         }
204         outpdimm->all_DIMMs_burst_lengths_bitmask = temp1;
205
206         /* Determine if all DIMMs registered buffered. */
207         temp1 = temp2 = 0;
208         for (i = 0; i < number_of_dimms; i++) {
209                 if (dimm_params[i].n_ranks) {
210                         if (dimm_params[i].registered_dimm)
211                                 temp1 = 1;
212                         if (!dimm_params[i].registered_dimm)
213                                 temp2 = 1;
214                 }
215         }
216
217         outpdimm->all_DIMMs_registered = 0;
218         outpdimm->all_DIMMs_unbuffered = 0;
219         if (temp1 && !temp2) {
220                 outpdimm->all_DIMMs_registered = 1;
221                 printf("Detected RDIMM(s)\n");
222         } else if (!temp1 && temp2) {
223                 outpdimm->all_DIMMs_unbuffered = 1;
224                 printf("Detected UDIMM(s)\n");
225         } else {
226                 printf("ERROR:  Mix of registered buffered and unbuffered "
227                                 "DIMMs detected!\n");
228         }
229
230         temp1 = 0;
231         if (outpdimm->all_DIMMs_registered)
232                 for (j = 0; j < 16; j++) {
233                         outpdimm->rcw[j] = dimm_params[0].rcw[j];
234                         for (i = 1; i < number_of_dimms; i++)
235                                 if (dimm_params[i].rcw[j] != dimm_params[0].rcw[j]) {
236                                         temp1 = 1;
237                                         break;
238                                 }
239                 }
240
241         if (temp1 != 0)
242                 printf("ERROR: Mix different RDIMM detected!\n");
243
244 #if defined(CONFIG_FSL_DDR3)
245         if (compute_cas_latency_ddr3(dimm_params, outpdimm, number_of_dimms))
246                 return 1;
247 #else
248         /*
249          * Compute a CAS latency suitable for all DIMMs
250          *
251          * Strategy for SPD-defined latencies: compute only
252          * CAS latency defined by all DIMMs.
253          */
254
255         /*
256          * Step 1: find CAS latency common to all DIMMs using bitwise
257          * operation.
258          */
259         temp1 = 0xFF;
260         for (i = 0; i < number_of_dimms; i++) {
261                 if (dimm_params[i].n_ranks) {
262                         temp2 = 0;
263                         temp2 |= 1 << dimm_params[i].caslat_X;
264                         temp2 |= 1 << dimm_params[i].caslat_X_minus_1;
265                         temp2 |= 1 << dimm_params[i].caslat_X_minus_2;
266                         /*
267                          * FIXME: If there was no entry for X-2 (X-1) in
268                          * the SPD, then caslat_X_minus_2
269                          * (caslat_X_minus_1) contains either 255 or
270                          * 0xFFFFFFFF because that's what the glorious
271                          * __ilog2 function returns for an input of 0.
272                          * On 32-bit PowerPC, left shift counts with bit
273                          * 26 set (that the value of 255 or 0xFFFFFFFF
274                          * will have), cause the destination register to
275                          * be 0.  That is why this works.
276                          */
277                         temp1 &= temp2;
278                 }
279         }
280
281         /*
282          * Step 2: check each common CAS latency against tCK of each
283          * DIMM's SPD.
284          */
285         lowest_good_caslat = 0;
286         temp2 = 0;
287         while (temp1) {
288                 not_ok = 0;
289                 temp2 =  __ilog2(temp1);
290                 debug("checking common caslat = %u\n", temp2);
291
292                 /* Check if this CAS latency will work on all DIMMs at tCK. */
293                 for (i = 0; i < number_of_dimms; i++) {
294                         if (!dimm_params[i].n_ranks) {
295                                 continue;
296                         }
297                         if (dimm_params[i].caslat_X == temp2) {
298                                 if (mclk_ps >= dimm_params[i].tCKmin_X_ps) {
299                                         debug("CL = %u ok on DIMM %u at tCK=%u"
300                                             " ps with its tCKmin_X_ps of %u\n",
301                                                temp2, i, mclk_ps,
302                                                dimm_params[i].tCKmin_X_ps);
303                                         continue;
304                                 } else {
305                                         not_ok++;
306                                 }
307                         }
308
309                         if (dimm_params[i].caslat_X_minus_1 == temp2) {
310                                 unsigned int tCKmin_X_minus_1_ps
311                                         = dimm_params[i].tCKmin_X_minus_1_ps;
312                                 if (mclk_ps >= tCKmin_X_minus_1_ps) {
313                                         debug("CL = %u ok on DIMM %u at "
314                                                 "tCK=%u ps with its "
315                                                 "tCKmin_X_minus_1_ps of %u\n",
316                                                temp2, i, mclk_ps,
317                                                tCKmin_X_minus_1_ps);
318                                         continue;
319                                 } else {
320                                         not_ok++;
321                                 }
322                         }
323
324                         if (dimm_params[i].caslat_X_minus_2 == temp2) {
325                                 unsigned int tCKmin_X_minus_2_ps
326                                         = dimm_params[i].tCKmin_X_minus_2_ps;
327                                 if (mclk_ps >= tCKmin_X_minus_2_ps) {
328                                         debug("CL = %u ok on DIMM %u at "
329                                                 "tCK=%u ps with its "
330                                                 "tCKmin_X_minus_2_ps of %u\n",
331                                                temp2, i, mclk_ps,
332                                                tCKmin_X_minus_2_ps);
333                                         continue;
334                                 } else {
335                                         not_ok++;
336                                 }
337                         }
338                 }
339
340                 if (!not_ok) {
341                         lowest_good_caslat = temp2;
342                 }
343
344                 temp1 &= ~(1 << temp2);
345         }
346
347         debug("lowest common SPD-defined CAS latency = %u\n",
348                lowest_good_caslat);
349         outpdimm->lowest_common_SPD_caslat = lowest_good_caslat;
350
351
352         /*
353          * Compute a common 'de-rated' CAS latency.
354          *
355          * The strategy here is to find the *highest* dereated cas latency
356          * with the assumption that all of the DIMMs will support a dereated
357          * CAS latency higher than or equal to their lowest dereated value.
358          */
359         temp1 = 0;
360         for (i = 0; i < number_of_dimms; i++) {
361                 temp1 = max(temp1, dimm_params[i].caslat_lowest_derated);
362         }
363         outpdimm->highest_common_derated_caslat = temp1;
364         debug("highest common dereated CAS latency = %u\n", temp1);
365 #endif /* #if defined(CONFIG_FSL_DDR3) */
366
367         /* Determine if all DIMMs ECC capable. */
368         temp1 = 1;
369         for (i = 0; i < number_of_dimms; i++) {
370                 if (dimm_params[i].n_ranks &&
371                         !(dimm_params[i].edc_config & EDC_ECC)) {
372                         temp1 = 0;
373                         break;
374                 }
375         }
376         if (temp1) {
377                 debug("all DIMMs ECC capable\n");
378         } else {
379                 debug("Warning: not all DIMMs ECC capable, cant enable ECC\n");
380         }
381         outpdimm->all_DIMMs_ECC_capable = temp1;
382
383 #ifndef CONFIG_FSL_DDR3
384         /* FIXME: move to somewhere else to validate. */
385         if (mclk_ps > tCKmax_max_ps) {
386                 printf("Warning: some of the installed DIMMs "
387                                 "can not operate this slowly.\n");
388                 return 1;
389         }
390 #endif
391         /*
392          * Compute additive latency.
393          *
394          * For DDR1, additive latency should be 0.
395          *
396          * For DDR2, with ODT enabled, use "a value" less than ACTTORW,
397          *      which comes from Trcd, and also note that:
398          *          add_lat + caslat must be >= 4
399          *
400          * For DDR3, we use the AL=0
401          *
402          * When to use additive latency for DDR2:
403          *
404          * I. Because you are using CL=3 and need to do ODT on writes and
405          *    want functionality.
406          *    1. Are you going to use ODT? (Does your board not have
407          *      additional termination circuitry for DQ, DQS, DQS_,
408          *      DM, RDQS, RDQS_ for x4/x8 configs?)
409          *    2. If so, is your lowest supported CL going to be 3?
410          *    3. If so, then you must set AL=1 because
411          *
412          *       WL >= 3 for ODT on writes
413          *       RL = AL + CL
414          *       WL = RL - 1
415          *       ->
416          *       WL = AL + CL - 1
417          *       AL + CL - 1 >= 3
418          *       AL + CL >= 4
419          *  QED
420          *
421          *  RL >= 3 for ODT on reads
422          *  RL = AL + CL
423          *
424          *  Since CL aren't usually less than 2, AL=0 is a minimum,
425          *  so the WL-derived AL should be the  -- FIXME?
426          *
427          * II. Because you are using auto-precharge globally and want to
428          *     use additive latency (posted CAS) to get more bandwidth.
429          *     1. Are you going to use auto-precharge mode globally?
430          *
431          *        Use addtivie latency and compute AL to be 1 cycle less than
432          *        tRCD, i.e. the READ or WRITE command is in the cycle
433          *        immediately following the ACTIVATE command..
434          *
435          * III. Because you feel like it or want to do some sort of
436          *      degraded-performance experiment.
437          *     1.  Do you just want to use additive latency because you feel
438          *         like it?
439          *
440          * Validation:  AL is less than tRCD, and within the other
441          * read-to-precharge constraints.
442          */
443
444         additive_latency = 0;
445
446 #if defined(CONFIG_FSL_DDR2)
447         if (lowest_good_caslat < 4) {
448                 additive_latency = picos_to_mclk(tRCD_ps) - lowest_good_caslat;
449                 if (mclk_to_picos(additive_latency) > tRCD_ps) {
450                         additive_latency = picos_to_mclk(tRCD_ps);
451                         debug("setting additive_latency to %u because it was "
452                                 " greater than tRCD_ps\n", additive_latency);
453                 }
454         }
455
456 #elif defined(CONFIG_FSL_DDR3)
457         /*
458          * The system will not use the global auto-precharge mode.
459          * However, it uses the page mode, so we set AL=0
460          */
461         additive_latency = 0;
462 #endif
463
464         /*
465          * Validate additive latency
466          * FIXME: move to somewhere else to validate
467          *
468          * AL <= tRCD(min)
469          */
470         if (mclk_to_picos(additive_latency) > tRCD_ps) {
471                 printf("Error: invalid additive latency exceeds tRCD(min).\n");
472                 return 1;
473         }
474
475         /*
476          * RL = CL + AL;  RL >= 3 for ODT_RD_CFG to be enabled
477          * WL = RL - 1;  WL >= 3 for ODT_WL_CFG to be enabled
478          * ADD_LAT (the register) must be set to a value less
479          * than ACTTORW if WL = 1, then AL must be set to 1
480          * RD_TO_PRE (the register) must be set to a minimum
481          * tRTP + AL if AL is nonzero
482          */
483
484         /*
485          * Additive latency will be applied only if the memctl option to
486          * use it.
487          */
488         outpdimm->additive_latency = additive_latency;
489
490         return 0;
491 }