arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c
   3  * This SPD DDR detection code supports IBM/AMCC PPC44x cpu with a
   4  * DDR controller. Those are 440GP/GX/EP/GR.
   5  *
   6  * (C) Copyright 2001
   7  * Bill Hunter, Wave 7 Optics, williamhunter@attbi.com
   8  *
   9  * Based on code by:
  10  *
  11  * Kenneth Johansson ,Ericsson AB.
  12  * kenneth.johansson@etx.ericsson.se
  13  *
  14  * hacked up by bill hunter. fixed so we could run before
  15  * serial_init and console_init. previous version avoided this by
  16  * running out of cache memory during serial/console init, then running
  17  * this code later.
  18  *
  19  * (C) Copyright 2002
  20  * Jun Gu, Artesyn Technology, jung@artesyncp.com
  21  * Support for AMCC 440 based on OpenBIOS draminit.c from IBM.
  22  *
  23  * (C) Copyright 2005-2007
  24  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  25  *
  26  * See file CREDITS for list of people who contributed to this
  27  * project.
  28  *
  29  * This program is free software; you can redistribute it and/or
  30  * modify it under the terms of the GNU General Public License as
  31  * published by the Free Software Foundation; either version 2 of
  32  * the License, or (at your option) any later version.
  33  *
  34  * This program is distributed in the hope that it will be useful,
  35  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  36  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  37  * GNU General Public License for more details.
  38  *
  39  * You should have received a copy of the GNU General Public License
  40  * along with this program; if not, write to the Free Software
  41  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  42  * MA 02111-1307 USA
  43  */
  44
  45 /* define DEBUG for debugging output (obviously ;-)) */
  46 #if 0
  47 #define DEBUG
  48 #endif
  49
  50 #include <common.h>
  51 #include <asm/processor.h>
  52 #include <i2c.h>
  53 #include <asm/ppc4xx.h>
  54 #include <asm/mmu.h>
  55
  56 #include "ecc.h"
  57
  58 #if defined(CONFIG_SPD_EEPROM) &&                                       \
  59         (defined(CONFIG_440GP) || defined(CONFIG_440GX) ||              \
  60          defined(CONFIG_440EP) || defined(CONFIG_440GR))
  61
  62 /*
  63  * Set default values
  64  */
  65 #define ONE_BILLION     1000000000
  66
  67 /*
  68  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  69  */
  70 void __spd_ddr_init_hang (void)
  71 {
  72         hang ();
  73 }
  74 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
  75
  76 /*-----------------------------------------------------------------------------+
  77   |  General Definition
  78   +-----------------------------------------------------------------------------*/
  79 #define DEFAULT_SPD_ADDR1       0x53
  80 #define DEFAULT_SPD_ADDR2       0x52
  81 #define MAXBANKS                4               /* at most 4 dimm banks */
  82 #define MAX_SPD_BYTES           256
  83 #define NUMHALFCYCLES           4
  84 #define NUMMEMTESTS             8
  85 #define NUMMEMWORDS             8
  86 #define MAXBXCR                 4
  87
  88 /*
  89  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  90  * region. Right now the cache should still be disabled in U-Boot because of the
  91  * EMAC driver, that need it's buffer descriptor to be located in non cached
  92  * memory.
  93  *
  94  * If at some time this restriction doesn't apply anymore, just define
  95  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  96  * everything correctly.
  97  */
  98 #ifdef CONFIG_4xx_DCACHE
  99 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
 100 #else
 101 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
 102 #endif
 103
 104 /* bank_parms is used to sort the bank sizes by descending order */
 105 struct bank_param {
 106         unsigned long cr;
 107         unsigned long bank_size_bytes;
 108 };
 109
 110 typedef struct bank_param BANKPARMS;
 111
 112 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
 113 extern const unsigned char cfg_simulate_spd_eeprom[128];
 114 #endif
 115
 116 static unsigned char spd_read(uchar chip, uint addr);
 117 static void get_spd_info(unsigned long *dimm_populated,
 118                          unsigned char *iic0_dimm_addr,
 119                          unsigned long num_dimm_banks);
 120 static void check_mem_type(unsigned long *dimm_populated,
 121                            unsigned char *iic0_dimm_addr,
 122                            unsigned long num_dimm_banks);
 123 static void check_volt_type(unsigned long *dimm_populated,
 124                             unsigned char *iic0_dimm_addr,
 125                             unsigned long num_dimm_banks);
 126 static void program_cfg0(unsigned long *dimm_populated,
 127                          unsigned char *iic0_dimm_addr,
 128                          unsigned long  num_dimm_banks);
 129 static void program_cfg1(unsigned long *dimm_populated,
 130                          unsigned char *iic0_dimm_addr,
 131                          unsigned long num_dimm_banks);
 132 static void program_rtr(unsigned long *dimm_populated,
 133                         unsigned char *iic0_dimm_addr,
 134                         unsigned long num_dimm_banks);
 135 static void program_tr0(unsigned long *dimm_populated,
 136                         unsigned char *iic0_dimm_addr,
 137                         unsigned long num_dimm_banks);
 138 static void program_tr1(void);
 139
 140 static unsigned long program_bxcr(unsigned long *dimm_populated,
 141                                   unsigned char *iic0_dimm_addr,
 142                                   unsigned long num_dimm_banks);
 143
 144 /*
 145  * This function is reading data from the DIMM module EEPROM over the SPD bus
 146  * and uses that to program the sdram controller.
 147  *
 148  * This works on boards that has the same schematics that the AMCC walnut has.
 149  *
 150  * BUG: Don't handle ECC memory
 151  * BUG: A few values in the TR register is currently hardcoded
 152  */
 153 long int spd_sdram(void) {
 154         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 155         unsigned long dimm_populated[sizeof(iic0_dimm_addr)];
 156         unsigned long total_size;
 157         unsigned long cfg0;
 158         unsigned long mcsts;
 159         unsigned long num_dimm_banks;               /* on board dimm banks */
 160
 161         num_dimm_banks = sizeof(iic0_dimm_addr);
 162
 163         /*
 164          * Make sure I2C controller is initialized
 165          * before continuing.
 166          */
 167         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
 168
 169         /*
 170          * Read the SPD information using I2C interface. Check to see if the
 171          * DIMM slots are populated.
 172          */
 173         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 174
 175         /*
 176          * Check the memory type for the dimms plugged.
 177          */
 178         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 179
 180         /*
 181          * Check the voltage type for the dimms plugged.
 182          */
 183         check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 184
 185 #if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
 186         /*
 187          * Soft-reset SDRAM controller.
 188          */
 189         mtsdr(SDR0_SRST, SDR0_SRST_DMC);
 190         mtsdr(SDR0_SRST, 0x00000000);
 191 #endif
 192
 193         /*
 194          * program 440GP SDRAM controller options (SDRAM0_CFG0)
 195          */
 196         program_cfg0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 197
 198         /*
 199          * program 440GP SDRAM controller options (SDRAM0_CFG1)
 200          */
 201         program_cfg1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 202
 203         /*
 204          * program SDRAM refresh register (SDRAM0_RTR)
 205          */
 206         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 207
 208         /*
 209          * program SDRAM Timing Register 0 (SDRAM0_TR0)
 210          */
 211         program_tr0(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 212
 213         /*
 214          * program the BxCR registers to find out total sdram installed
 215          */
 216         total_size = program_bxcr(dimm_populated, iic0_dimm_addr,
 217                                   num_dimm_banks);
 218
 219 #ifdef CONFIG_PROG_SDRAM_TLB /* this define should eventually be removed */
 220         /* and program tlb entries for this size (dynamic) */
 221         program_tlb(0, 0, total_size, MY_TLB_WORD2_I_ENABLE);
 222 #endif
 223
 224         /*
 225          * program SDRAM Clock Timing Register (SDRAM0_CLKTR)
 226          */
 227         mtsdram(SDRAM0_CLKTR, 0x40000000);
 228
 229         /*
 230          * delay to ensure 200 usec has elapsed
 231          */
 232         udelay(400);
 233
 234         /*
 235          * enable the memory controller
 236          */
 237         mfsdram(SDRAM0_CFG0, cfg0);
 238         mtsdram(SDRAM0_CFG0, cfg0 | SDRAM_CFG0_DCEN);
 239
 240         /*
 241          * wait for SDRAM_CFG0_DC_EN to complete
 242          */
 243         while (1) {
 244                 mfsdram(SDRAM0_MCSTS, mcsts);
 245                 if ((mcsts & SDRAM_MCSTS_MRSC) != 0)
 246                         break;
 247         }
 248
 249         /*
 250          * program SDRAM Timing Register 1, adding some delays
 251          */
 252         program_tr1();
 253
 254 #ifdef CONFIG_DDR_ECC
 255         /*
 256          * If ecc is enabled, initialize the parity bits.
 257          */
 258         ecc_init(CONFIG_SYS_SDRAM_BASE, total_size);
 259 #endif
 260
 261         return total_size;
 262 }
 263
 264 static unsigned char spd_read(uchar chip, uint addr)
 265 {
 266         unsigned char data[2];
 267
 268 #ifdef CONFIG_SYS_SIMULATE_SPD_EEPROM
 269         if (chip == CONFIG_SYS_SIMULATE_SPD_EEPROM) {
 270                 /*
 271                  * Onboard spd eeprom requested -> simulate values
 272                  */
 273                 return cfg_simulate_spd_eeprom[addr];
 274         }
 275 #endif /* CONFIG_SYS_SIMULATE_SPD_EEPROM */
 276
 277         if (i2c_probe(chip) == 0) {
 278                 if (i2c_read(chip, addr, 1, data, 1) == 0) {
 279                         return data[0];
 280                 }
 281         }
 282
 283         return 0;
 284 }
 285
 286 static void get_spd_info(unsigned long *dimm_populated,
 287                          unsigned char *iic0_dimm_addr,
 288                          unsigned long num_dimm_banks)
 289 {
 290         unsigned long dimm_num;
 291         unsigned long dimm_found;
 292         unsigned char num_of_bytes;
 293         unsigned char total_size;
 294
 295         dimm_found = false;
 296         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 297                 num_of_bytes = 0;
 298                 total_size = 0;
 299
 300                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 301                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 302
 303                 if ((num_of_bytes != 0) && (total_size != 0)) {
 304                         dimm_populated[dimm_num] = true;
 305                         dimm_found = true;
 306                         debug("DIMM slot %lu: populated\n", dimm_num);
 307                 } else {
 308                         dimm_populated[dimm_num] = false;
 309                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 310                 }
 311         }
 312
 313         if (dimm_found == false) {
 314                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 315                 spd_ddr_init_hang ();
 316         }
 317 }
 318
 319 static void check_mem_type(unsigned long *dimm_populated,
 320                            unsigned char *iic0_dimm_addr,
 321                            unsigned long num_dimm_banks)
 322 {
 323         unsigned long dimm_num;
 324         unsigned char dimm_type;
 325
 326         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 327                 if (dimm_populated[dimm_num] == true) {
 328                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 329                         switch (dimm_type) {
 330                         case 7:
 331                                 debug("DIMM slot %lu: DDR SDRAM detected\n", dimm_num);
 332                                 break;
 333                         default:
 334                                 printf("ERROR: Unsupported DIMM detected in slot %lu.\n",
 335                                        dimm_num);
 336                                 printf("Only DDR SDRAM DIMMs are supported.\n");
 337                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 338                                 spd_ddr_init_hang ();
 339                                 break;
 340                         }
 341                 }
 342         }
 343 }
 344
 345 static void check_volt_type(unsigned long *dimm_populated,
 346                             unsigned char *iic0_dimm_addr,
 347                             unsigned long num_dimm_banks)
 348 {
 349         unsigned long dimm_num;
 350         unsigned long voltage_type;
 351
 352         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 353                 if (dimm_populated[dimm_num] == true) {
 354                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 355                         if (voltage_type != 0x04) {
 356                                 printf("ERROR: DIMM %lu with unsupported voltage level.\n",
 357                                        dimm_num);
 358                                 spd_ddr_init_hang ();
 359                         } else {
 360                                 debug("DIMM %lu voltage level supported.\n", dimm_num);
 361                         }
 362                         break;
 363                 }
 364         }
 365 }
 366
 367 static void program_cfg0(unsigned long *dimm_populated,
 368                          unsigned char *iic0_dimm_addr,
 369                          unsigned long num_dimm_banks)
 370 {
 371         unsigned long dimm_num;
 372         unsigned long cfg0;
 373         unsigned long ecc_enabled;
 374         unsigned char ecc;
 375         unsigned char attributes;
 376         unsigned long data_width;
 377
 378         /*
 379          * get Memory Controller Options 0 data
 380          */
 381         mfsdram(SDRAM0_CFG0, cfg0);
 382
 383         /*
 384          * clear bits
 385          */
 386         cfg0 &= ~(SDRAM_CFG0_DCEN | SDRAM_CFG0_MCHK_MASK |
 387                   SDRAM_CFG0_RDEN | SDRAM_CFG0_PMUD |
 388                   SDRAM_CFG0_DMWD_MASK |
 389                   SDRAM_CFG0_UIOS_MASK | SDRAM_CFG0_PDP);
 390
 391
 392         /*
 393          * FIXME: assume the DDR SDRAMs in both banks are the same
 394          */
 395         ecc_enabled = true;
 396         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 397                 if (dimm_populated[dimm_num] == true) {
 398                         ecc = spd_read(iic0_dimm_addr[dimm_num], 11);
 399                         if (ecc != 0x02) {
 400                                 ecc_enabled = false;
 401                         }
 402
 403                         /*
 404                          * program Registered DIMM Enable
 405                          */
 406                         attributes = spd_read(iic0_dimm_addr[dimm_num], 21);
 407                         if ((attributes & 0x02) != 0x00) {
 408                                 cfg0 |= SDRAM_CFG0_RDEN;
 409                         }
 410
 411                         /*
 412                          * program DDR SDRAM Data Width
 413                          */
 414                         data_width =
 415                                 (unsigned long)spd_read(iic0_dimm_addr[dimm_num],6) +
 416                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num],7)) << 8);
 417                         if (data_width == 64 || data_width == 72) {
 418                                 cfg0 |= SDRAM_CFG0_DMWD_64;
 419                         } else if (data_width == 32 || data_width == 40) {
 420                                 cfg0 |= SDRAM_CFG0_DMWD_32;
 421                         } else {
 422                                 printf("WARNING: DIMM with datawidth of %lu bits.\n",
 423                                        data_width);
 424                                 printf("Only DIMMs with 32 or 64 bit datawidths supported.\n");
 425                                 spd_ddr_init_hang ();
 426                         }
 427                         break;
 428                 }
 429         }
 430
 431         /*
 432          * program Memory Data Error Checking
 433          */
 434         if (ecc_enabled == true) {
 435                 cfg0 |= SDRAM_CFG0_MCHK_GEN;
 436         } else {
 437                 cfg0 |= SDRAM_CFG0_MCHK_NON;
 438         }
 439
 440         /*
 441          * program Page Management Unit (0 == enabled)
 442          */
 443         cfg0 &= ~SDRAM_CFG0_PMUD;
 444
 445         /*
 446          * program Memory Controller Options 0
 447          * Note: DCEN must be enabled after all DDR SDRAM controller
 448          * configuration registers get initialized.
 449          */
 450         mtsdram(SDRAM0_CFG0, cfg0);
 451 }
 452
 453 static void program_cfg1(unsigned long *dimm_populated,
 454                          unsigned char *iic0_dimm_addr,
 455                          unsigned long num_dimm_banks)
 456 {
 457         unsigned long cfg1;
 458         mfsdram(SDRAM0_CFG1, cfg1);
 459
 460         /*
 461          * Self-refresh exit, disable PM
 462          */
 463         cfg1 &= ~(SDRAM_CFG1_SRE | SDRAM_CFG1_PMEN);
 464
 465         /*
 466          * program Memory Controller Options 1
 467          */
 468         mtsdram(SDRAM0_CFG1, cfg1);
 469 }
 470
 471 static void program_rtr(unsigned long *dimm_populated,
 472                         unsigned char *iic0_dimm_addr,
 473                         unsigned long num_dimm_banks)
 474 {
 475         unsigned long dimm_num;
 476         unsigned long bus_period_x_10;
 477         unsigned long refresh_rate = 0;
 478         unsigned char refresh_rate_type;
 479         unsigned long refresh_interval;
 480         unsigned long sdram_rtr;
 481         PPC4xx_SYS_INFO sys_info;
 482
 483         /*
 484          * get the board info
 485          */
 486         get_sys_info(&sys_info);
 487         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 488
 489         for (dimm_num = 0;  dimm_num < num_dimm_banks; dimm_num++) {
 490                 if (dimm_populated[dimm_num] == true) {
 491                         refresh_rate_type = 0x7F & spd_read(iic0_dimm_addr[dimm_num], 12);
 492                         switch (refresh_rate_type) {
 493                         case 0x00:
 494                                 refresh_rate = 15625;
 495                                 break;
 496                         case 0x01:
 497                                 refresh_rate = 15625/4;
 498                                 break;
 499                         case 0x02:
 500                                 refresh_rate = 15625/2;
 501                                 break;
 502                         case 0x03:
 503                                 refresh_rate = 15626*2;
 504                                 break;
 505                         case 0x04:
 506                                 refresh_rate = 15625*4;
 507                                 break;
 508                         case 0x05:
 509                                 refresh_rate = 15625*8;
 510                                 break;
 511                         default:
 512                                 printf("ERROR: DIMM %lu, unsupported refresh rate/type.\n",
 513                                        dimm_num);
 514                                 printf("Replace the DIMM module with a supported DIMM.\n");
 515                                 break;
 516                         }
 517
 518                         break;
 519                 }
 520         }
 521
 522         refresh_interval = refresh_rate * 10 / bus_period_x_10;
 523         sdram_rtr = (refresh_interval & 0x3ff8) <<  16;
 524
 525         /*
 526          * program Refresh Timer Register (SDRAM0_RTR)
 527          */
 528         mtsdram(SDRAM0_RTR, sdram_rtr);
 529 }
 530
 531 static void program_tr0(unsigned long *dimm_populated,
 532                          unsigned char *iic0_dimm_addr,
 533                          unsigned long num_dimm_banks)
 534 {
 535         unsigned long dimm_num;
 536         unsigned long tr0;
 537         unsigned char wcsbc;
 538         unsigned char t_rp_ns;
 539         unsigned char t_rcd_ns;
 540         unsigned char t_ras_ns;
 541         unsigned long t_rp_clk;
 542         unsigned long t_ras_rcd_clk;
 543         unsigned long t_rcd_clk;
 544         unsigned long t_rfc_clk;
 545         unsigned long plb_check;
 546         unsigned char cas_bit;
 547         unsigned long cas_index;
 548         unsigned char cas_2_0_available;
 549         unsigned char cas_2_5_available;
 550         unsigned char cas_3_0_available;
 551         unsigned long cycle_time_ns_x_10[3];
 552         unsigned long tcyc_3_0_ns_x_10;
 553         unsigned long tcyc_2_5_ns_x_10;
 554         unsigned long tcyc_2_0_ns_x_10;
 555         unsigned long tcyc_reg;
 556         unsigned long bus_period_x_10;
 557         PPC4xx_SYS_INFO sys_info;
 558         unsigned long residue;
 559
 560         /*
 561          * get the board info
 562          */
 563         get_sys_info(&sys_info);
 564         bus_period_x_10 = ONE_BILLION / (sys_info.freqPLB / 10);
 565
 566         /*
 567          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
 568          */
 569         mfsdram(SDRAM0_TR0, tr0);
 570         tr0 &= ~(SDRAM_TR0_SDWR_MASK | SDRAM_TR0_SDWD_MASK |
 571                  SDRAM_TR0_SDCL_MASK | SDRAM_TR0_SDPA_MASK |
 572                  SDRAM_TR0_SDCP_MASK | SDRAM_TR0_SDLD_MASK |
 573                  SDRAM_TR0_SDRA_MASK | SDRAM_TR0_SDRD_MASK);
 574
 575         /*
 576          * initialization
 577          */
 578         wcsbc = 0;
 579         t_rp_ns = 0;
 580         t_rcd_ns = 0;
 581         t_ras_ns = 0;
 582         cas_2_0_available = true;
 583         cas_2_5_available = true;
 584         cas_3_0_available = true;
 585         tcyc_2_0_ns_x_10 = 0;
 586         tcyc_2_5_ns_x_10 = 0;
 587         tcyc_3_0_ns_x_10 = 0;
 588
 589         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 590                 if (dimm_populated[dimm_num] == true) {
 591                         wcsbc = spd_read(iic0_dimm_addr[dimm_num], 15);
 592                         t_rp_ns  = spd_read(iic0_dimm_addr[dimm_num], 27) >> 2;
 593                         t_rcd_ns = spd_read(iic0_dimm_addr[dimm_num], 29) >> 2;
 594                         t_ras_ns = spd_read(iic0_dimm_addr[dimm_num], 30);
 595                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
 596
 597                         for (cas_index = 0; cas_index < 3; cas_index++) {
 598                                 switch (cas_index) {
 599                                 case 0:
 600                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 601                                         break;
 602                                 case 1:
 603                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
 604                                         break;
 605                                 default:
 606                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
 607                                         break;
 608                                 }
 609
 610                                 if ((tcyc_reg & 0x0F) >= 10) {
 611                                         printf("ERROR: Tcyc incorrect for DIMM in slot %lu\n",
 612                                                dimm_num);
 613                                         spd_ddr_init_hang ();
 614                                 }
 615
 616                                 cycle_time_ns_x_10[cas_index] =
 617                                         (((tcyc_reg & 0xF0) >> 4) * 10) + (tcyc_reg & 0x0F);
 618                         }
 619
 620                         cas_index = 0;
 621
 622                         if ((cas_bit & 0x80) != 0) {
 623                                 cas_index += 3;
 624                         } else if ((cas_bit & 0x40) != 0) {
 625                                 cas_index += 2;
 626                         } else if ((cas_bit & 0x20) != 0) {
 627                                 cas_index += 1;
 628                         }
 629
 630                         if (((cas_bit & 0x10) != 0) && (cas_index < 3)) {
 631                                 tcyc_3_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 632                                 cas_index++;
 633                         } else {
 634                                 if (cas_index != 0) {
 635                                         cas_index++;
 636                                 }
 637                                 cas_3_0_available = false;
 638                         }
 639
 640                         if (((cas_bit & 0x08) != 0) || (cas_index < 3)) {
 641                                 tcyc_2_5_ns_x_10 = cycle_time_ns_x_10[cas_index];
 642                                 cas_index++;
 643                         } else {
 644                                 if (cas_index != 0) {
 645                                         cas_index++;
 646                                 }
 647                                 cas_2_5_available = false;
 648                         }
 649
 650                         if (((cas_bit & 0x04) != 0) || (cas_index < 3)) {
 651                                 tcyc_2_0_ns_x_10 = cycle_time_ns_x_10[cas_index];
 652                                 cas_index++;
 653                         } else {
 654                                 if (cas_index != 0) {
 655                                         cas_index++;
 656                                 }
 657                                 cas_2_0_available = false;
 658                         }
 659
 660                         break;
 661                 }
 662         }
 663
 664         /*
 665          * Program SD_WR and SD_WCSBC fields
 666          */
 667         tr0 |= SDRAM_TR0_SDWR_2_CLK;                /* Write Recovery: 2 CLK */
 668         switch (wcsbc) {
 669         case 0:
 670                 tr0 |= SDRAM_TR0_SDWD_0_CLK;
 671                 break;
 672         default:
 673                 tr0 |= SDRAM_TR0_SDWD_1_CLK;
 674                 break;
 675         }
 676
 677         /*
 678          * Program SD_CASL field
 679          */
 680         if ((cas_2_0_available == true) &&
 681             (bus_period_x_10 >= tcyc_2_0_ns_x_10)) {
 682                 tr0 |= SDRAM_TR0_SDCL_2_0_CLK;
 683         } else if ((cas_2_5_available == true) &&
 684                  (bus_period_x_10 >= tcyc_2_5_ns_x_10)) {
 685                 tr0 |= SDRAM_TR0_SDCL_2_5_CLK;
 686         } else if ((cas_3_0_available == true) &&
 687                  (bus_period_x_10 >= tcyc_3_0_ns_x_10)) {
 688                 tr0 |= SDRAM_TR0_SDCL_3_0_CLK;
 689         } else {
 690                 printf("ERROR: No supported CAS latency with the installed DIMMs.\n");
 691                 printf("Only CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
 692                 printf("Make sure the PLB speed is within the supported range.\n");
 693                 spd_ddr_init_hang ();
 694         }
 695
 696         /*
 697          * Calculate Trp in clock cycles and round up if necessary
 698          * Program SD_PTA field
 699          */
 700         t_rp_clk = sys_info.freqPLB * t_rp_ns / ONE_BILLION;
 701         plb_check = ONE_BILLION * t_rp_clk / t_rp_ns;
 702         if (sys_info.freqPLB != plb_check) {
 703                 t_rp_clk++;
 704         }
 705         switch ((unsigned long)t_rp_clk) {
 706         case 0:
 707         case 1:
 708         case 2:
 709                 tr0 |= SDRAM_TR0_SDPA_2_CLK;
 710                 break;
 711         case 3:
 712                 tr0 |= SDRAM_TR0_SDPA_3_CLK;
 713                 break;
 714         default:
 715                 tr0 |= SDRAM_TR0_SDPA_4_CLK;
 716                 break;
 717         }
 718
 719         /*
 720          * Program SD_CTP field
 721          */
 722         t_ras_rcd_clk = sys_info.freqPLB * (t_ras_ns - t_rcd_ns) / ONE_BILLION;
 723         plb_check = ONE_BILLION * t_ras_rcd_clk / (t_ras_ns - t_rcd_ns);
 724         if (sys_info.freqPLB != plb_check) {
 725                 t_ras_rcd_clk++;
 726         }
 727         switch (t_ras_rcd_clk) {
 728         case 0:
 729         case 1:
 730         case 2:
 731                 tr0 |= SDRAM_TR0_SDCP_2_CLK;
 732                 break;
 733         case 3:
 734                 tr0 |= SDRAM_TR0_SDCP_3_CLK;
 735                 break;
 736         case 4:
 737                 tr0 |= SDRAM_TR0_SDCP_4_CLK;
 738                 break;
 739         default:
 740                 tr0 |= SDRAM_TR0_SDCP_5_CLK;
 741                 break;
 742         }
 743
 744         /*
 745          * Program SD_LDF field
 746          */
 747         tr0 |= SDRAM_TR0_SDLD_2_CLK;
 748
 749         /*
 750          * Program SD_RFTA field
 751          * FIXME tRFC hardcoded as 75 nanoseconds
 752          */
 753         t_rfc_clk = sys_info.freqPLB / (ONE_BILLION / 75);
 754         residue = sys_info.freqPLB % (ONE_BILLION / 75);
 755         if (residue >= (ONE_BILLION / 150)) {
 756                 t_rfc_clk++;
 757         }
 758         switch (t_rfc_clk) {
 759         case 0:
 760         case 1:
 761         case 2:
 762         case 3:
 763         case 4:
 764         case 5:
 765         case 6:
 766                 tr0 |= SDRAM_TR0_SDRA_6_CLK;
 767                 break;
 768         case 7:
 769                 tr0 |= SDRAM_TR0_SDRA_7_CLK;
 770                 break;
 771         case 8:
 772                 tr0 |= SDRAM_TR0_SDRA_8_CLK;
 773                 break;
 774         case 9:
 775                 tr0 |= SDRAM_TR0_SDRA_9_CLK;
 776                 break;
 777         case 10:
 778                 tr0 |= SDRAM_TR0_SDRA_10_CLK;
 779                 break;
 780         case 11:
 781                 tr0 |= SDRAM_TR0_SDRA_11_CLK;
 782                 break;
 783         case 12:
 784                 tr0 |= SDRAM_TR0_SDRA_12_CLK;
 785                 break;
 786         default:
 787                 tr0 |= SDRAM_TR0_SDRA_13_CLK;
 788                 break;
 789         }
 790
 791         /*
 792          * Program SD_RCD field
 793          */
 794         t_rcd_clk = sys_info.freqPLB * t_rcd_ns / ONE_BILLION;
 795         plb_check = ONE_BILLION * t_rcd_clk / t_rcd_ns;
 796         if (sys_info.freqPLB != plb_check) {
 797                 t_rcd_clk++;
 798         }
 799         switch (t_rcd_clk) {
 800         case 0:
 801         case 1:
 802         case 2:
 803                 tr0 |= SDRAM_TR0_SDRD_2_CLK;
 804                 break;
 805         case 3:
 806                 tr0 |= SDRAM_TR0_SDRD_3_CLK;
 807                 break;
 808         default:
 809                 tr0 |= SDRAM_TR0_SDRD_4_CLK;
 810                 break;
 811         }
 812
 813         debug("tr0: %lx\n", tr0);
 814         mtsdram(SDRAM0_TR0, tr0);
 815 }
 816
 817 static int short_mem_test(void)
 818 {
 819         unsigned long i, j;
 820         unsigned long bxcr_num;
 821         unsigned long *membase;
 822         const unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
 823                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
 824                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
 825                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
 826                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
 827                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
 828                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
 829                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
 830                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
 831                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
 832                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
 833                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
 834                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
 835                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
 836                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
 837                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
 838                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55}};
 839
 840         for (bxcr_num = 0; bxcr_num < MAXBXCR; bxcr_num++) {
 841                 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bxcr_num << 2));
 842                 if ((mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBE) == SDRAM_BXCR_SDBE) {
 843                         /* Bank is enabled */
 844                         membase = (unsigned long*)
 845                                 (mfdcr(SDRAM0_CFGDATA) & SDRAM_BXCR_SDBA_MASK);
 846
 847                         /*
 848                          * Run the short memory test
 849                          */
 850                         for (i = 0; i < NUMMEMTESTS; i++) {
 851                                 for (j = 0; j < NUMMEMWORDS; j++) {
 852                                         /* printf("bank enabled base:%x\n", &membase[j]); */
 853                                         membase[j] = test[i][j];
 854                                         ppcDcbf((unsigned long)&(membase[j]));
 855                                 }
 856
 857                                 for (j = 0; j < NUMMEMWORDS; j++) {
 858                                         if (membase[j] != test[i][j]) {
 859                                                 ppcDcbf((unsigned long)&(membase[j]));
 860                                                 return 0;
 861                                         }
 862                                         ppcDcbf((unsigned long)&(membase[j]));
 863                                 }
 864
 865                                 if (j < NUMMEMWORDS)
 866                                         return 0;
 867                         }
 868
 869                         /*
 870                          * see if the rdclt value passed
 871                          */
 872                         if (i < NUMMEMTESTS)
 873                                 return 0;
 874                 }
 875         }
 876
 877         return 1;
 878 }
 879
 880 static void program_tr1(void)
 881 {
 882         unsigned long tr0;
 883         unsigned long tr1;
 884         unsigned long cfg0;
 885         unsigned long ecc_temp;
 886         unsigned long dlycal;
 887         unsigned long dly_val;
 888         unsigned long k;
 889         unsigned long max_pass_length;
 890         unsigned long current_pass_length;
 891         unsigned long current_fail_length;
 892         unsigned long current_start;
 893         unsigned long rdclt;
 894         unsigned long rdclt_offset;
 895         long max_start;
 896         long max_end;
 897         long rdclt_average;
 898         unsigned char window_found;
 899         unsigned char fail_found;
 900         unsigned char pass_found;
 901         PPC4xx_SYS_INFO sys_info;
 902
 903         /*
 904          * get the board info
 905          */
 906         get_sys_info(&sys_info);
 907
 908         /*
 909          * get SDRAM Timing Register 0 (SDRAM_TR0) and clear bits
 910          */
 911         mfsdram(SDRAM0_TR1, tr1);
 912         tr1 &= ~(SDRAM_TR1_RDSS_MASK | SDRAM_TR1_RDSL_MASK |
 913                  SDRAM_TR1_RDCD_MASK | SDRAM_TR1_RDCT_MASK);
 914
 915         mfsdram(SDRAM0_TR0, tr0);
 916         if (((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) &&
 917             (sys_info.freqPLB > 100000000)) {
 918                 tr1 |= SDRAM_TR1_RDSS_TR2;
 919                 tr1 |= SDRAM_TR1_RDSL_STAGE3;
 920                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
 921         } else {
 922                 tr1 |= SDRAM_TR1_RDSS_TR1;
 923                 tr1 |= SDRAM_TR1_RDSL_STAGE2;
 924                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
 925         }
 926
 927         /*
 928          * save CFG0 ECC setting to a temporary variable and turn ECC off
 929          */
 930         mfsdram(SDRAM0_CFG0, cfg0);
 931         ecc_temp = cfg0 & SDRAM_CFG0_MCHK_MASK;
 932         mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_NON);
 933
 934         /*
 935          * get the delay line calibration register value
 936          */
 937         mfsdram(SDRAM0_DLYCAL, dlycal);
 938         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
 939
 940         max_pass_length = 0;
 941         max_start = 0;
 942         max_end = 0;
 943         current_pass_length = 0;
 944         current_fail_length = 0;
 945         current_start = 0;
 946         rdclt_offset = 0;
 947         window_found = false;
 948         fail_found = false;
 949         pass_found = false;
 950         debug("Starting memory test ");
 951
 952         for (k = 0; k < NUMHALFCYCLES; k++) {
 953                 for (rdclt = 0; rdclt < dly_val; rdclt++) {
 954                         /*
 955                          * Set the timing reg for the test.
 956                          */
 957                         mtsdram(SDRAM0_TR1, (tr1 | SDRAM_TR1_RDCT_ENCODE(rdclt)));
 958
 959                         if (short_mem_test()) {
 960                                 if (fail_found == true) {
 961                                         pass_found = true;
 962                                         if (current_pass_length == 0) {
 963                                                 current_start = rdclt_offset + rdclt;
 964                                         }
 965
 966                                         current_fail_length = 0;
 967                                         current_pass_length++;
 968
 969                                         if (current_pass_length > max_pass_length) {
 970                                                 max_pass_length = current_pass_length;
 971                                                 max_start = current_start;
 972                                                 max_end = rdclt_offset + rdclt;
 973                                         }
 974                                 }
 975                         } else {
 976                                 current_pass_length = 0;
 977                                 current_fail_length++;
 978
 979                                 if (current_fail_length >= (dly_val>>2)) {
 980                                         if (fail_found == false) {
 981                                                 fail_found = true;
 982                                         } else if (pass_found == true) {
 983                                                 window_found = true;
 984                                                 break;
 985                                         }
 986                                 }
 987                         }
 988                 }
 989                 debug(".");
 990
 991                 if (window_found == true)
 992                         break;
 993
 994                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
 995                 rdclt_offset += dly_val;
 996         }
 997         debug("\n");
 998
 999         /*
1000          * make sure we find the window
1001          */
1002         if (window_found == false) {
1003                 printf("ERROR: Cannot determine a common read delay.\n");
1004                 spd_ddr_init_hang ();
1005         }
1006
1007         /*
1008          * restore the orignal ECC setting
1009          */
1010         mtsdram(SDRAM0_CFG0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | ecc_temp);
1011
1012         /*
1013          * set the SDRAM TR1 RDCD value
1014          */
1015         tr1 &= ~SDRAM_TR1_RDCD_MASK;
1016         if ((tr0 & SDRAM_TR0_SDCL_MASK) == SDRAM_TR0_SDCL_2_5_CLK) {
1017                 tr1 |= SDRAM_TR1_RDCD_RCD_1_2;
1018         } else {
1019                 tr1 |= SDRAM_TR1_RDCD_RCD_0_0;
1020         }
1021
1022         /*
1023          * set the SDRAM TR1 RDCLT value
1024          */
1025         tr1 &= ~SDRAM_TR1_RDCT_MASK;
1026         while (max_end >= (dly_val << 1)) {
1027                 max_end -= (dly_val << 1);
1028                 max_start -= (dly_val << 1);
1029         }
1030
1031         rdclt_average = ((max_start + max_end) >> 1);
1032
1033         if (rdclt_average < 0) {
1034                 rdclt_average = 0;
1035         }
1036
1037         if (rdclt_average >= dly_val) {
1038                 rdclt_average -= dly_val;
1039                 tr1 = tr1 ^ SDRAM_TR1_RDCD_MASK;
1040         }
1041         tr1 |= SDRAM_TR1_RDCT_ENCODE(rdclt_average);
1042
1043         debug("tr1: %lx\n", tr1);
1044
1045         /*
1046          * program SDRAM Timing Register 1 TR1
1047          */
1048         mtsdram(SDRAM0_TR1, tr1);
1049 }
1050
1051 static unsigned long program_bxcr(unsigned long *dimm_populated,
1052                                   unsigned char *iic0_dimm_addr,
1053                                   unsigned long num_dimm_banks)
1054 {
1055         unsigned long dimm_num;
1056         unsigned long bank_base_addr;
1057         unsigned long cr;
1058         unsigned long i;
1059         unsigned long j;
1060         unsigned long temp;
1061         unsigned char num_row_addr;
1062         unsigned char num_col_addr;
1063         unsigned char num_banks;
1064         unsigned char bank_size_id;
1065         unsigned long ctrl_bank_num[MAXBANKS];
1066         unsigned long bx_cr_num;
1067         unsigned long largest_size_index;
1068         unsigned long largest_size;
1069         unsigned long current_size_index;
1070         BANKPARMS bank_parms[MAXBXCR];
1071         unsigned long sorted_bank_num[MAXBXCR]; /* DDR Controller bank number table (sorted by size) */
1072         unsigned long sorted_bank_size[MAXBXCR]; /* DDR Controller bank size table (sorted by size)*/
1073
1074         /*
1075          * Set the BxCR regs.  First, wipe out the bank config registers.
1076          */
1077         for (bx_cr_num = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1078                 mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (bx_cr_num << 2));
1079                 mtdcr(SDRAM0_CFGDATA, 0x00000000);
1080                 bank_parms[bx_cr_num].bank_size_bytes = 0;
1081         }
1082
1083 #ifdef CONFIG_BAMBOO
1084         /*
1085          * This next section is hardware dependent and must be programmed
1086          * to match the hardware.  For bamboo, the following holds...
1087          * 1. SDRAM0_B0CR: Bank 0 of dimm 0 ctrl_bank_num : 0 (soldered onboard)
1088          * 2. SDRAM0_B1CR: Bank 0 of dimm 1 ctrl_bank_num : 1
1089          * 3. SDRAM0_B2CR: Bank 1 of dimm 1 ctrl_bank_num : 1
1090          * 4. SDRAM0_B3CR: Bank 0 of dimm 2 ctrl_bank_num : 3
1091          * ctrl_bank_num corresponds to the first usable DDR controller bank number by DIMM
1092          */
1093         ctrl_bank_num[0] = 0;
1094         ctrl_bank_num[1] = 1;
1095         ctrl_bank_num[2] = 3;
1096 #else
1097         /*
1098          * Ocotea, Ebony and the other IBM/AMCC eval boards have
1099          * 2 DIMM slots with each max 2 banks
1100          */
1101         ctrl_bank_num[0] = 0;
1102         ctrl_bank_num[1] = 2;
1103 #endif
1104
1105         /*
1106          * reset the bank_base address
1107          */
1108         bank_base_addr = CONFIG_SYS_SDRAM_BASE;
1109
1110         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1111                 if (dimm_populated[dimm_num] == true) {
1112                         num_row_addr = spd_read(iic0_dimm_addr[dimm_num], 3);
1113                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
1114                         num_banks    = spd_read(iic0_dimm_addr[dimm_num], 5);
1115                         bank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
1116                         debug("DIMM%ld: row=%d col=%d banks=%d\n", dimm_num,
1117                               num_row_addr, num_col_addr, num_banks);
1118
1119                         /*
1120                          * Set the SDRAM0_BxCR regs
1121                          */
1122                         cr = 0;
1123                         switch (bank_size_id) {
1124                         case 0x02:
1125                                 cr |= SDRAM_BXCR_SDSZ_8;
1126                                 break;
1127                         case 0x04:
1128                                 cr |= SDRAM_BXCR_SDSZ_16;
1129                                 break;
1130                         case 0x08:
1131                                 cr |= SDRAM_BXCR_SDSZ_32;
1132                                 break;
1133                         case 0x10:
1134                                 cr |= SDRAM_BXCR_SDSZ_64;
1135                                 break;
1136                         case 0x20:
1137                                 cr |= SDRAM_BXCR_SDSZ_128;
1138                                 break;
1139                         case 0x40:
1140                                 cr |= SDRAM_BXCR_SDSZ_256;
1141                                 break;
1142                         case 0x80:
1143                                 cr |= SDRAM_BXCR_SDSZ_512;
1144                                 break;
1145                         default:
1146                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1147                                        dimm_num);
1148                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
1149                                        bank_size_id);
1150                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1151                                 spd_ddr_init_hang ();
1152                         }
1153
1154                         switch (num_col_addr) {
1155                         case 0x08:
1156                                 cr |= SDRAM_BXCR_SDAM_1;
1157                                 break;
1158                         case 0x09:
1159                                 cr |= SDRAM_BXCR_SDAM_2;
1160                                 break;
1161                         case 0x0A:
1162                                 cr |= SDRAM_BXCR_SDAM_3;
1163                                 break;
1164                         case 0x0B:
1165                                 cr |= SDRAM_BXCR_SDAM_4;
1166                                 break;
1167                         default:
1168                                 printf("DDR-SDRAM: DIMM %lu BxCR configuration.\n",
1169                                        dimm_num);
1170                                 printf("ERROR: Unsupported value for number of "
1171                                        "column addresses: %d.\n", num_col_addr);
1172                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1173                                 spd_ddr_init_hang ();
1174                         }
1175
1176                         /*
1177                          * enable the bank
1178                          */
1179                         cr |= SDRAM_BXCR_SDBE;
1180
1181                         for (i = 0; i < num_banks; i++) {
1182                                 bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
1183                                         (4 << 20) * bank_size_id;
1184                                 bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
1185                                 debug("DIMM%ld-bank %ld (SDRAM0_B%ldCR): "
1186                                         "bank_size_bytes=%ld\n",
1187                                         dimm_num, i,
1188                                         ctrl_bank_num[dimm_num] + i,
1189                                         bank_parms[ctrl_bank_num[dimm_num] + i].bank_size_bytes);
1190                         }
1191                 }
1192         }
1193
1194         /* Initialize sort tables */
1195         for (i = 0; i < MAXBXCR; i++) {
1196                 sorted_bank_num[i] = i;
1197                 sorted_bank_size[i] = bank_parms[i].bank_size_bytes;
1198         }
1199
1200         for (i = 0; i < MAXBXCR-1; i++) {
1201                 largest_size = sorted_bank_size[i];
1202                 largest_size_index = 255;
1203
1204                 /* Find the largest remaining value */
1205                 for (j = i + 1; j < MAXBXCR; j++) {
1206                         if (sorted_bank_size[j] > largest_size) {
1207                                 /* Save largest remaining value and its index */
1208                                 largest_size = sorted_bank_size[j];
1209                                 largest_size_index = j;
1210                         }
1211                 }
1212
1213                 if (largest_size_index != 255) {
1214                         /* Swap the current and largest values */
1215                         current_size_index = sorted_bank_num[largest_size_index];
1216                         sorted_bank_size[largest_size_index] = sorted_bank_size[i];
1217                         sorted_bank_size[i] = largest_size;
1218                         sorted_bank_num[largest_size_index] = sorted_bank_num[i];
1219                         sorted_bank_num[i] = current_size_index;
1220                 }
1221         }
1222
1223         /* Set the SDRAM0_BxCR regs thanks to sort tables */
1224         for (bx_cr_num = 0, bank_base_addr = 0; bx_cr_num < MAXBXCR; bx_cr_num++) {
1225                 if (bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes) {
1226                         mtdcr(SDRAM0_CFGADDR, SDRAM0_B0CR + (sorted_bank_num[bx_cr_num] << 2));
1227                         temp = mfdcr(SDRAM0_CFGDATA) & ~(SDRAM_BXCR_SDBA_MASK | SDRAM_BXCR_SDSZ_MASK |
1228                                                   SDRAM_BXCR_SDAM_MASK | SDRAM_BXCR_SDBE);
1229                         temp = temp | (bank_base_addr & SDRAM_BXCR_SDBA_MASK) |
1230                                 bank_parms[sorted_bank_num[bx_cr_num]].cr;
1231                         mtdcr(SDRAM0_CFGDATA, temp);
1232                         bank_base_addr += bank_parms[sorted_bank_num[bx_cr_num]].bank_size_bytes;
1233                         debug("SDRAM0_B%ldCR=0x%08lx\n",
1234                                 sorted_bank_num[bx_cr_num], temp);
1235                 }
1236         }
1237
1238         return(bank_base_addr);
1239 }
1240 #endif /* CONFIG_SPD_EEPROM */