arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x CPUs with a Denali-core
   4  * DDR2 controller, specifically the 440EPx/GRx.
   5  *
   6  * (C) Copyright 2007-2008
   7  * Larry Johnson, lrj@acm.org.
   8  *
   9  * Based primarily on arch/powerpc/cpu/ppc4xx/4xx_spd_ddr2.c, which is...
  10  *
  11  * (C) Copyright 2007
  12  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  13  *
  14  * COPYRIGHT   AMCC   CORPORATION 2004
  15  *
  16  * SPDX-License-Identifier:     GPL-2.0+
  17  */
  18
  19 /* define DEBUG for debugging output (obviously ;-)) */
  20 #if 0
  21 #define DEBUG
  22 #endif
  23
  24 #include <common.h>
  25 #include <command.h>
  26 #include <asm/ppc4xx.h>
  27 #include <i2c.h>
  28 #include <asm/io.h>
  29 #include <asm/processor.h>
  30 #include <asm/mmu.h>
  31 #include <asm/cache.h>
  32
  33 #if defined(CONFIG_SPD_EEPROM) &&                               \
  34         (defined(CONFIG_440EPX) || defined(CONFIG_440GRX))
  35
  36 /*-----------------------------------------------------------------------------+
  37  * Defines
  38  *-----------------------------------------------------------------------------*/
  39 #define MAXDIMMS        2
  40 #define MAXRANKS        2
  41
  42 #define ONE_BILLION     1000000000
  43
  44 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
  45
  46 #define DLL_DQS_DELAY   0x19
  47 #define DLL_DQS_BYPASS  0x0B
  48 #define DQS_OUT_SHIFT   0x7F
  49
  50 /*
  51  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2 memory
  52  * region. Right now the cache should still be disabled in U-Boot because of the
  53  * EMAC driver, that need it's buffer descriptor to be located in non cached
  54  * memory.
  55  *
  56  * If at some time this restriction doesn't apply anymore, just define
  57  * CONFIG_4xx_DCACHE in the board config file and this code should setup
  58  * everything correctly.
  59  */
  60 #if defined(CONFIG_4xx_DCACHE)
  61 #define MY_TLB_WORD2_I_ENABLE   0                       /* enable caching on SDRAM */
  62 #else
  63 #define MY_TLB_WORD2_I_ENABLE   TLB_WORD2_I_ENABLE      /* disable caching on SDRAM */
  64 #endif
  65
  66 /*-----------------------------------------------------------------------------+
  67  * Prototypes
  68  *-----------------------------------------------------------------------------*/
  69 extern int denali_wait_for_dlllock(void);
  70 extern void denali_core_search_data_eye(void);
  71 extern void dcbz_area(u32 start_address, u32 num_bytes);
  72
  73 /*
  74  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
  75  */
  76 void __spd_ddr_init_hang(void)
  77 {
  78         hang();
  79 }
  80 void spd_ddr_init_hang(void)
  81     __attribute__ ((weak, alias("__spd_ddr_init_hang")));
  82
  83 #if defined(DEBUG)
  84 static void print_mcsr(void)
  85 {
  86         printf("MCSR = 0x%08X\n", mfspr(SPRN_MCSR));
  87 }
  88
  89 static void denali_sdram_register_dump(void)
  90 {
  91         unsigned int sdram_data;
  92
  93         printf("\n  Register Dump:\n");
  94         mfsdram(DDR0_00, sdram_data);
  95         printf("        DDR0_00 = 0x%08X", sdram_data);
  96         mfsdram(DDR0_01, sdram_data);
  97         printf("        DDR0_01 = 0x%08X\n", sdram_data);
  98         mfsdram(DDR0_02, sdram_data);
  99         printf("        DDR0_02 = 0x%08X", sdram_data);
 100         mfsdram(DDR0_03, sdram_data);
 101         printf("        DDR0_03 = 0x%08X\n", sdram_data);
 102         mfsdram(DDR0_04, sdram_data);
 103         printf("        DDR0_04 = 0x%08X", sdram_data);
 104         mfsdram(DDR0_05, sdram_data);
 105         printf("        DDR0_05 = 0x%08X\n", sdram_data);
 106         mfsdram(DDR0_06, sdram_data);
 107         printf("        DDR0_06 = 0x%08X", sdram_data);
 108         mfsdram(DDR0_07, sdram_data);
 109         printf("        DDR0_07 = 0x%08X\n", sdram_data);
 110         mfsdram(DDR0_08, sdram_data);
 111         printf("        DDR0_08 = 0x%08X", sdram_data);
 112         mfsdram(DDR0_09, sdram_data);
 113         printf("        DDR0_09 = 0x%08X\n", sdram_data);
 114         mfsdram(DDR0_10, sdram_data);
 115         printf("        DDR0_10 = 0x%08X", sdram_data);
 116         mfsdram(DDR0_11, sdram_data);
 117         printf("        DDR0_11 = 0x%08X\n", sdram_data);
 118         mfsdram(DDR0_12, sdram_data);
 119         printf("        DDR0_12 = 0x%08X", sdram_data);
 120         mfsdram(DDR0_14, sdram_data);
 121         printf("        DDR0_14 = 0x%08X\n", sdram_data);
 122         mfsdram(DDR0_17, sdram_data);
 123         printf("        DDR0_17 = 0x%08X", sdram_data);
 124         mfsdram(DDR0_18, sdram_data);
 125         printf("        DDR0_18 = 0x%08X\n", sdram_data);
 126         mfsdram(DDR0_19, sdram_data);
 127         printf("        DDR0_19 = 0x%08X", sdram_data);
 128         mfsdram(DDR0_20, sdram_data);
 129         printf("        DDR0_20 = 0x%08X\n", sdram_data);
 130         mfsdram(DDR0_21, sdram_data);
 131         printf("        DDR0_21 = 0x%08X", sdram_data);
 132         mfsdram(DDR0_22, sdram_data);
 133         printf("        DDR0_22 = 0x%08X\n", sdram_data);
 134         mfsdram(DDR0_23, sdram_data);
 135         printf("        DDR0_23 = 0x%08X", sdram_data);
 136         mfsdram(DDR0_24, sdram_data);
 137         printf("        DDR0_24 = 0x%08X\n", sdram_data);
 138         mfsdram(DDR0_25, sdram_data);
 139         printf("        DDR0_25 = 0x%08X", sdram_data);
 140         mfsdram(DDR0_26, sdram_data);
 141         printf("        DDR0_26 = 0x%08X\n", sdram_data);
 142         mfsdram(DDR0_27, sdram_data);
 143         printf("        DDR0_27 = 0x%08X", sdram_data);
 144         mfsdram(DDR0_28, sdram_data);
 145         printf("        DDR0_28 = 0x%08X\n", sdram_data);
 146         mfsdram(DDR0_31, sdram_data);
 147         printf("        DDR0_31 = 0x%08X", sdram_data);
 148         mfsdram(DDR0_32, sdram_data);
 149         printf("        DDR0_32 = 0x%08X\n", sdram_data);
 150         mfsdram(DDR0_33, sdram_data);
 151         printf("        DDR0_33 = 0x%08X", sdram_data);
 152         mfsdram(DDR0_34, sdram_data);
 153         printf("        DDR0_34 = 0x%08X\n", sdram_data);
 154         mfsdram(DDR0_35, sdram_data);
 155         printf("        DDR0_35 = 0x%08X", sdram_data);
 156         mfsdram(DDR0_36, sdram_data);
 157         printf("        DDR0_36 = 0x%08X\n", sdram_data);
 158         mfsdram(DDR0_37, sdram_data);
 159         printf("        DDR0_37 = 0x%08X", sdram_data);
 160         mfsdram(DDR0_38, sdram_data);
 161         printf("        DDR0_38 = 0x%08X\n", sdram_data);
 162         mfsdram(DDR0_39, sdram_data);
 163         printf("        DDR0_39 = 0x%08X", sdram_data);
 164         mfsdram(DDR0_40, sdram_data);
 165         printf("        DDR0_40 = 0x%08X\n", sdram_data);
 166         mfsdram(DDR0_41, sdram_data);
 167         printf("        DDR0_41 = 0x%08X", sdram_data);
 168         mfsdram(DDR0_42, sdram_data);
 169         printf("        DDR0_42 = 0x%08X\n", sdram_data);
 170         mfsdram(DDR0_43, sdram_data);
 171         printf("        DDR0_43 = 0x%08X", sdram_data);
 172         mfsdram(DDR0_44, sdram_data);
 173         printf("        DDR0_44 = 0x%08X\n", sdram_data);
 174 }
 175 #else
 176 static inline void denali_sdram_register_dump(void)
 177 {
 178 }
 179
 180 inline static void print_mcsr(void)
 181 {
 182 }
 183 #endif /* defined(DEBUG) */
 184
 185 static int is_ecc_enabled(void)
 186 {
 187         u32 val;
 188
 189         mfsdram(DDR0_22, val);
 190         return 0x3 == DDR0_22_CTRL_RAW_DECODE(val);
 191 }
 192
 193 static unsigned char spd_read(u8 chip, unsigned int addr)
 194 {
 195         u8 data[2];
 196
 197         if (0 != i2c_probe(chip) || 0 != i2c_read(chip, addr, 1, data, 1)) {
 198                 debug("spd_read(0x%02X, 0x%02X) failed\n", chip, addr);
 199                 return 0;
 200         }
 201         debug("spd_read(0x%02X, 0x%02X) returned 0x%02X\n",
 202               chip, addr, data[0]);
 203         return data[0];
 204 }
 205
 206 static unsigned long get_tcyc(unsigned char reg)
 207 {
 208         /*
 209          * Byte 9, et al: Cycle time for CAS Latency=X, is split into two
 210          * nibbles: the higher order nibble (bits 4-7) designates the cycle time
 211          * to a granularity of 1ns; the value presented by the lower order
 212          * nibble (bits 0-3) has a granularity of .1ns and is added to the value
 213          * designated by the higher nibble. In addition, four lines of the lower
 214          * order nibble are assigned to support +.25, +.33, +.66, and +.75.
 215          */
 216
 217         unsigned char subfield_b = reg & 0x0F;
 218
 219         switch (subfield_b & 0x0F) {
 220         case 0x0:
 221         case 0x1:
 222         case 0x2:
 223         case 0x3:
 224         case 0x4:
 225         case 0x5:
 226         case 0x6:
 227         case 0x7:
 228         case 0x8:
 229         case 0x9:
 230                 return 1000 * (reg >> 4) + 100 * subfield_b;
 231         case 0xA:
 232                 return 1000 * (reg >> 4) + 250;
 233         case 0xB:
 234                 return 1000 * (reg >> 4) + 333;
 235         case 0xC:
 236                 return 1000 * (reg >> 4) + 667;
 237         case 0xD:
 238                 return 1000 * (reg >> 4) + 750;
 239         }
 240         return 0;
 241 }
 242
 243 /*------------------------------------------------------------------
 244  * Find the installed DIMMs, make sure that the are DDR2, and fill
 245  * in the dimm_ranks array.  Then dimm_ranks[dimm_num] > 0 iff the
 246  * DIMM and dimm_num is present.
 247  * Note: Because there are only two chip-select lines, it is assumed
 248  * that a board with a single socket can support two ranks on that
 249  * socket, while a board with two sockets can support only one rank
 250  * on each socket.
 251  *-----------------------------------------------------------------*/
 252 static void get_spd_info(unsigned long dimm_ranks[],
 253                          unsigned long *ranks,
 254                          unsigned char const iic0_dimm_addr[],
 255                          unsigned long num_dimm_banks)
 256 {
 257         unsigned long dimm_num;
 258         unsigned long dimm_found = false;
 259         unsigned long const max_ranks_per_dimm = (1 == num_dimm_banks) ? 2 : 1;
 260         unsigned char num_of_bytes;
 261         unsigned char total_size;
 262
 263         *ranks = 0;
 264         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 265                 num_of_bytes = 0;
 266                 total_size = 0;
 267
 268                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 269                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 270                 if ((num_of_bytes != 0) && (total_size != 0)) {
 271                         unsigned char const dimm_type =
 272                             spd_read(iic0_dimm_addr[dimm_num], 2);
 273
 274                         unsigned long ranks_on_dimm =
 275                             (spd_read(iic0_dimm_addr[dimm_num], 5) & 0x07) + 1;
 276
 277                         if (8 != dimm_type) {
 278                                 switch (dimm_type) {
 279                                 case 1:
 280                                         printf("ERROR: Standard Fast Page Mode "
 281                                                "DRAM DIMM");
 282                                         break;
 283                                 case 2:
 284                                         printf("ERROR: EDO DIMM");
 285                                         break;
 286                                 case 3:
 287                                         printf("ERROR: Pipelined Nibble DIMM");
 288                                         break;
 289                                 case 4:
 290                                         printf("ERROR: SDRAM DIMM");
 291                                         break;
 292                                 case 5:
 293                                         printf("ERROR: Multiplexed ROM DIMM");
 294                                         break;
 295                                 case 6:
 296                                         printf("ERROR: SGRAM DIMM");
 297                                         break;
 298                                 case 7:
 299                                         printf("ERROR: DDR1 DIMM");
 300                                         break;
 301                                 default:
 302                                         printf("ERROR: Unknown DIMM (type %d)",
 303                                                (unsigned int)dimm_type);
 304                                         break;
 305                                 }
 306                                 printf(" detected in slot %lu.\n", dimm_num);
 307                                 printf("Only DDR2 SDRAM DIMMs are supported."
 308                                        "\n");
 309                                 printf("Replace the module with a DDR2 DIMM."
 310                                        "\n\n");
 311                                 spd_ddr_init_hang();
 312                         }
 313                         dimm_found = true;
 314                         debug("DIMM slot %lu: populated with %lu-rank DDR2 DIMM"
 315                               "\n", dimm_num, ranks_on_dimm);
 316                         if (ranks_on_dimm > max_ranks_per_dimm) {
 317                                 printf("WARNING: DRAM DIMM in slot %lu has %lu "
 318                                        "ranks.\n", dimm_num, ranks_on_dimm);
 319                                 if (1 == max_ranks_per_dimm) {
 320                                         printf("Only one rank will be used.\n");
 321                                 } else {
 322                                         printf
 323                                             ("Only two ranks will be used.\n");
 324                                 }
 325                                 ranks_on_dimm = max_ranks_per_dimm;
 326                         }
 327                         dimm_ranks[dimm_num] = ranks_on_dimm;
 328                         *ranks += ranks_on_dimm;
 329                 } else {
 330                         dimm_ranks[dimm_num] = 0;
 331                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 332                 }
 333         }
 334         if (dimm_found == false) {
 335                 printf("ERROR: No memory installed.\n");
 336                 printf("Install at least one DDR2 DIMM.\n\n");
 337                 spd_ddr_init_hang();
 338         }
 339         debug("Total number of ranks = %ld\n", *ranks);
 340 }
 341
 342 /*------------------------------------------------------------------
 343  * For the memory DIMMs installed, this routine verifies that
 344  * frequency previously calculated is supported.
 345  *-----------------------------------------------------------------*/
 346 static void check_frequency(unsigned long *dimm_ranks,
 347                             unsigned char const iic0_dimm_addr[],
 348                             unsigned long num_dimm_banks,
 349                             unsigned long sdram_freq)
 350 {
 351         unsigned long dimm_num;
 352         unsigned long cycle_time;
 353         unsigned long calc_cycle_time;
 354
 355         /*
 356          * calc_cycle_time is calculated from DDR frequency set by board/chip
 357          * and is expressed in picoseconds to match the way DIMM cycle time is
 358          * calculated below.
 359          */
 360         calc_cycle_time = MULDIV64(ONE_BILLION, 1000, sdram_freq);
 361
 362         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 363                 if (dimm_ranks[dimm_num]) {
 364                         cycle_time =
 365                             get_tcyc(spd_read(iic0_dimm_addr[dimm_num], 9));
 366                         debug("cycle_time=%ld ps\n", cycle_time);
 367
 368                         if (cycle_time > (calc_cycle_time + 10)) {
 369                                 /*
 370                                  * the provided sdram cycle_time is too small
 371                                  * for the available DIMM cycle_time. The
 372                                  * additionnal 10ps is here to accept a small
 373                                  * incertainty.
 374                                  */
 375                                 printf
 376                                     ("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 377                                      "slot %d \n while calculated cycle time is %d ps.\n",
 378                                      (unsigned int)cycle_time,
 379                                      (unsigned int)dimm_num,
 380                                      (unsigned int)calc_cycle_time);
 381                                 printf
 382                                     ("Replace the DIMM, or change DDR frequency via "
 383                                      "strapping bits.\n\n");
 384                                 spd_ddr_init_hang();
 385                         }
 386                 }
 387         }
 388 }
 389
 390 /*------------------------------------------------------------------
 391  * This routine gets size information for the installed memory
 392  * DIMMs.
 393  *-----------------------------------------------------------------*/
 394 static void get_dimm_size(unsigned long dimm_ranks[],
 395                           unsigned char const iic0_dimm_addr[],
 396                           unsigned long num_dimm_banks,
 397                           unsigned long *const rows,
 398                           unsigned long *const banks,
 399                           unsigned long *const cols, unsigned long *const width)
 400 {
 401         unsigned long dimm_num;
 402
 403         *rows = 0;
 404         *banks = 0;
 405         *cols = 0;
 406         *width = 0;
 407         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 408                 if (dimm_ranks[dimm_num]) {
 409                         unsigned long t;
 410
 411                         /* Rows */
 412                         t = spd_read(iic0_dimm_addr[dimm_num], 3);
 413                         if (0 == *rows) {
 414                                 *rows = t;
 415                         } else if (t != *rows) {
 416                                 printf("ERROR: DRAM DIMM modules do not all "
 417                                        "have the same number of rows.\n\n");
 418                                 spd_ddr_init_hang();
 419                         }
 420                         /* Banks */
 421                         t = spd_read(iic0_dimm_addr[dimm_num], 17);
 422                         if (0 == *banks) {
 423                                 *banks = t;
 424                         } else if (t != *banks) {
 425                                 printf("ERROR: DRAM DIMM modules do not all "
 426                                        "have the same number of banks.\n\n");
 427                                 spd_ddr_init_hang();
 428                         }
 429                         /* Columns */
 430                         t = spd_read(iic0_dimm_addr[dimm_num], 4);
 431                         if (0 == *cols) {
 432                                 *cols = t;
 433                         } else if (t != *cols) {
 434                                 printf("ERROR: DRAM DIMM modules do not all "
 435                                        "have the same number of columns.\n\n");
 436                                 spd_ddr_init_hang();
 437                         }
 438                         /* Data width */
 439                         t = spd_read(iic0_dimm_addr[dimm_num], 6);
 440                         if (0 == *width) {
 441                                 *width = t;
 442                         } else if (t != *width) {
 443                                 printf("ERROR: DRAM DIMM modules do not all "
 444                                        "have the same data width.\n\n");
 445                                 spd_ddr_init_hang();
 446                         }
 447                 }
 448         }
 449         debug("Number of rows = %ld\n", *rows);
 450         debug("Number of columns = %ld\n", *cols);
 451         debug("Number of banks = %ld\n", *banks);
 452         debug("Data width = %ld\n", *width);
 453         if (*rows > 14) {
 454                 printf("ERROR: DRAM DIMM modules have %lu address rows.\n",
 455                        *rows);
 456                 printf("Only modules with 14 or fewer rows are supported.\n\n");
 457                 spd_ddr_init_hang();
 458         }
 459         if (4 != *banks && 8 != *banks) {
 460                 printf("ERROR: DRAM DIMM modules have %lu banks.\n", *banks);
 461                 printf("Only modules with 4 or 8 banks are supported.\n\n");
 462                 spd_ddr_init_hang();
 463         }
 464         if (*cols > 12) {
 465                 printf("ERROR: DRAM DIMM modules have %lu address columns.\n",
 466                        *cols);
 467                 printf("Only modules with 12 or fewer columns are "
 468                        "supported.\n\n");
 469                 spd_ddr_init_hang();
 470         }
 471         if (32 != *width && 40 != *width && 64 != *width && 72 != *width) {
 472                 printf("ERROR: DRAM DIMM modules have a width of %lu bit.\n",
 473                        *width);
 474                 printf("Only modules with widths of 32, 40, 64, and 72 bits "
 475                        "are supported.\n\n");
 476                 spd_ddr_init_hang();
 477         }
 478 }
 479
 480 /*------------------------------------------------------------------
 481  * Only 1.8V modules are supported.  This routine verifies this.
 482  *-----------------------------------------------------------------*/
 483 static void check_voltage_type(unsigned long dimm_ranks[],
 484                                unsigned char const iic0_dimm_addr[],
 485                                unsigned long num_dimm_banks)
 486 {
 487         unsigned long dimm_num;
 488         unsigned long voltage_type;
 489
 490         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 491                 if (dimm_ranks[dimm_num]) {
 492                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 493                         if (0x05 != voltage_type) {     /* 1.8V for DDR2 */
 494                                 printf("ERROR: Slot %lu provides 1.8V for DDR2 "
 495                                        "DIMMs.\n", dimm_num);
 496                                 switch (voltage_type) {
 497                                 case 0x00:
 498                                         printf("This DIMM is 5.0 Volt/TTL.\n");
 499                                         break;
 500                                 case 0x01:
 501                                         printf("This DIMM is LVTTL.\n");
 502                                         break;
 503                                 case 0x02:
 504                                         printf("This DIMM is 1.5 Volt.\n");
 505                                         break;
 506                                 case 0x03:
 507                                         printf("This DIMM is 3.3 Volt/TTL.\n");
 508                                         break;
 509                                 case 0x04:
 510                                         printf("This DIMM is 2.5 Volt.\n");
 511                                         break;
 512                                 default:
 513                                         printf("This DIMM is an unknown "
 514                                                "voltage.\n");
 515                                         break;
 516                                 }
 517                                 printf("Replace it with a 1.8V DDR2 DIMM.\n\n");
 518                                 spd_ddr_init_hang();
 519                         }
 520                 }
 521         }
 522 }
 523
 524 static void program_ddr0_03(unsigned long dimm_ranks[],
 525                             unsigned char const iic0_dimm_addr[],
 526                             unsigned long num_dimm_banks,
 527                             unsigned long sdram_freq,
 528                             unsigned long rows, unsigned long *cas_latency)
 529 {
 530         unsigned long dimm_num;
 531         unsigned long cas_index;
 532         unsigned long cycle_2_0_clk;
 533         unsigned long cycle_3_0_clk;
 534         unsigned long cycle_4_0_clk;
 535         unsigned long cycle_5_0_clk;
 536         unsigned long max_2_0_tcyc_ps = 100;
 537         unsigned long max_3_0_tcyc_ps = 100;
 538         unsigned long max_4_0_tcyc_ps = 100;
 539         unsigned long max_5_0_tcyc_ps = 100;
 540         unsigned char cas_available = 0x3C;     /* value for DDR2 */
 541         u32 ddr0_03 = DDR0_03_BSTLEN_ENCODE(0x2) | DDR0_03_INITAREF_ENCODE(0x2);
 542         unsigned int const tcyc_addr[3] = { 9, 23, 25 };
 543
 544         /*------------------------------------------------------------------
 545          * Get the board configuration info.
 546          *-----------------------------------------------------------------*/
 547         debug("sdram_freq = %ld\n", sdram_freq);
 548
 549         /*------------------------------------------------------------------
 550          * Handle the timing.  We need to find the worst case timing of all
 551          * the dimm modules installed.
 552          *-----------------------------------------------------------------*/
 553         /* loop through all the DIMM slots on the board */
 554         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 555                 /* If a dimm is installed in a particular slot ... */
 556                 if (dimm_ranks[dimm_num]) {
 557                         unsigned char const cas_bit =
 558                             spd_read(iic0_dimm_addr[dimm_num], 18);
 559                         unsigned char cas_mask;
 560
 561                         cas_available &= cas_bit;
 562                         for (cas_mask = 0x80; cas_mask; cas_mask >>= 1) {
 563                                 if (cas_bit & cas_mask)
 564                                         break;
 565                         }
 566                         debug("cas_bit (SPD byte 18) = %02X, cas_mask = %02X\n",
 567                               cas_bit, cas_mask);
 568
 569                         for (cas_index = 0; cas_index < 3;
 570                              cas_mask >>= 1, cas_index++) {
 571                                 unsigned long cycle_time_ps;
 572
 573                                 if (!(cas_available & cas_mask)) {
 574                                         continue;
 575                                 }
 576                                 cycle_time_ps =
 577                                     get_tcyc(spd_read(iic0_dimm_addr[dimm_num],
 578                                                       tcyc_addr[cas_index]));
 579
 580                                 debug("cas_index = %ld: cycle_time_ps = %ld\n",
 581                                       cas_index, cycle_time_ps);
 582                                 /*
 583                                  * DDR2 devices use the following bitmask for CAS latency:
 584                                  *  Bit   7    6    5    4    3    2    1    0
 585                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
 586                                  */
 587                                 switch (cas_mask) {
 588                                 case 0x20:
 589                                         max_5_0_tcyc_ps =
 590                                             max(max_5_0_tcyc_ps, cycle_time_ps);
 591                                         break;
 592                                 case 0x10:
 593                                         max_4_0_tcyc_ps =
 594                                             max(max_4_0_tcyc_ps, cycle_time_ps);
 595                                         break;
 596                                 case 0x08:
 597                                         max_3_0_tcyc_ps =
 598                                             max(max_3_0_tcyc_ps, cycle_time_ps);
 599                                         break;
 600                                 case 0x04:
 601                                         max_2_0_tcyc_ps =
 602                                             max(max_2_0_tcyc_ps, cycle_time_ps);
 603                                         break;
 604                                 }
 605                         }
 606                 }
 607         }
 608         debug("cas_available (bit map) = 0x%02X\n", cas_available);
 609
 610         /*------------------------------------------------------------------
 611          * Set the SDRAM mode, SDRAM_MMODE
 612          *-----------------------------------------------------------------*/
 613
 614         /* add 10 here because of rounding problems */
 615         cycle_2_0_clk = MULDIV64(ONE_BILLION, 1000, max_2_0_tcyc_ps) + 10;
 616         cycle_3_0_clk = MULDIV64(ONE_BILLION, 1000, max_3_0_tcyc_ps) + 10;
 617         cycle_4_0_clk = MULDIV64(ONE_BILLION, 1000, max_4_0_tcyc_ps) + 10;
 618         cycle_5_0_clk = MULDIV64(ONE_BILLION, 1000, max_5_0_tcyc_ps) + 10;
 619         debug("cycle_2_0_clk = %ld\n", cycle_2_0_clk);
 620         debug("cycle_3_0_clk = %ld\n", cycle_3_0_clk);
 621         debug("cycle_4_0_clk = %ld\n", cycle_4_0_clk);
 622         debug("cycle_5_0_clk = %ld\n", cycle_5_0_clk);
 623
 624         if ((cas_available & 0x04) && (sdram_freq <= cycle_2_0_clk)) {
 625                 *cas_latency = 2;
 626                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x2) |
 627                     DDR0_03_CASLAT_LIN_ENCODE(0x4);
 628         } else if ((cas_available & 0x08) && (sdram_freq <= cycle_3_0_clk)) {
 629                 *cas_latency = 3;
 630                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x3) |
 631                     DDR0_03_CASLAT_LIN_ENCODE(0x6);
 632         } else if ((cas_available & 0x10) && (sdram_freq <= cycle_4_0_clk)) {
 633                 *cas_latency = 4;
 634                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x4) |
 635                     DDR0_03_CASLAT_LIN_ENCODE(0x8);
 636         } else if ((cas_available & 0x20) && (sdram_freq <= cycle_5_0_clk)) {
 637                 *cas_latency = 5;
 638                 ddr0_03 |= DDR0_03_CASLAT_ENCODE(0x5) |
 639                     DDR0_03_CASLAT_LIN_ENCODE(0xA);
 640         } else {
 641                 printf("ERROR: Cannot find a supported CAS latency with the "
 642                        "installed DIMMs.\n");
 643                 printf("Only DDR2 DIMMs with CAS latencies of 2.0, 3.0, 4.0, "
 644                        "and 5.0 are supported.\n");
 645                 printf("Make sure the PLB speed is within the supported range "
 646                        "of the DIMMs.\n");
 647                 printf("sdram_freq=%ld cycle2=%ld cycle3=%ld cycle4=%ld "
 648                        "cycle5=%ld\n\n", sdram_freq, cycle_2_0_clk,
 649                        cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
 650                 spd_ddr_init_hang();
 651         }
 652         debug("CAS latency = %ld\n", *cas_latency);
 653         mtsdram(DDR0_03, ddr0_03);
 654 }
 655
 656 static void program_ddr0_04(unsigned long dimm_ranks[],
 657                             unsigned char const iic0_dimm_addr[],
 658                             unsigned long num_dimm_banks,
 659                             unsigned long sdram_freq)
 660 {
 661         unsigned long dimm_num;
 662         unsigned long t_rc_ps = 0;
 663         unsigned long t_rrd_ps = 0;
 664         unsigned long t_rtp_ps = 0;
 665         unsigned long t_rc_clk;
 666         unsigned long t_rrd_clk;
 667         unsigned long t_rtp_clk;
 668
 669         /*------------------------------------------------------------------
 670          * Handle the timing.  We need to find the worst case timing of all
 671          * the dimm modules installed.
 672          *-----------------------------------------------------------------*/
 673         /* loop through all the DIMM slots on the board */
 674         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 675                 /* If a dimm is installed in a particular slot ... */
 676                 if (dimm_ranks[dimm_num]) {
 677                         unsigned long ps;
 678
 679                         /* tRC */
 680                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 41);
 681                         switch (spd_read(iic0_dimm_addr[dimm_num], 40) >> 4) {
 682                         case 0x1:
 683                                 ps += 250;
 684                                 break;
 685                         case 0x2:
 686                                 ps += 333;
 687                                 break;
 688                         case 0x3:
 689                                 ps += 500;
 690                                 break;
 691                         case 0x4:
 692                                 ps += 667;
 693                                 break;
 694                         case 0x5:
 695                                 ps += 750;
 696                                 break;
 697                         }
 698                         t_rc_ps = max(t_rc_ps, ps);
 699                         /* tRRD */
 700                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 28);
 701                         t_rrd_ps = max(t_rrd_ps, ps);
 702                         /* tRTP */
 703                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 38);
 704                         t_rtp_ps = max(t_rtp_ps, ps);
 705                 }
 706         }
 707         debug("t_rc_ps  = %ld\n", t_rc_ps);
 708         t_rc_clk = (MULDIV64(sdram_freq, t_rc_ps, ONE_BILLION) + 999) / 1000;
 709         debug("t_rrd_ps = %ld\n", t_rrd_ps);
 710         t_rrd_clk = (MULDIV64(sdram_freq, t_rrd_ps, ONE_BILLION) + 999) / 1000;
 711         debug("t_rtp_ps = %ld\n", t_rtp_ps);
 712         t_rtp_clk = (MULDIV64(sdram_freq, t_rtp_ps, ONE_BILLION) + 999) / 1000;
 713         mtsdram(DDR0_04, DDR0_04_TRC_ENCODE(t_rc_clk) |
 714                 DDR0_04_TRRD_ENCODE(t_rrd_clk) |
 715                 DDR0_04_TRTP_ENCODE(t_rtp_clk));
 716 }
 717
 718 static void program_ddr0_05(unsigned long dimm_ranks[],
 719                             unsigned char const iic0_dimm_addr[],
 720                             unsigned long num_dimm_banks,
 721                             unsigned long sdram_freq)
 722 {
 723         unsigned long dimm_num;
 724         unsigned long t_rp_ps = 0;
 725         unsigned long t_ras_ps = 0;
 726         unsigned long t_rp_clk;
 727         unsigned long t_ras_clk;
 728         u32 ddr0_05 = DDR0_05_TMRD_ENCODE(0x2) | DDR0_05_TEMRS_ENCODE(0x2);
 729
 730         /*------------------------------------------------------------------
 731          * Handle the timing.  We need to find the worst case timing of all
 732          * the dimm modules installed.
 733          *-----------------------------------------------------------------*/
 734         /* loop through all the DIMM slots on the board */
 735         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 736                 /* If a dimm is installed in a particular slot ... */
 737                 if (dimm_ranks[dimm_num]) {
 738                         unsigned long ps;
 739
 740                         /* tRP */
 741                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 27);
 742                         t_rp_ps = max(t_rp_ps, ps);
 743                         /* tRAS */
 744                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 30);
 745                         t_ras_ps = max(t_ras_ps, ps);
 746                 }
 747         }
 748         debug("t_rp_ps  = %ld\n", t_rp_ps);
 749         t_rp_clk = (MULDIV64(sdram_freq, t_rp_ps, ONE_BILLION) + 999) / 1000;
 750         debug("t_ras_ps = %ld\n", t_ras_ps);
 751         t_ras_clk = (MULDIV64(sdram_freq, t_ras_ps, ONE_BILLION) + 999) / 1000;
 752         mtsdram(DDR0_05, ddr0_05 | DDR0_05_TRP_ENCODE(t_rp_clk) |
 753                 DDR0_05_TRAS_MIN_ENCODE(t_ras_clk));
 754 }
 755
 756 static void program_ddr0_06(unsigned long dimm_ranks[],
 757                             unsigned char const iic0_dimm_addr[],
 758                             unsigned long num_dimm_banks,
 759                             unsigned long sdram_freq)
 760 {
 761         unsigned long dimm_num;
 762         unsigned char spd_40;
 763         unsigned long t_wtr_ps = 0;
 764         unsigned long t_rfc_ps = 0;
 765         unsigned long t_wtr_clk;
 766         unsigned long t_rfc_clk;
 767         u32 ddr0_06 =
 768             DDR0_06_WRITEINTERP_ENCODE(0x1) | DDR0_06_TDLL_ENCODE(200);
 769
 770         /*------------------------------------------------------------------
 771          * Handle the timing.  We need to find the worst case timing of all
 772          * the dimm modules installed.
 773          *-----------------------------------------------------------------*/
 774         /* loop through all the DIMM slots on the board */
 775         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 776                 /* If a dimm is installed in a particular slot ... */
 777                 if (dimm_ranks[dimm_num]) {
 778                         unsigned long ps;
 779
 780                         /* tWTR */
 781                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 37);
 782                         t_wtr_ps = max(t_wtr_ps, ps);
 783                         /* tRFC */
 784                         ps = 1000 * spd_read(iic0_dimm_addr[dimm_num], 42);
 785                         spd_40 = spd_read(iic0_dimm_addr[dimm_num], 40);
 786                         ps += 256000 * (spd_40 & 0x01);
 787                         switch ((spd_40 & 0x0E) >> 1) {
 788                         case 0x1:
 789                                 ps += 250;
 790                                 break;
 791                         case 0x2:
 792                                 ps += 333;
 793                                 break;
 794                         case 0x3:
 795                                 ps += 500;
 796                                 break;
 797                         case 0x4:
 798                                 ps += 667;
 799                                 break;
 800                         case 0x5:
 801                                 ps += 750;
 802                                 break;
 803                         }
 804                         t_rfc_ps = max(t_rfc_ps, ps);
 805                 }
 806         }
 807         debug("t_wtr_ps = %ld\n", t_wtr_ps);
 808         t_wtr_clk = (MULDIV64(sdram_freq, t_wtr_ps, ONE_BILLION) + 999) / 1000;
 809         debug("t_rfc_ps = %ld\n", t_rfc_ps);
 810         t_rfc_clk = (MULDIV64(sdram_freq, t_rfc_ps, ONE_BILLION) + 999) / 1000;
 811         mtsdram(DDR0_06, ddr0_06 | DDR0_06_TWTR_ENCODE(t_wtr_clk) |
 812                 DDR0_06_TRFC_ENCODE(t_rfc_clk));
 813 }
 814
 815 static void program_ddr0_10(unsigned long dimm_ranks[], unsigned long ranks)
 816 {
 817         unsigned long csmap;
 818
 819         if (2 == ranks) {
 820                 /* Both chip selects in use */
 821                 csmap = 0x03;
 822         } else {
 823                 /* One chip select in use */
 824                 csmap = (1 == dimm_ranks[0]) ? 0x1 : 0x2;
 825         }
 826         mtsdram(DDR0_10, DDR0_10_WRITE_MODEREG_ENCODE(0x0) |
 827                 DDR0_10_CS_MAP_ENCODE(csmap) |
 828                 DDR0_10_OCD_ADJUST_PUP_CS_0_ENCODE(0));
 829 }
 830
 831 static void program_ddr0_11(unsigned long sdram_freq)
 832 {
 833         unsigned long const t_xsnr_ps = 200000; /* 200 ns */
 834         unsigned long t_xsnr_clk;
 835
 836         debug("t_xsnr_ps = %ld\n", t_xsnr_ps);
 837         t_xsnr_clk =
 838             (MULDIV64(sdram_freq, t_xsnr_ps, ONE_BILLION) + 999) / 1000;
 839         mtsdram(DDR0_11, DDR0_11_SREFRESH_ENCODE(0) |
 840                 DDR0_11_TXSNR_ENCODE(t_xsnr_clk) | DDR0_11_TXSR_ENCODE(200));
 841 }
 842
 843 static void program_ddr0_22(unsigned long dimm_ranks[],
 844                             unsigned char const iic0_dimm_addr[],
 845                             unsigned long num_dimm_banks, unsigned long width)
 846 {
 847 #if defined(CONFIG_DDR_ECC)
 848         unsigned long dimm_num;
 849         unsigned long ecc_available = width >= 64;
 850         u32 ddr0_22 = DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
 851             DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
 852             DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS);
 853
 854         /* loop through all the DIMM slots on the board */
 855         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 856                 /* If a dimm is installed in a particular slot ... */
 857                 if (dimm_ranks[dimm_num]) {
 858                         /* Check for ECC */
 859                         if (0 == (spd_read(iic0_dimm_addr[dimm_num], 11) &
 860                                   0x02)) {
 861                                 ecc_available = false;
 862                         }
 863                 }
 864         }
 865         if (ecc_available) {
 866                 debug("ECC found on all DIMMs present\n");
 867                 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x3));
 868         } else {
 869                 debug("ECC not found on some or all DIMMs present\n");
 870                 mtsdram(DDR0_22, ddr0_22 | DDR0_22_CTRL_RAW_ENCODE(0x0));
 871         }
 872 #else
 873         mtsdram(DDR0_22, DDR0_22_CTRL_RAW_ENCODE(0x0) |
 874                 DDR0_22_DQS_OUT_SHIFT_BYPASS_ENCODE(0x26) |
 875                 DDR0_22_DQS_OUT_SHIFT_ENCODE(DQS_OUT_SHIFT) |
 876                 DDR0_22_DLL_DQS_BYPASS_8_ENCODE(DLL_DQS_BYPASS));
 877 #endif /* defined(CONFIG_DDR_ECC) */
 878 }
 879
 880 static void program_ddr0_24(unsigned long ranks)
 881 {
 882         u32 ddr0_24 = DDR0_24_RTT_PAD_TERMINATION_ENCODE(0x1) | /* 75 ohm */
 883             DDR0_24_ODT_RD_MAP_CS1_ENCODE(0x0);
 884
 885         if (2 == ranks) {
 886                 /* Both chip selects in use */
 887                 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x1) |
 888                     DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x2);
 889         } else {
 890                 /* One chip select in use */
 891                 /* One of the two fields added to ddr0_24 is a "don't care" */
 892                 ddr0_24 |= DDR0_24_ODT_WR_MAP_CS1_ENCODE(0x2) |
 893                     DDR0_24_ODT_WR_MAP_CS0_ENCODE(0x1);
 894         }
 895         mtsdram(DDR0_24, ddr0_24);
 896 }
 897
 898 static void program_ddr0_26(unsigned long sdram_freq)
 899 {
 900         unsigned long const t_ref_ps = 7800000; /* 7.8 us. refresh */
 901         /* TODO: check definition of tRAS_MAX */
 902         unsigned long const t_ras_max_ps = 9 * t_ref_ps;
 903         unsigned long t_ras_max_clk;
 904         unsigned long t_ref_clk;
 905
 906         /* Round down t_ras_max_clk and t_ref_clk */
 907         debug("t_ras_max_ps = %ld\n", t_ras_max_ps);
 908         t_ras_max_clk = MULDIV64(sdram_freq, t_ras_max_ps, ONE_BILLION) / 1000;
 909         debug("t_ref_ps     = %ld\n", t_ref_ps);
 910         t_ref_clk = MULDIV64(sdram_freq, t_ref_ps, ONE_BILLION) / 1000;
 911         mtsdram(DDR0_26, DDR0_26_TRAS_MAX_ENCODE(t_ras_max_clk) |
 912                 DDR0_26_TREF_ENCODE(t_ref_clk));
 913 }
 914
 915 static void program_ddr0_27(unsigned long sdram_freq)
 916 {
 917         unsigned long const t_init_ps = 200000000;      /* 200 us. init */
 918         unsigned long t_init_clk;
 919
 920         debug("t_init_ps = %ld\n", t_init_ps);
 921         t_init_clk =
 922             (MULDIV64(sdram_freq, t_init_ps, ONE_BILLION) + 999) / 1000;
 923         mtsdram(DDR0_27, DDR0_27_EMRS_DATA_ENCODE(0x0000) |
 924                 DDR0_27_TINIT_ENCODE(t_init_clk));
 925 }
 926
 927 static void program_ddr0_43(unsigned long dimm_ranks[],
 928                             unsigned char const iic0_dimm_addr[],
 929                             unsigned long num_dimm_banks,
 930                             unsigned long sdram_freq,
 931                             unsigned long cols, unsigned long banks)
 932 {
 933         unsigned long dimm_num;
 934         unsigned long t_wr_ps = 0;
 935         unsigned long t_wr_clk;
 936         u32 ddr0_43 = DDR0_43_APREBIT_ENCODE(10) |
 937             DDR0_43_COLUMN_SIZE_ENCODE(12 - cols) |
 938             DDR0_43_EIGHT_BANK_MODE_ENCODE(8 == banks ? 1 : 0);
 939
 940         /*------------------------------------------------------------------
 941          * Handle the timing.  We need to find the worst case timing of all
 942          * the dimm modules installed.
 943          *-----------------------------------------------------------------*/
 944         /* loop through all the DIMM slots on the board */
 945         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 946                 /* If a dimm is installed in a particular slot ... */
 947                 if (dimm_ranks[dimm_num]) {
 948                         unsigned long ps;
 949
 950                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 36);
 951                         t_wr_ps = max(t_wr_ps, ps);
 952                 }
 953         }
 954         debug("t_wr_ps = %ld\n", t_wr_ps);
 955         t_wr_clk = (MULDIV64(sdram_freq, t_wr_ps, ONE_BILLION) + 999) / 1000;
 956         mtsdram(DDR0_43, ddr0_43 | DDR0_43_TWR_ENCODE(t_wr_clk));
 957 }
 958
 959 static void program_ddr0_44(unsigned long dimm_ranks[],
 960                             unsigned char const iic0_dimm_addr[],
 961                             unsigned long num_dimm_banks,
 962                             unsigned long sdram_freq)
 963 {
 964         unsigned long dimm_num;
 965         unsigned long t_rcd_ps = 0;
 966         unsigned long t_rcd_clk;
 967
 968         /*------------------------------------------------------------------
 969          * Handle the timing.  We need to find the worst case timing of all
 970          * the dimm modules installed.
 971          *-----------------------------------------------------------------*/
 972         /* loop through all the DIMM slots on the board */
 973         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 974                 /* If a dimm is installed in a particular slot ... */
 975                 if (dimm_ranks[dimm_num]) {
 976                         unsigned long ps;
 977
 978                         ps = 250 * spd_read(iic0_dimm_addr[dimm_num], 29);
 979                         t_rcd_ps = max(t_rcd_ps, ps);
 980                 }
 981         }
 982         debug("t_rcd_ps = %ld\n", t_rcd_ps);
 983         t_rcd_clk = (MULDIV64(sdram_freq, t_rcd_ps, ONE_BILLION) + 999) / 1000;
 984         mtsdram(DDR0_44, DDR0_44_TRCD_ENCODE(t_rcd_clk));
 985 }
 986
 987 /*-----------------------------------------------------------------------------+
 988  * initdram.  Initializes the 440EPx/GPx DDR SDRAM controller.
 989  * Note: This routine runs from flash with a stack set up in the chip's
 990  * sram space.  It is important that the routine does not require .sbss, .bss or
 991  * .data sections.  It also cannot call routines that require these sections.
 992  *-----------------------------------------------------------------------------*/
 993 /*-----------------------------------------------------------------------------
 994  * Function:     initdram
 995  * Description:  Configures SDRAM memory banks for DDR operation.
 996  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 997  *               via the IIC bus and then configures the DDR SDRAM memory
 998  *               banks appropriately. If Auto Memory Configuration is
 999  *               not used, it is assumed that no DIMM is plugged
1000  *-----------------------------------------------------------------------------*/
1001 phys_size_t initdram(int board_type)
1002 {
1003         unsigned char const iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
1004         unsigned long dimm_ranks[MAXDIMMS];
1005         unsigned long ranks;
1006         unsigned long rows;
1007         unsigned long banks;
1008         unsigned long cols;
1009         unsigned long width;
1010         unsigned long const sdram_freq = get_bus_freq(0);
1011         unsigned long const num_dimm_banks = sizeof(iic0_dimm_addr);    /* on board dimm banks */
1012         unsigned long cas_latency = 0;  /* to quiet initialization warning */
1013         unsigned long dram_size;
1014
1015         debug("\nEntering initdram()\n");
1016
1017         /*------------------------------------------------------------------
1018          * Stop the DDR-SDRAM controller.
1019          *-----------------------------------------------------------------*/
1020         mtsdram(DDR0_02, DDR0_02_START_ENCODE(0));
1021
1022         /*
1023          * Make sure I2C controller is initialized
1024          * before continuing.
1025          */
1026         /* switch to correct I2C bus */
1027         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
1028         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
1029
1030         /*------------------------------------------------------------------
1031          * Clear out the serial presence detect buffers.
1032          * Perform IIC reads from the dimm.  Fill in the spds.
1033          * Check to see if the dimm slots are populated
1034          *-----------------------------------------------------------------*/
1035         get_spd_info(dimm_ranks, &ranks, iic0_dimm_addr, num_dimm_banks);
1036
1037         /*------------------------------------------------------------------
1038          * Check the frequency supported for the dimms plugged.
1039          *-----------------------------------------------------------------*/
1040         check_frequency(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1041
1042         /*------------------------------------------------------------------
1043          * Check and get size information.
1044          *-----------------------------------------------------------------*/
1045         get_dimm_size(dimm_ranks, iic0_dimm_addr, num_dimm_banks, &rows, &banks,
1046                       &cols, &width);
1047
1048         /*------------------------------------------------------------------
1049          * Check the voltage type for the dimms plugged.
1050          *-----------------------------------------------------------------*/
1051         check_voltage_type(dimm_ranks, iic0_dimm_addr, num_dimm_banks);
1052
1053         /*------------------------------------------------------------------
1054          * Program registers for SDRAM controller.
1055          *-----------------------------------------------------------------*/
1056         mtsdram(DDR0_00, DDR0_00_DLL_INCREMENT_ENCODE(0x19) |
1057                 DDR0_00_DLL_START_POINT_DECODE(0x0A));
1058
1059         mtsdram(DDR0_01, DDR0_01_PLB0_DB_CS_LOWER_ENCODE(0x01) |
1060                 DDR0_01_PLB0_DB_CS_UPPER_ENCODE(0x00) |
1061                 DDR0_01_INT_MASK_ENCODE(0xFF));
1062
1063         program_ddr0_03(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1064                         rows, &cas_latency);
1065
1066         program_ddr0_04(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1067
1068         program_ddr0_05(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1069
1070         program_ddr0_06(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1071
1072         /*
1073          * TODO: tFAW not found in SPD.  Value of 13 taken from Sequoia
1074          * board SDRAM, but may be overly conservative.
1075          */
1076         mtsdram(DDR0_07, DDR0_07_NO_CMD_INIT_ENCODE(0) |
1077                 DDR0_07_TFAW_ENCODE(13) |
1078                 DDR0_07_AUTO_REFRESH_MODE_ENCODE(1) |
1079                 DDR0_07_AREFRESH_ENCODE(0));
1080
1081         mtsdram(DDR0_08, DDR0_08_WRLAT_ENCODE(cas_latency - 1) |
1082                 DDR0_08_TCPD_ENCODE(200) | DDR0_08_DQS_N_EN_ENCODE(0) |
1083                 DDR0_08_DDRII_ENCODE(1));
1084
1085         mtsdram(DDR0_09, DDR0_09_OCD_ADJUST_PDN_CS_0_ENCODE(0x00) |
1086                 DDR0_09_RTT_0_ENCODE(0x1) |
1087                 DDR0_09_WR_DQS_SHIFT_BYPASS_ENCODE(0x1D) |
1088                 DDR0_09_WR_DQS_SHIFT_ENCODE(DQS_OUT_SHIFT - 0x20));
1089
1090         program_ddr0_10(dimm_ranks, ranks);
1091
1092         program_ddr0_11(sdram_freq);
1093
1094         mtsdram(DDR0_12, DDR0_12_TCKE_ENCODE(3));
1095
1096         mtsdram(DDR0_14, DDR0_14_DLL_BYPASS_MODE_ENCODE(0) |
1097                 DDR0_14_REDUC_ENCODE(width <= 40 ? 1 : 0) |
1098                 DDR0_14_REG_DIMM_ENABLE_ENCODE(0));
1099
1100         mtsdram(DDR0_17, DDR0_17_DLL_DQS_DELAY_0_ENCODE(DLL_DQS_DELAY));
1101
1102         mtsdram(DDR0_18, DDR0_18_DLL_DQS_DELAY_4_ENCODE(DLL_DQS_DELAY) |
1103                 DDR0_18_DLL_DQS_DELAY_3_ENCODE(DLL_DQS_DELAY) |
1104                 DDR0_18_DLL_DQS_DELAY_2_ENCODE(DLL_DQS_DELAY) |
1105                 DDR0_18_DLL_DQS_DELAY_1_ENCODE(DLL_DQS_DELAY));
1106
1107         mtsdram(DDR0_19, DDR0_19_DLL_DQS_DELAY_8_ENCODE(DLL_DQS_DELAY) |
1108                 DDR0_19_DLL_DQS_DELAY_7_ENCODE(DLL_DQS_DELAY) |
1109                 DDR0_19_DLL_DQS_DELAY_6_ENCODE(DLL_DQS_DELAY) |
1110                 DDR0_19_DLL_DQS_DELAY_5_ENCODE(DLL_DQS_DELAY));
1111
1112         mtsdram(DDR0_20, DDR0_20_DLL_DQS_BYPASS_3_ENCODE(DLL_DQS_BYPASS) |
1113                 DDR0_20_DLL_DQS_BYPASS_2_ENCODE(DLL_DQS_BYPASS) |
1114                 DDR0_20_DLL_DQS_BYPASS_1_ENCODE(DLL_DQS_BYPASS) |
1115                 DDR0_20_DLL_DQS_BYPASS_0_ENCODE(DLL_DQS_BYPASS));
1116
1117         mtsdram(DDR0_21, DDR0_21_DLL_DQS_BYPASS_7_ENCODE(DLL_DQS_BYPASS) |
1118                 DDR0_21_DLL_DQS_BYPASS_6_ENCODE(DLL_DQS_BYPASS) |
1119                 DDR0_21_DLL_DQS_BYPASS_5_ENCODE(DLL_DQS_BYPASS) |
1120                 DDR0_21_DLL_DQS_BYPASS_4_ENCODE(DLL_DQS_BYPASS));
1121
1122         program_ddr0_22(dimm_ranks, iic0_dimm_addr, num_dimm_banks, width);
1123
1124         mtsdram(DDR0_23, DDR0_23_ODT_RD_MAP_CS0_ENCODE(0x0) |
1125                 DDR0_23_FWC_ENCODE(0));
1126
1127         program_ddr0_24(ranks);
1128
1129         program_ddr0_26(sdram_freq);
1130
1131         program_ddr0_27(sdram_freq);
1132
1133         mtsdram(DDR0_28, DDR0_28_EMRS3_DATA_ENCODE(0x0000) |
1134                 DDR0_28_EMRS2_DATA_ENCODE(0x0000));
1135
1136         mtsdram(DDR0_31, DDR0_31_XOR_CHECK_BITS_ENCODE(0x0000));
1137
1138         mtsdram(DDR0_42, DDR0_42_ADDR_PINS_ENCODE(14 - rows) |
1139                 DDR0_42_CASLAT_LIN_GATE_ENCODE(2 * cas_latency));
1140
1141         program_ddr0_43(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq,
1142                         cols, banks);
1143
1144         program_ddr0_44(dimm_ranks, iic0_dimm_addr, num_dimm_banks, sdram_freq);
1145
1146         denali_sdram_register_dump();
1147
1148         dram_size = (width >= 64) ? 8 : 4;
1149         dram_size *= 1 << cols;
1150         dram_size *= banks;
1151         dram_size *= 1 << rows;
1152         dram_size *= ranks;
1153         debug("dram_size = %lu\n", dram_size);
1154
1155         /* Start the SDRAM controler */
1156         mtsdram(DDR0_02, DDR0_02_START_ENCODE(1));
1157         denali_wait_for_dlllock();
1158
1159 #if defined(CONFIG_DDR_DATA_EYE)
1160         /*
1161          * Map the first 1 MiB of memory in the TLB, and perform the data eye
1162          * search.
1163          */
1164         program_tlb(0, CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE, TLB_WORD2_I_ENABLE);
1165         denali_core_search_data_eye();
1166         denali_sdram_register_dump();
1167         remove_tlb(CONFIG_SYS_SDRAM_BASE, TLB_1MB_SIZE);
1168 #endif
1169
1170 #if defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC)
1171         program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, 0);
1172         sync();
1173         /* Zero the memory */
1174         debug("Zeroing SDRAM...");
1175 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
1176         dcbz_area(CONFIG_SYS_SDRAM_BASE, dram_size - CONFIG_SYS_MEM_TOP_HIDE);
1177 #else
1178 #error Please define CONFIG_SYS_MEM_TOP_HIDE (see README) in your board config file
1179 #endif
1180         /* Write modified dcache lines back to memory */
1181         clean_dcache_range(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_BASE + dram_size - CONFIG_SYS_MEM_TOP_HIDE);
1182         debug("Completed\n");
1183         sync();
1184         remove_tlb(CONFIG_SYS_SDRAM_BASE, dram_size);
1185
1186 #if defined(CONFIG_DDR_ECC)
1187         /*
1188          * If ECC is enabled, clear and enable interrupts
1189          */
1190         if (is_ecc_enabled()) {
1191                 u32 val;
1192
1193                 sync();
1194                 /* Clear error status */
1195                 mfsdram(DDR0_00, val);
1196                 mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
1197                 /* Set 'int_mask' parameter to functionnal value */
1198                 mfsdram(DDR0_01, val);
1199                 mtsdram(DDR0_01, (val & ~DDR0_01_INT_MASK_MASK) |
1200                         DDR0_01_INT_MASK_ALL_OFF);
1201 #if defined(CONFIG_DDR_DATA_EYE)
1202                 /*
1203                  * Running denali_core_search_data_eye() when ECC is enabled
1204                  * causes non-ECC machine checks.  This clears them.
1205                  */
1206                 print_mcsr();
1207                 mtspr(SPRN_MCSR, mfspr(SPRN_MCSR));
1208                 print_mcsr();
1209 #endif
1210                 sync();
1211         }
1212 #endif /* defined(CONFIG_DDR_ECC) */
1213 #endif /* defined(CONFIG_ZERO_SDRAM) || defined(CONFIG_DDR_ECC) */
1214
1215         program_tlb(0, CONFIG_SYS_SDRAM_BASE, dram_size, MY_TLB_WORD2_I_ENABLE);
1216         return dram_size;
1217 }
1218
1219 void board_add_ram_info(int use_default)
1220 {
1221         u32 val;
1222
1223         printf(" (ECC");
1224         if (!is_ecc_enabled()) {
1225                 printf(" not");
1226         }
1227         printf(" enabled, %ld MHz", (2 * get_bus_freq(0)) / 1000000);
1228
1229         mfsdram(DDR0_03, val);
1230         printf(", CL%d)", DDR0_03_CASLAT_LIN_DECODE(val) >> 1);
1231 }
1232 #endif /* CONFIG_SPD_EEPROM */