2 * (C) Copyright 2008, 2011 Renesas Solutions Corp.
4 * SH7724 Internal I/O register
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifndef _ASM_CPU_SH7724_H_
23 #define _ASM_CPU_SH7724_H_
25 #define CACHE_OC_NUM_WAYS 4
26 #define CCR_CACHE_INIT 0x0000090d
29 #define TRA 0xFF000020
30 #define EXPEVT 0xFF000024
31 #define INTEVT 0xFF000028
34 #define PTEH 0xFF000000
35 #define PTEL 0xFF000004
36 #define TTB 0xFF000008
37 #define TEA 0xFF00000C
38 #define MMUCR 0xFF000010
39 #define PASCR 0xFF000070
40 #define IRMCR 0xFF000078
43 #define CCR 0xFF00001C
44 #define RAMCR 0xFF000074
49 #define MMSELR 0xFF800020
50 #define CMNCR 0xFEC10000
51 #define CS0BCR 0xFEC10004
52 #define CS2BCR 0xFEC10008
53 #define CS4BCR 0xFEC10010
54 #define CS5ABCR 0xFEC10014
55 #define CS5BBCR 0xFEC10018
56 #define CS6ABCR 0xFEC1001C
57 #define CS6BBCR 0xFEC10020
58 #define CS0WCR 0xFEC10024
59 #define CS2WCR 0xFEC10028
60 #define CS4WCR 0xFEC10030
61 #define CS5AWCR 0xFEC10034
62 #define CS5BWCR 0xFEC10038
63 #define CS6AWCR 0xFEC1003C
64 #define CS6BWCR 0xFEC10040
65 #define RBWTCNT 0xFEC10054
68 #define SBSC_SDCR 0xFE400008
69 #define SBSC_SDWCR 0xFE40000C
70 #define SBSC_SDPCR 0xFE400010
71 #define SBSC_RTCSR 0xFE400014
72 #define SBSC_RTCNT 0xFE400018
73 #define SBSC_RTCOR 0xFE40001C
74 #define SBSC_RFCR 0xFE400020
77 #define DBKIND 0xFD000008
78 #define DBSTATE 0xFD00000C
79 #define DBEN 0xFD000010
80 #define DBCMDCNT 0xFD000014
81 #define DBCKECNT 0xFD000018
82 #define DBCONF 0xFD000020
83 #define DBTR0 0xFD000030
84 #define DBTR1 0xFD000034
85 #define DBTR2 0xFD000038
86 #define DBTR3 0xFD00003C
87 #define DBRFPDN0 0xFD000040
88 #define DBRFPDN1 0xFD000044
89 #define DBRFPDN2 0xFD000048
90 #define DBRFSTS 0xFD00004C
91 #define DBMRCNT 0xFD000060
92 #define DBPDCNT0 0xFD000108
97 #define FRQCRA 0xA4150000
98 #define FRQCRB 0xA4150004
100 #define VCLKCR 0xA4150004
101 #define SCLKACR 0xA4150008
102 #define SCLKBCR 0xA415000C
103 #define IRDACLKCR 0xA4150018
104 #define PLLCR 0xA4150024
105 #define DLLFRQ 0xA4150050
108 #define STBCR 0xA4150020
109 #define MSTPCR0 0xA4150030
110 #define MSTPCR1 0xA4150034
111 #define MSTPCR2 0xA4150038
114 #define RWTCNT 0xA4520000
115 #define RWTCSR 0xA4520004
119 #define TSTR 0xFFD80004
120 #define TCOR0 0xFFD80008
121 #define TCNT0 0xFFD8000C
122 #define TCR0 0xFFD80010
123 #define TCOR1 0xFFD80014
124 #define TCNT1 0xFFD80018
125 #define TCR1 0xFFD8001C
126 #define TCOR2 0xFFD80020
127 #define TCNT2 0xFFD80024
128 #define TCR2 0xFFD80028
133 #define CMSTR 0xA44A0000
134 #define CMCSR 0xA44A0060
135 #define CMCNT 0xA44A0064
136 #define CMCOR 0xA44A0068
141 #define SCIF0_BASE 0xFFE00000
142 #define SCIF1_BASE 0xFFE10000
143 #define SCIF2_BASE 0xFFE20000
144 #define SCIF3_BASE 0xa4e30000
145 #define SCIF4_BASE 0xa4e40000
146 #define SCIF5_BASE 0xa4e50000
166 #define PACR 0xA4050100
167 #define PBCR 0xA4050102
168 #define PCCR 0xA4050104
169 #define PDCR 0xA4050106
170 #define PECR 0xA4050108
171 #define PFCR 0xA405010A
172 #define PGCR 0xA405010C
173 #define PHCR 0xA405010E
174 #define PJCR 0xA4050110
175 #define PKCR 0xA4050112
176 #define PLCR 0xA4050114
177 #define PMCR 0xA4050116
178 #define PNCR 0xA4050118
179 #define PQCR 0xA405011A
180 #define PRCR 0xA405011C
181 #define PSCR 0xA405011E
182 #define PTCR 0xA4050140
183 #define PUCR 0xA4050142
184 #define PVCR 0xA4050144
185 #define PWCR 0xA4050146
186 #define PXCR 0xA4050148
187 #define PYCR 0xA405014A
188 #define PZCR 0xA405014C
189 #define PSELA 0xA405014E
190 #define PSELB 0xA4050150
191 #define PSELC 0xA4050152
192 #define PSELD 0xA4050154
193 #define PSELE 0xA4050156
194 #define HIZCRA 0xA4050158
195 #define HIZCRB 0xA405015A
196 #define HIZCRC 0xA405015C
197 #define HIZCRD 0xA405015E
198 #define MSELCRA 0xA4050180
199 #define MSELCRB 0xA4050182
200 #define PULCR 0xA4050184
201 #define DRVCRA 0xA405018A
202 #define DRVCRB 0xA405018C
205 #define PADR 0xA4050120
206 #define PBDR 0xA4050122
207 #define PCDR 0xA4050124
208 #define PDDR 0xA4050126
209 #define PEDR 0xA4050128
210 #define PFDR 0xA405012A
211 #define PGDR 0xA405012C
212 #define PHDR 0xA405012E
213 #define PJDR 0xA4050130
214 #define PKDR 0xA4050132
215 #define PLDR 0xA4050134
216 #define PMDR 0xA4050136
217 #define PNDR 0xA4050138
218 #define PQDR 0xA405013A
219 #define PRDR 0xA405013C
220 #define PSDR 0xA405013E
221 #define PTDR 0xA4050160
222 #define PUDR 0xA4050162
223 #define PVDR 0xA4050164
224 #define PWDR 0xA4050166
225 #define PYDR 0xA4050168
226 #define PZDR 0xA405016A
229 #define EDMR 0xA4600000
234 #endif /* _ASM_CPU_SH7724_H_ */