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1 /*
2  * Copyright (c) 2011 The Chromium OS Authors.
3  * (C) Copyright 2008,2009
4  * Graeme Russ, <graeme.russ@gmail.com>
5  *
6  * (C) Copyright 2002
7  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
8  *
9  * SPDX-License-Identifier:     GPL-2.0+
10  */
11
12 #include <common.h>
13 #include <pci.h>
14 #include <asm/pci.h>
15
16 static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
17                               struct pci_config_table *table)
18 {
19         u8 secondary;
20
21         hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
22         if (secondary != 0)
23                 pci_hose_scan_bus(hose, secondary);
24 }
25
26 static struct pci_config_table pci_ivybridge_config_table[] = {
27         /* vendor, device, class, bus, dev, func */
28         { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
29                 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
30         {}
31 };
32
33 void board_pci_setup_hose(struct pci_controller *hose)
34 {
35         hose->config_table = pci_ivybridge_config_table;
36         hose->first_busno = 0;
37         hose->last_busno = 0;
38
39         /* PCI memory space */
40         pci_set_region(hose->regions + 0,
41                        CONFIG_PCI_MEM_BUS,
42                        CONFIG_PCI_MEM_PHYS,
43                        CONFIG_PCI_MEM_SIZE,
44                        PCI_REGION_MEM);
45
46         /* PCI IO space */
47         pci_set_region(hose->regions + 1,
48                        CONFIG_PCI_IO_BUS,
49                        CONFIG_PCI_IO_PHYS,
50                        CONFIG_PCI_IO_SIZE,
51                        PCI_REGION_IO);
52
53         pci_set_region(hose->regions + 2,
54                        CONFIG_PCI_PREF_BUS,
55                        CONFIG_PCI_PREF_PHYS,
56                        CONFIG_PCI_PREF_SIZE,
57                        PCI_REGION_PREFETCH);
58
59         hose->region_count = 3;
60 }