arch/x86/dts/crownbay.dts

   1 /*
   2  * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /dts-v1/;
   8
   9 #include <dt-bindings/interrupt-router/intel-irq.h>
  10
  11 /include/ "skeleton.dtsi"
  12 /include/ "serial.dtsi"
  13 /include/ "rtc.dtsi"
  14
  15 / {
  16         model = "Intel Crown Bay";
  17         compatible = "intel,crownbay", "intel,queensbay";
  18
  19         aliases {
  20                 spi0 = "/spi";
  21         };
  22
  23         config {
  24                 silent_console = <0>;
  25         };
  26
  27         cpus {
  28                 #address-cells = <1>;
  29                 #size-cells = <0>;
  30
  31                 cpu@0 {
  32                         device_type = "cpu";
  33                         compatible = "cpu-x86";
  34                         reg = <0>;
  35                         intel,apic-id = <0>;
  36                 };
  37
  38                 cpu@1 {
  39                         device_type = "cpu";
  40                         compatible = "cpu-x86";
  41                         reg = <1>;
  42                         intel,apic-id = <1>;
  43                 };
  44
  45         };
  46
  47         gpioa {
  48                 compatible = "intel,ich6-gpio";
  49                 u-boot,dm-pre-reloc;
  50                 reg = <0 0x20>;
  51                 bank-name = "A";
  52         };
  53
  54         gpiob {
  55                 compatible = "intel,ich6-gpio";
  56                 u-boot,dm-pre-reloc;
  57                 reg = <0x20 0x20>;
  58                 bank-name = "B";
  59         };
  60
  61         chosen {
  62                 /*
  63                  * By default the legacy superio serial port is used as the
  64                  * U-Boot serial console. If we want to use UART from Topcliff
  65                  * PCH as the console, change this property to &pciuart#.
  66                  *
  67                  * For example, stdout-path = &pciuart0 will use the first
  68                  * UART on Topcliff PCH.
  69                  */
  70                 stdout-path = "/serial";
  71         };
  72
  73         spi {
  74                 #address-cells = <1>;
  75                 #size-cells = <0>;
  76                 compatible = "intel,ich-spi";
  77                 spi-flash@0 {
  78                         reg = <0>;
  79                         compatible = "sst,25vf016b", "spi-flash";
  80                         memory-map = <0xffe00000 0x00200000>;
  81                 };
  82         };
  83
  84         microcode {
  85                 update@0 {
  86 #include "microcode/m0220661105_cv.dtsi"
  87                 };
  88         };
  89
  90         pci {
  91                 #address-cells = <3>;
  92                 #size-cells = <2>;
  93                 compatible = "pci-x86";
  94                 u-boot,dm-pre-reloc;
  95                 ranges = <0x02000000 0x0 0x40000000 0x40000000 0 0x80000000
  96                           0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000
  97                           0x01000000 0x0 0x2000 0x2000 0 0xe000>;
  98
  99                 pcie@17,0 {
 100                         #address-cells = <3>;
 101                         #size-cells = <2>;
 102                         compatible = "pci-bridge";
 103                         u-boot,dm-pre-reloc;
 104                         reg = <0x0000b800 0x0 0x0 0x0 0x0>;
 105
 106                         topcliff@0,0 {
 107                                 #address-cells = <3>;
 108                                 #size-cells = <2>;
 109                                 compatible = "pci-bridge";
 110                                 u-boot,dm-pre-reloc;
 111                                 reg = <0x00010000 0x0 0x0 0x0 0x0>;
 112
 113                                 pciuart0: uart@a,1 {
 114                                         compatible = "pci8086,8811.00",
 115                                                         "pci8086,8811",
 116                                                         "pciclass,070002",
 117                                                         "pciclass,0700",
 118                                                         "x86-uart";
 119                                         u-boot,dm-pre-reloc;
 120                                         reg = <0x00025100 0x0 0x0 0x0 0x0
 121                                                0x01025110 0x0 0x0 0x0 0x0>;
 122                                         reg-shift = <0>;
 123                                         clock-frequency = <1843200>;
 124                                         current-speed = <115200>;
 125                                 };
 126
 127                                 pciuart1: uart@a,2 {
 128                                         compatible = "pci8086,8812.00",
 129                                                         "pci8086,8812",
 130                                                         "pciclass,070002",
 131                                                         "pciclass,0700",
 132                                                         "x86-uart";
 133                                         u-boot,dm-pre-reloc;
 134                                         reg = <0x00025200 0x0 0x0 0x0 0x0
 135                                                0x01025210 0x0 0x0 0x0 0x0>;
 136                                         reg-shift = <0>;
 137                                         clock-frequency = <1843200>;
 138                                         current-speed = <115200>;
 139                                 };
 140
 141                                 pciuart2: uart@a,3 {
 142                                         compatible = "pci8086,8813.00",
 143                                                         "pci8086,8813",
 144                                                         "pciclass,070002",
 145                                                         "pciclass,0700",
 146                                                         "x86-uart";
 147                                         u-boot,dm-pre-reloc;
 148                                         reg = <0x00025300 0x0 0x0 0x0 0x0
 149                                                0x01025310 0x0 0x0 0x0 0x0>;
 150                                         reg-shift = <0>;
 151                                         clock-frequency = <1843200>;
 152                                         current-speed = <115200>;
 153                                 };
 154
 155                                 pciuart3: uart@a,4 {
 156                                         compatible = "pci8086,8814.00",
 157                                                         "pci8086,8814",
 158                                                         "pciclass,070002",
 159                                                         "pciclass,0700",
 160                                                         "x86-uart";
 161                                         u-boot,dm-pre-reloc;
 162                                         reg = <0x00025400 0x0 0x0 0x0 0x0
 163                                                0x01025410 0x0 0x0 0x0 0x0>;
 164                                         reg-shift = <0>;
 165                                         clock-frequency = <1843200>;
 166                                         current-speed = <115200>;
 167                                 };
 168                         };
 169                 };
 170
 171                 irq-router@1f,0 {
 172                         reg = <0x0000f800 0 0 0 0>;
 173                         compatible = "intel,irq-router";
 174                         intel,pirq-config = "pci";
 175                         intel,pirq-link = <0x60 8>;
 176                         intel,pirq-mask = <0xcee0>;
 177                         intel,pirq-routing = <
 178                                 /* TunnelCreek PCI devices */
 179                                 PCI_BDF(0, 2, 0) INTA PIRQE
 180                                 PCI_BDF(0, 3, 0) INTA PIRQF
 181                                 PCI_BDF(0, 23, 0) INTA PIRQA
 182                                 PCI_BDF(0, 23, 0) INTB PIRQB
 183                                 PCI_BDF(0, 23, 0) INTC PIRQC
 184                                 PCI_BDF(0, 23, 0) INTD PIRQD
 185                                 PCI_BDF(0, 24, 0) INTA PIRQB
 186                                 PCI_BDF(0, 24, 0) INTB PIRQC
 187                                 PCI_BDF(0, 24, 0) INTC PIRQD
 188                                 PCI_BDF(0, 24, 0) INTD PIRQA
 189                                 PCI_BDF(0, 25, 0) INTA PIRQC
 190                                 PCI_BDF(0, 25, 0) INTB PIRQD
 191                                 PCI_BDF(0, 25, 0) INTC PIRQA
 192                                 PCI_BDF(0, 25, 0) INTD PIRQB
 193                                 PCI_BDF(0, 26, 0) INTA PIRQD
 194                                 PCI_BDF(0, 26, 0) INTB PIRQA
 195                                 PCI_BDF(0, 26, 0) INTC PIRQB
 196                                 PCI_BDF(0, 26, 0) INTD PIRQC
 197                                 PCI_BDF(0, 27, 0) INTA PIRQG
 198                                 /*
 199                                  * Topcliff PCI devices
 200                                  *
 201                                  * Note on the Crown Bay board, Topcliff chipset
 202                                  * is connected to TunnelCreek PCIe port 0, so
 203                                  * its bus number is 1 for its PCIe port and 2
 204                                  * for its PCI devices per U-Boot current PCI
 205                                  * bus enumeration algorithm.
 206                                  */
 207                                 PCI_BDF(1, 0, 0) INTA PIRQA
 208                                 PCI_BDF(2, 0, 1) INTA PIRQA
 209                                 PCI_BDF(2, 0, 2) INTA PIRQA
 210                                 PCI_BDF(2, 2, 0) INTB PIRQD
 211                                 PCI_BDF(2, 2, 1) INTB PIRQD
 212                                 PCI_BDF(2, 2, 2) INTB PIRQD
 213                                 PCI_BDF(2, 2, 3) INTB PIRQD
 214                                 PCI_BDF(2, 2, 4) INTB PIRQD
 215                                 PCI_BDF(2, 4, 0) INTC PIRQC
 216                                 PCI_BDF(2, 4, 1) INTC PIRQC
 217                                 PCI_BDF(2, 6, 0) INTD PIRQB
 218                                 PCI_BDF(2, 8, 0) INTA PIRQA
 219                                 PCI_BDF(2, 8, 1) INTA PIRQA
 220                                 PCI_BDF(2, 8, 2) INTA PIRQA
 221                                 PCI_BDF(2, 8, 3) INTA PIRQA
 222                                 PCI_BDF(2, 10, 0) INTB PIRQD
 223                                 PCI_BDF(2, 10, 1) INTB PIRQD
 224                                 PCI_BDF(2, 10, 2) INTB PIRQD
 225                                 PCI_BDF(2, 10, 3) INTB PIRQD
 226                                 PCI_BDF(2, 10, 4) INTB PIRQD
 227                                 PCI_BDF(2, 12, 0) INTC PIRQC
 228                                 PCI_BDF(2, 12, 1) INTC PIRQC
 229                                 PCI_BDF(2, 12, 2) INTC PIRQC
 230                                 PCI_BDF(2, 12, 3) INTC PIRQC
 231                                 PCI_BDF(2, 12, 4) INTC PIRQC
 232                         >;
 233                 };
 234         };
 235
 236 };