board/amcc/ocotea/ocotea.c

   1 /*
   2  *  Copyright (C) 2004 PaulReynolds@lhsolutions.com
   3  *
   4  * (C) Copyright 2005
   5  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26
  27 #include <common.h>
  28 #include "ocotea.h"
  29 #include <asm/processor.h>
  30 #include <spd_sdram.h>
  31 #include <asm/ppc4xx-emac.h>
  32
  33 DECLARE_GLOBAL_DATA_PTR;
  34
  35 #define BOOT_SMALL_FLASH        32      /* 00100000 */
  36 #define FLASH_ONBD_N            2       /* 00000010 */
  37 #define FLASH_SRAM_SEL          1       /* 00000001 */
  38
  39 long int fixed_sdram (void);
  40 void fpga_init (void);
  41
  42 int board_early_init_f (void)
  43 {
  44         unsigned long mfr;
  45         unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
  46         unsigned char switch_status;
  47         unsigned long cs0_base;
  48         unsigned long cs0_size;
  49         unsigned long cs0_twt;
  50         unsigned long cs2_base;
  51         unsigned long cs2_size;
  52         unsigned long cs2_twt;
  53
  54         /*-------------------------------------------------------------------------+
  55           | Initialize EBC CONFIG
  56           +-------------------------------------------------------------------------*/
  57         mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
  58               EBC_CFG_PTD_ENABLE | EBC_CFG_RTC_64PERCLK |
  59               EBC_CFG_ATC_PREVIOUS | EBC_CFG_DTC_PREVIOUS |
  60               EBC_CFG_CTC_PREVIOUS | EBC_CFG_EMC_NONDEFAULT |
  61               EBC_CFG_PME_DISABLE | EBC_CFG_PR_32);
  62
  63         /*-------------------------------------------------------------------------+
  64           | FPGA. Initialize bank 7 with default values.
  65           +-------------------------------------------------------------------------*/
  66         mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
  67               EBC_BXAP_BCE_DISABLE|
  68               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
  69               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
  70               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
  71               EBC_BXAP_BEM_WRITEONLY|
  72               EBC_BXAP_PEN_DISABLED);
  73         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
  74               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
  75
  76         /* read FPGA base register FPGA_REG0 */
  77         switch_status = *fpga_base;
  78
  79         if (switch_status & 0x40) {
  80                 cs0_base = 0xFFE00000;
  81                 cs0_size = EBC_BXCR_BS_2MB;
  82                 cs0_twt = 8;
  83                 cs2_base = 0xFF800000;
  84                 cs2_size = EBC_BXCR_BS_4MB;
  85                 cs2_twt = 10;
  86         } else {
  87                 cs0_base = 0xFFC00000;
  88                 cs0_size = EBC_BXCR_BS_4MB;
  89                 cs0_twt = 10;
  90                 cs2_base = 0xFF800000;
  91                 cs2_size = EBC_BXCR_BS_2MB;
  92                 cs2_twt = 8;
  93         }
  94
  95         /*-------------------------------------------------------------------------+
  96           | 1 MB FLASH / 1 MB SRAM. Initialize bank 0 with default values.
  97           +-------------------------------------------------------------------------*/
  98         mtebc(PB0AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs0_twt)|
  99               EBC_BXAP_BCE_DISABLE|
 100               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 101               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 102               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 103               EBC_BXAP_BEM_WRITEONLY|
 104               EBC_BXAP_PEN_DISABLED);
 105         mtebc(PB0CR, EBC_BXCR_BAS_ENCODE(cs0_base)|
 106               cs0_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 107
 108         /*-------------------------------------------------------------------------+
 109           | 8KB NVRAM/RTC. Initialize bank 1 with default values.
 110           +-------------------------------------------------------------------------*/
 111         mtebc(PB1AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(10)|
 112               EBC_BXAP_BCE_DISABLE|
 113               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 114               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 115               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 116               EBC_BXAP_BEM_WRITEONLY|
 117               EBC_BXAP_PEN_DISABLED);
 118         mtebc(PB1CR, EBC_BXCR_BAS_ENCODE(0x48000000)|
 119               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 120
 121         /*-------------------------------------------------------------------------+
 122           | 4 MB FLASH. Initialize bank 2 with default values.
 123           +-------------------------------------------------------------------------*/
 124         mtebc(PB2AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(cs2_twt)|
 125               EBC_BXAP_BCE_DISABLE|
 126               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 127               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 128               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 129               EBC_BXAP_BEM_WRITEONLY|
 130               EBC_BXAP_PEN_DISABLED);
 131         mtebc(PB2CR, EBC_BXCR_BAS_ENCODE(cs2_base)|
 132               cs2_size|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 133
 134         /*-------------------------------------------------------------------------+
 135           | FPGA. Initialize bank 7 with default values.
 136           +-------------------------------------------------------------------------*/
 137         mtebc(PB7AP, EBC_BXAP_BME_DISABLED|EBC_BXAP_TWT_ENCODE(7)|
 138               EBC_BXAP_BCE_DISABLE|
 139               EBC_BXAP_CSN_ENCODE(1)|EBC_BXAP_OEN_ENCODE(1)|
 140               EBC_BXAP_WBN_ENCODE(1)|EBC_BXAP_WBF_ENCODE(1)|
 141               EBC_BXAP_TH_ENCODE(1)|EBC_BXAP_RE_DISABLED|
 142               EBC_BXAP_BEM_WRITEONLY|
 143               EBC_BXAP_PEN_DISABLED);
 144         mtebc(PB7CR, EBC_BXCR_BAS_ENCODE(0x48300000)|
 145               EBC_BXCR_BS_1MB|EBC_BXCR_BU_RW|EBC_BXCR_BW_8BIT);
 146
 147         /*--------------------------------------------------------------------
 148          * Setup the interrupt controller polarities, triggers, etc.
 149          *-------------------------------------------------------------------*/
 150         /*
 151          * Because of the interrupt handling rework to handle 440GX interrupts
 152          * with the common code, we needed to change names of the UIC registers.
 153          * Here the new relationship:
 154          *
 155          * U-Boot name  440GX name
 156          * -----------------------
 157          * UIC0         UICB0
 158          * UIC1         UIC0
 159          * UIC2         UIC1
 160          * UIC3         UIC2
 161          */
 162         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 163         mtdcr (UIC1ER, 0x00000000);     /* disable all */
 164         mtdcr (UIC1CR, 0x00000009);     /* SMI & UIC1 crit are critical */
 165         mtdcr (UIC1PR, 0xfffffe13);     /* per ref-board manual */
 166         mtdcr (UIC1TR, 0x01c00008);     /* per ref-board manual */
 167         mtdcr (UIC1VR, 0x00000001);     /* int31 highest, base=0x000 */
 168         mtdcr (UIC1SR, 0xffffffff);     /* clear all */
 169
 170         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 171         mtdcr (UIC2ER, 0x00000000);     /* disable all */
 172         mtdcr (UIC2CR, 0x00000000);     /* all non-critical */
 173         mtdcr (UIC2PR, 0xffffe0ff);     /* per ref-board manual */
 174         mtdcr (UIC2TR, 0x00ffc000);     /* per ref-board manual */
 175         mtdcr (UIC2VR, 0x00000001);     /* int31 highest, base=0x000 */
 176         mtdcr (UIC2SR, 0xffffffff);     /* clear all */
 177
 178         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 179         mtdcr (UIC3ER, 0x00000000);     /* disable all */
 180         mtdcr (UIC3CR, 0x00000000);     /* all non-critical */
 181         mtdcr (UIC3PR, 0xffffffff);     /* per ref-board manual */
 182         mtdcr (UIC3TR, 0x00ff8c0f);     /* per ref-board manual */
 183         mtdcr (UIC3VR, 0x00000001);     /* int31 highest, base=0x000 */
 184         mtdcr (UIC3SR, 0xffffffff);     /* clear all */
 185
 186         mtdcr (UIC0SR, 0xfc000000); /* clear all */
 187         mtdcr (UIC0ER, 0x00000000); /* disable all */
 188         mtdcr (UIC0CR, 0x00000000); /* all non-critical */
 189         mtdcr (UIC0PR, 0xfc000000); /* */
 190         mtdcr (UIC0TR, 0x00000000); /* */
 191         mtdcr (UIC0VR, 0x00000001); /* */
 192         mfsdr (SDR0_MFR, mfr);
 193         mfr &= ~SDR0_MFR_ECS_MASK;
 194 /*      mtsdr(SDR0_MFR, mfr); */
 195         fpga_init();
 196
 197         return 0;
 198 }
 199
 200
 201 int checkboard (void)
 202 {
 203         char buf[64];
 204         int i = getenv_f("serial#", buf, sizeof(buf));
 205
 206         printf ("Board: Ocotea - AMCC PPC440GX Evaluation Board");
 207         if (i > 0) {
 208                 puts(", serial# ");
 209                 puts(buf);
 210         }
 211         putc ('\n');
 212
 213         return (0);
 214 }
 215
 216
 217 phys_size_t initdram (int board_type)
 218 {
 219         long dram_size = 0;
 220
 221 #if defined(CONFIG_SPD_EEPROM)
 222         dram_size = spd_sdram ();
 223 #else
 224         dram_size = fixed_sdram ();
 225 #endif
 226         return dram_size;
 227 }
 228
 229
 230 #if !defined(CONFIG_SPD_EEPROM)
 231 /*************************************************************************
 232  *  fixed sdram init -- doesn't use serial presence detect.
 233  *
 234  *  Assumes:    128 MB, non-ECC, non-registered
 235  *              PLB @ 133 MHz
 236  *
 237  ************************************************************************/
 238 long int fixed_sdram (void)
 239 {
 240         uint reg;
 241
 242         /*--------------------------------------------------------------------
 243          * Setup some default
 244          *------------------------------------------------------------------*/
 245         mtsdram (SDRAM0_UABBA, 0x00000000);     /* ubba=0 (default)             */
 246         mtsdram (SDRAM0_SLIO, 0x00000000);              /* rdre=0 wrre=0 rarw=0         */
 247         mtsdram (SDRAM0_DEVOPT, 0x00000000);    /* dll=0 ds=0 (normal)          */
 248         mtsdram (SDRAM0_WDDCTR, 0x00000000);    /* wrcp=0 dcd=0                 */
 249         mtsdram (SDRAM0_CLKTR, 0x40000000);     /* clkp=1 (90 deg wr) dcdt=0    */
 250
 251         /*--------------------------------------------------------------------
 252          * Setup for board-specific specific mem
 253          *------------------------------------------------------------------*/
 254         /*
 255          * Following for CAS Latency = 2.5 @ 133 MHz PLB
 256          */
 257         mtsdram (SDRAM0_B0CR, 0x000a4001);      /* SDBA=0x000 128MB, Mode 3, enabled */
 258         mtsdram (SDRAM0_TR0, 0x410a4012);       /* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
 259         /* RA=10 RD=3                       */
 260         mtsdram (SDRAM0_TR1, 0x8080082f);       /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
 261         mtsdram (SDRAM0_RTR, 0x08200000);       /* Rate 15.625 ns @ 133 MHz PLB     */
 262         mtsdram (SDRAM0_CFG1, 0x00000000);      /* Self-refresh exit, disable PM    */
 263         udelay (400);                   /* Delay 200 usecs (min)            */
 264
 265         /*--------------------------------------------------------------------
 266          * Enable the controller, then wait for DCEN to complete
 267          *------------------------------------------------------------------*/
 268         mtsdram (SDRAM0_CFG0, 0x86000000);      /* DCEN=1, PMUD=1, 64-bit           */
 269         for (;;) {
 270                 mfsdram (SDRAM0_MCSTS, reg);
 271                 if (reg & 0x80000000)
 272                         break;
 273         }
 274
 275         return (128 * 1024 * 1024);     /* 128 MB                           */
 276 }
 277 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 278
 279 void fpga_init(void)
 280 {
 281         unsigned long group;
 282         unsigned long sdr0_pfc0;
 283         unsigned long sdr0_pfc1;
 284         unsigned long sdr0_cust0;
 285         unsigned long pvr;
 286
 287         mfsdr (SDR0_PFC0, sdr0_pfc0);
 288         mfsdr (SDR0_PFC1, sdr0_pfc1);
 289         group = SDR0_PFC1_EPS_DECODE(sdr0_pfc1);
 290         pvr = get_pvr ();
 291
 292         sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_GEIE_MASK) | SDR0_PFC0_GEIE_TRE;
 293         if ( ((pvr == PVR_440GX_RA) || (pvr == PVR_440GX_RB)) && ((group == 4) || (group == 5))) {
 294                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_DISABLE;
 295                 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
 296                 out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 297                      FPGA_REG2_EXT_INTFACE_ENABLE);
 298                 mtsdr (SDR0_PFC0, sdr0_pfc0);
 299                 mtsdr (SDR0_PFC1, sdr0_pfc1);
 300         } else {
 301                 sdr0_pfc0 = (sdr0_pfc0 & ~SDR0_PFC0_TRE_MASK) | SDR0_PFC0_TRE_ENABLE;
 302                 switch (group)
 303                 {
 304                 case 0:
 305                 case 1:
 306                 case 2:
 307                         /* CPU trace A */
 308                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 309                              FPGA_REG2_EXT_INTFACE_ENABLE);
 310                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_EMS;
 311                         mtsdr (SDR0_PFC0, sdr0_pfc0);
 312                         mtsdr (SDR0_PFC1, sdr0_pfc1);
 313                         break;
 314                 case 3:
 315                 case 4:
 316                 case 5:
 317                 case 6:
 318                         /* CPU trace B - Over EBMI */
 319                         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_CTEMS_MASK) | SDR0_PFC1_CTEMS_CPUTRACE;
 320                         mtsdr (SDR0_PFC0, sdr0_pfc0);
 321                         mtsdr (SDR0_PFC1, sdr0_pfc1);
 322                         out8(FPGA_REG2, (in8(FPGA_REG2) & ~FPGA_REG2_EXT_INTFACE_MASK) |
 323                              FPGA_REG2_EXT_INTFACE_DISABLE);
 324                         break;
 325                 }
 326         }
 327
 328         /* Initialize the ethernet specific functions in the fpga */
 329         mfsdr(SDR0_PFC1, sdr0_pfc1);
 330         mfsdr(SDR0_CUST0, sdr0_cust0);
 331         if ( (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) == 4) &&
 332             ((SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII) ||
 333              (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_TBI)))
 334         {
 335                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 336                 {
 337                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
 338                              FPGA_REG3_ENET_GROUP7);
 339                 }
 340                 else
 341                 {
 342                         if (SDR0_CUST0_RGMII2_DECODE(sdr0_cust0) == RGMII_FER_GMII)
 343                         {
 344                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 345                                      FPGA_REG3_ENET_GROUP7);
 346                         }
 347                         else
 348                         {
 349                                 out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 350                                      FPGA_REG3_ENET_GROUP8);
 351                         }
 352                 }
 353         }
 354         else
 355         {
 356                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 357                 {
 358                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK1) |
 359                              FPGA_REG3_ENET_ENCODE1(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
 360                 }
 361                 else
 362                 {
 363                         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_ENET_MASK2) |
 364                              FPGA_REG3_ENET_ENCODE2(SDR0_PFC1_EPS_DECODE(sdr0_pfc1)));
 365                 }
 366         }
 367         out8(FPGA_REG4, FPGA_REG4_GPHY_MODE10 |
 368              FPGA_REG4_GPHY_MODE100 | FPGA_REG4_GPHY_MODE1000 |
 369              FPGA_REG4_GPHY_FRC_DPLX | FPGA_REG4_CONNECT_PHYS);
 370
 371         /* reset the gigabyte phy if necessary */
 372         if (SDR0_PFC1_EPS_DECODE(sdr0_pfc1) >= 3)
 373         {
 374                 if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER1)
 375                 {
 376                         out8(FPGA_REG3, in8(FPGA_REG3) & ~FPGA_REG3_GIGABIT_RESET_DISABLE);
 377                         udelay(10000);
 378                         out8(FPGA_REG3, in8(FPGA_REG3) | FPGA_REG3_GIGABIT_RESET_DISABLE);
 379                 }
 380                 else
 381                 {
 382                         out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_GIGABIT_RESET_DISABLE);
 383                         udelay(10000);
 384                         out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_GIGABIT_RESET_DISABLE);
 385                 }
 386         }
 387
 388         /*
 389          * new Ocotea with Rev. F (pass 3) chips has SMII PHY reset
 390          */
 391         if ((in8(FPGA_REG0) & FPGA_REG0_ECLS_MASK) == FPGA_REG0_ECLS_VER2) {
 392                 out8(FPGA_REG2, in8(FPGA_REG2) & ~FPGA_REG2_SMII_RESET_DISABLE);
 393                 udelay(10000);
 394                 out8(FPGA_REG2, in8(FPGA_REG2) | FPGA_REG2_SMII_RESET_DISABLE);
 395         }
 396
 397         /* Turn off the LED's */
 398         out8(FPGA_REG3, (in8(FPGA_REG3) & ~FPGA_REG3_STAT_MASK) |
 399              FPGA_REG3_STAT_LED8_DISAB | FPGA_REG3_STAT_LED4_DISAB |
 400              FPGA_REG3_STAT_LED2_DISAB | FPGA_REG3_STAT_LED1_DISAB);
 401
 402         return;
 403 }