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mxc_ipuv3: fix memory alignment of framebuffer
[karo-tx-uboot.git] / board / amcc / sequoia / chip_config.c
1 /*
2  * (C) Copyright 2009
3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
4  *
5  * See file CREDITS for list of people who contributed to this
6  * project.
7  *
8  * This program is free software; you can redistribute it and/or
9  * modify it under the terms of the GNU General Public License as
10  * published by the Free Software Foundation; either version 2 of
11  * the License, or (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21  * MA 02111-1307 USA
22  *
23  */
24
25 #include <common.h>
26 #include <asm/ppc4xx_config.h>
27
28 struct ppc4xx_config ppc4xx_config_val[] = {
29         {
30                 "333-133-nor", "NOR  CPU: 333 PLB: 133 OPB:  66 EBC:  66",
31                 {
32                         0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10,
33                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
34                 }
35         },
36         {
37                 "333-166-nor", "NOR  CPU: 333 PLB: 166 OPB:  83 EBC:  55",
38                 {
39                         0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30,
40                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
41                 }
42         },
43         {
44                 "333-166-nand", "NAND CPU: 333 PLB: 166 OPB:  83 EBC:  55",
45                 {
46                         0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xd0, 0x30,
47                         0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
48                 }
49         },
50         {
51                 "400-133-nor", "NOR  CPU: 400 PLB: 133 OPB:  66 EBC:  66",
52                 {
53                         0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30,
54                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
55                 }
56         },
57         {
58                 "400-160-nor", "NOR  CPU: 400 PLB: 160 OPB:  80 EBC:  53",
59                 {
60                         0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
61                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
62                 }
63         },
64         {
65                 "416-166-nor", "NOR  CPU: 416 PLB: 166 OPB:  83 EBC:  55",
66                 {
67                         0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10,
68                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
69                 }
70         },
71         {
72                 "416-166-nand", "NAND CPU: 416 PLB: 166 OPB:  83 EBC:  55",
73                 {
74                         0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xd0, 0x10,
75                         0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
76                 }
77         },
78         {
79                 "500-166-nor", "NOR  CPU: 500 PLB: 166 OPB:  83 EBC:  55",
80                 {
81                         0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30,
82                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
83                 }
84         },
85         {
86                 "500-166-nand", "NAND CPU: 500 PLB: 166 OPB:  83 EBC:  55",
87                 {
88                         0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xd0, 0x30,
89                         0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
90                 }
91         },
92         {
93                 "533-133-nor", "NOR  CPU: 533 PLB: 133 OPB:  66 EBC:  66",
94                 {
95                         0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
96                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
97                 }
98         },
99         {
100                 "667-133-nor", "NOR  CPU: 667 PLB: 133 OPB:  66 EBC:  66",
101                 {
102                         0x87, 0x78, 0xa2, 0x56, 0x09, 0x57, 0xa0, 0x30,
103                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
104                 }
105         },
106         {
107                 "667-166-nor", "NOR  CPU: 667 PLB: 166 OPB:  83 EBC:  55",
108                 {
109                         0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
110                         0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
111                 }
112         },
113         {
114                 "667-166-nand", "NAND CPU: 667 PLB: 166 OPB:  83 EBC:  55",
115                 {
116                         0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x30,
117                         0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
118                 }
119         },
120 };
121
122 int ppc4xx_config_count = ARRAY_SIZE(ppc4xx_config_val);