board/amcc/taishan/showinfo.c

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <config.h>
   9 #include <common.h>
  10 #include <command.h>
  11 #include <asm/processor.h>
  12 #include <pci.h>
  13
  14 void show_reset_reg(void)
  15 {
  16         unsigned long reg;
  17
  18         /* read clock regsiter */
  19         printf("===== Display reset and initialize register Start =========\n");
  20         mfcpr(CPR0_PLLC,reg);
  21         printf("cpr_pllc   = %#010lx\n",reg);
  22
  23         mfcpr(CPR0_PLLD,reg);
  24         printf("cpr_plld   = %#010lx\n",reg);
  25
  26         mfcpr(CPR0_PRIMAD0,reg);
  27         printf("cpr_primad = %#010lx\n",reg);
  28
  29         mfcpr(CPR0_PRIMBD0,reg);
  30         printf("cpr_primbd = %#010lx\n",reg);
  31
  32         mfcpr(CPR0_OPBD0,reg);
  33         printf("cpr_opbd   = %#010lx\n",reg);
  34
  35         mfcpr(CPR0_PERD,reg);
  36         printf("cpr_perd   = %#010lx\n",reg);
  37
  38         mfcpr(CPR0_MALD,reg);
  39         printf("cpr_mald   = %#010lx\n",reg);
  40
  41         /* read sdr register */
  42         mfsdr(SDR0_EBC,reg);
  43         printf("SDR0_EBC    = %#010lx\n",reg);
  44
  45         mfsdr(SDR0_CP440,reg);
  46         printf("SDR0_CP440  = %#010lx\n",reg);
  47
  48         mfsdr(SDR0_XCR,reg);
  49         printf("SDR0_XCR    = %#010lx\n",reg);
  50
  51         mfsdr(SDR0_XPLLC,reg);
  52         printf("SDR0_XPLLC  = %#010lx\n",reg);
  53
  54         mfsdr(SDR0_XPLLD,reg);
  55         printf("SDR0_XPLLD  = %#010lx\n",reg);
  56
  57         mfsdr(SDR0_PFC0,reg);
  58         printf("SDR0_PFC0   = %#010lx\n",reg);
  59
  60         mfsdr(SDR0_PFC1,reg);
  61         printf("SDR0_PFC1   = %#010lx\n",reg);
  62
  63         mfsdr(SDR0_CUST0,reg);
  64         printf("SDR0_CUST0  = %#010lx\n",reg);
  65
  66         mfsdr(SDR0_CUST1,reg);
  67         printf("SDR0_CUST1  = %#010lx\n",reg);
  68
  69         mfsdr(SDR0_UART0,reg);
  70         printf("SDR0_UART0  = %#010lx\n",reg);
  71
  72         mfsdr(SDR0_UART1,reg);
  73         printf("SDR0_UART1  = %#010lx\n",reg);
  74
  75         printf("===== Display reset and initialize register End   =========\n");
  76 }
  77
  78 void show_xbridge_info(void)
  79 {
  80         unsigned long reg;
  81
  82         printf("PCI-X chip control registers\n");
  83         mfsdr(SDR0_XCR, reg);
  84         printf("SDR0_XCR    = %#010lx\n", reg);
  85
  86         mfsdr(SDR0_XPLLC, reg);
  87         printf("SDR0_XPLLC  = %#010lx\n", reg);
  88
  89         mfsdr(SDR0_XPLLD, reg);
  90         printf("SDR0_XPLLD  = %#010lx\n", reg);
  91
  92         printf("PCI-X Bridge Configure registers\n");
  93         printf("PCIL0_VENDID            = %#06x\n", in16r(PCIL0_VENDID));
  94         printf("PCIL0_DEVID             = %#06x\n", in16r(PCIL0_DEVID));
  95         printf("PCIL0_CMD               = %#06x\n", in16r(PCIL0_CMD));
  96         printf("PCIL0_STATUS            = %#06x\n", in16r(PCIL0_STATUS));
  97         printf("PCIL0_REVID             = %#04x\n", in8(PCIL0_REVID));
  98         printf("PCIL0_CACHELS           = %#04x\n", in8(PCIL0_CACHELS));
  99         printf("PCIL0_LATTIM            = %#04x\n", in8(PCIL0_LATTIM));
 100         printf("PCIL0_HDTYPE            = %#04x\n", in8(PCIL0_HDTYPE));
 101         printf("PCIL0_BIST              = %#04x\n", in8(PCIL0_BIST));
 102
 103         printf("PCIL0_BAR0              = %#010lx\n", in32r(PCIL0_BAR0));
 104         printf("PCIL0_BAR1              = %#010lx\n", in32r(PCIL0_BAR1));
 105         printf("PCIL0_BAR2              = %#010lx\n", in32r(PCIL0_BAR2));
 106         printf("PCIL0_BAR3              = %#010lx\n", in32r(PCIL0_BAR3));
 107         printf("PCIL0_BAR4              = %#010lx\n", in32r(PCIL0_BAR4));
 108         printf("PCIL0_BAR5              = %#010lx\n", in32r(PCIL0_BAR5));
 109
 110         printf("PCIL0_CISPTR            = %#010lx\n", in32r(PCIL0_CISPTR));
 111         printf("PCIL0_SBSSYSVID         = %#010x\n", in16r(PCIL0_SBSYSVID));
 112         printf("PCIL0_SBSSYSID          = %#010x\n", in16r(PCIL0_SBSYSID));
 113         printf("PCIL0_EROMBA            = %#010lx\n", in32r(PCIL0_EROMBA));
 114         printf("PCIL0_CAP               = %#04x\n", in8(PCIL0_CAP));
 115         printf("PCIL0_INTLN             = %#04x\n", in8(PCIL0_INTLN));
 116         printf("PCIL0_INTPN             = %#04x\n", in8(PCIL0_INTPN));
 117         printf("PCIL0_MINGNT            = %#04x\n", in8(PCIL0_MINGNT));
 118         printf("PCIL0_MAXLTNCY          = %#04x\n", in8(PCIL0_MAXLTNCY));
 119
 120         printf("PCIL0_BRDGOPT1          = %#010lx\n", in32r(PCIL0_BRDGOPT1));
 121         printf("PCIL0_BRDGOPT2          = %#010lx\n", in32r(PCIL0_BRDGOPT2));
 122
 123         printf("PCIL0_POM0LAL           = %#010lx\n", in32r(PCIL0_POM0LAL));
 124         printf("PCIL0_POM0LAH           = %#010lx\n", in32r(PCIL0_POM0LAH));
 125         printf("PCIL0_POM0SA            = %#010lx\n", in32r(PCIL0_POM0SA));
 126         printf("PCIL0_POM0PCILAL        = %#010lx\n", in32r(PCIL0_POM0PCIAL));
 127         printf("PCIL0_POM0PCILAH        = %#010lx\n", in32r(PCIL0_POM0PCIAH));
 128         printf("PCIL0_POM1LAL           = %#010lx\n", in32r(PCIL0_POM1LAL));
 129         printf("PCIL0_POM1LAH           = %#010lx\n", in32r(PCIL0_POM1LAH));
 130         printf("PCIL0_POM1SA            = %#010lx\n", in32r(PCIL0_POM1SA));
 131         printf("PCIL0_POM1PCILAL        = %#010lx\n", in32r(PCIL0_POM1PCIAL));
 132         printf("PCIL0_POM1PCILAH        = %#010lx\n", in32r(PCIL0_POM1PCIAH));
 133         printf("PCIL0_POM2SA            = %#010lx\n", in32r(PCIL0_POM2SA));
 134
 135         printf("PCIL0_PIM0SA            = %#010lx\n", in32r(PCIL0_PIM0SA));
 136         printf("PCIL0_PIM0LAL           = %#010lx\n", in32r(PCIL0_PIM0LAL));
 137         printf("PCIL0_PIM0LAH           = %#010lx\n", in32r(PCIL0_PIM0LAH));
 138         printf("PCIL0_PIM1SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
 139         printf("PCIL0_PIM1LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
 140         printf("PCIL0_PIM1LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
 141         printf("PCIL0_PIM2SA            = %#010lx\n", in32r(PCIL0_PIM1SA));
 142         printf("PCIL0_PIM2LAL           = %#010lx\n", in32r(PCIL0_PIM1LAL));
 143         printf("PCIL0_PIM2LAH           = %#010lx\n", in32r(PCIL0_PIM1LAH));
 144
 145         printf("PCIL0_XSTS              = %#010lx\n", in32r(PCIL0_STS));
 146 }
 147
 148 int do_show_xbridge_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 149 {
 150         show_xbridge_info();
 151         return 0;
 152 }
 153
 154 U_BOOT_CMD(xbriinfo, 1, 1, do_show_xbridge_info,
 155            "Show PCIX bridge info", "");
 156
 157 #define TAISHAN_PCI_DEV_ID0 0x800
 158 #define TAISHAN_PCI_DEV_ID1 0x1000
 159
 160 void show_pcix_device_info(void)
 161 {
 162         int ii;
 163         int dev;
 164         u8 capp;
 165         u8 xcapid;
 166         u16 status;
 167         u16 xcommand;
 168         u32 xstatus;
 169
 170         for (ii = 0; ii < 2; ii++) {
 171                 if (ii == 0)
 172                         dev = TAISHAN_PCI_DEV_ID0;
 173                 else
 174                         dev = TAISHAN_PCI_DEV_ID1;
 175
 176                 pci_read_config_word(dev, PCI_STATUS, &status);
 177                 if (status & PCI_STATUS_CAP_LIST) {
 178                         pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &capp);
 179
 180                         pci_read_config_byte(dev, (int)(capp), &xcapid);
 181                         if (xcapid == 0x07) {
 182                                 pci_read_config_word(dev, (int)(capp + 2),
 183                                                      &xcommand);
 184                                 pci_read_config_dword(dev, (int)(capp + 4),
 185                                                       &xstatus);
 186                                 printf("BUS0 dev%d Xcommand=%#06x,Xstatus=%#010x\n",
 187                                        (ii + 1), xcommand, xstatus);
 188                         } else {
 189                                 printf("BUS0 dev%d PCI-X CAP ID error,"
 190                                        "CAP=%#04x,XCAPID=%#04x\n",
 191                                        (ii + 1), capp, xcapid);
 192                         }
 193                 } else {
 194                         printf("BUS0 dev%d not found PCI_STATUS_CAP_LIST supporting\n",
 195                                ii + 1);
 196                 }
 197         }
 198
 199 }
 200
 201 int do_show_pcix_device_info(cmd_tbl_t * cmdtp, int flag, int argc,
 202                              char * const argv[])
 203 {
 204         show_pcix_device_info();
 205         return 0;
 206 }
 207
 208 U_BOOT_CMD(xdevinfo, 1, 1, do_show_pcix_device_info,
 209            "Show PCIX Device info", "");
 210
 211 extern void show_reset_reg(void);
 212
 213 int do_show_reset_reg_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
 214 {
 215         show_reset_reg();
 216         return 0;
 217 }
 218
 219 U_BOOT_CMD(resetinfo, 1, 1, do_show_reset_reg_info,
 220            "Show Reset REG info", "");