board/atmel/at91sam9m10g45ek/at91sam9m10g45ek.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian@popies.net>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/at91sam9g45_matrix.h>
  12 #include <asm/arch/at91sam9_smc.h>
  13 #include <asm/arch/at91_common.h>
  14 #include <asm/arch/at91_pmc.h>
  15 #include <asm/arch/at91_rstc.h>
  16 #include <asm/arch/gpio.h>
  17 #include <asm/arch/clk.h>
  18 #include <lcd.h>
  19 #include <atmel_lcdc.h>
  20 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  21 #include <net.h>
  22 #endif
  23 #include <netdev.h>
  24
  25 DECLARE_GLOBAL_DATA_PTR;
  26
  27 /* ------------------------------------------------------------------------- */
  28 /*
  29  * Miscelaneous platform dependent initialisations
  30  */
  31
  32 #ifdef CONFIG_CMD_NAND
  33 void at91sam9m10g45ek_nand_hw_init(void)
  34 {
  35         struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  36         struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  37         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  38         unsigned long csa;
  39
  40         /* Enable CS3 */
  41         csa = readl(&matrix->ebicsa);
  42         csa |= AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA;
  43         writel(csa, &matrix->ebicsa);
  44
  45         /* Configure SMC CS3 for NAND/SmartMedia */
  46         writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  47                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  48                &smc->cs[3].setup);
  49         writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(3) |
  50                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(2),
  51                &smc->cs[3].pulse);
  52         writel(AT91_SMC_CYCLE_NWE(7) | AT91_SMC_CYCLE_NRD(4),
  53                &smc->cs[3].cycle);
  54         writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  55                AT91_SMC_MODE_EXNW_DISABLE |
  56 #ifdef CONFIG_SYS_NAND_DBW_16
  57                AT91_SMC_MODE_DBW_16 |
  58 #else /* CONFIG_SYS_NAND_DBW_8 */
  59                AT91_SMC_MODE_DBW_8 |
  60 #endif
  61                AT91_SMC_MODE_TDF_CYCLE(3),
  62                &smc->cs[3].mode);
  63
  64         writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  65
  66         /* Configure RDY/BSY */
  67         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  68
  69         /* Enable NandFlash */
  70         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  71 }
  72 #endif
  73
  74 #ifdef CONFIG_CMD_USB
  75 static void at91sam9m10g45ek_usb_hw_init(void)
  76 {
  77         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  78
  79         writel(1 << ATMEL_ID_PIODE, &pmc->pcer);
  80
  81         at91_set_gpio_output(AT91_PIN_PD1, 0);
  82         at91_set_gpio_output(AT91_PIN_PD3, 0);
  83 }
  84 #endif
  85
  86 #ifdef CONFIG_MACB
  87 static void at91sam9m10g45ek_macb_hw_init(void)
  88 {
  89         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  90         struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  91         struct at91_rstc *rstc = (struct at91_rstc *)ATMEL_BASE_RSTC;
  92         unsigned long erstl;
  93
  94         /* Enable clock */
  95         writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  96
  97         /*
  98          * Disable pull-up on:
  99          *      RXDV (PA15) => PHY normal mode (not Test mode)
 100          *      ERX0 (PA12) => PHY ADDR0
 101          *      ERX1 (PA13) => PHY ADDR1 => PHYADDR = 0x0
 102          *
 103          * PHY has internal pull-down
 104          */
 105         writel(pin_to_mask(AT91_PIN_PA15) |
 106                pin_to_mask(AT91_PIN_PA12) |
 107                pin_to_mask(AT91_PIN_PA13),
 108                &pioa->pudr);
 109
 110         erstl = readl(&rstc->mr) & AT91_RSTC_MR_ERSTL_MASK;
 111
 112         /* Need to reset PHY -> 500ms reset */
 113         writel(AT91_RSTC_KEY | AT91_RSTC_MR_ERSTL(13) |
 114                 AT91_RSTC_MR_URSTEN, &rstc->mr);
 115
 116         writel(AT91_RSTC_KEY | AT91_RSTC_CR_EXTRST, &rstc->cr);
 117
 118         /* Wait for end hardware reset */
 119         while (!(readl(&rstc->sr) & AT91_RSTC_SR_NRSTL))
 120                 ;
 121
 122         /* Restore NRST value */
 123         writel(AT91_RSTC_KEY | erstl | AT91_RSTC_MR_URSTEN,
 124                 &rstc->mr);
 125
 126         /* Re-enable pull-up */
 127         writel(pin_to_mask(AT91_PIN_PA15) |
 128                pin_to_mask(AT91_PIN_PA12) |
 129                pin_to_mask(AT91_PIN_PA13),
 130                &pioa->puer);
 131
 132         /* And the pins. */
 133         at91_macb_hw_init();
 134 }
 135 #endif
 136
 137 #ifdef CONFIG_LCD
 138
 139 vidinfo_t panel_info = {
 140         vl_col:         480,
 141         vl_row:         272,
 142         vl_clk:         9000000,
 143         vl_sync:        ATMEL_LCDC_INVLINE_NORMAL |
 144                         ATMEL_LCDC_INVFRAME_NORMAL,
 145         vl_bpix:        3,
 146         vl_tft:         1,
 147         vl_hsync_len:   45,
 148         vl_left_margin: 1,
 149         vl_right_margin:1,
 150         vl_vsync_len:   1,
 151         vl_upper_margin:40,
 152         vl_lower_margin:1,
 153         mmio :           ATMEL_BASE_LCDC,
 154 };
 155
 156
 157 void lcd_enable(void)
 158 {
 159         at91_set_A_periph(AT91_PIN_PE6, 1);     /* power up */
 160 }
 161
 162 void lcd_disable(void)
 163 {
 164         at91_set_A_periph(AT91_PIN_PE6, 0);     /* power down */
 165 }
 166
 167 static void at91sam9m10g45ek_lcd_hw_init(void)
 168 {
 169         struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
 170
 171         at91_set_A_periph(AT91_PIN_PE0, 0);     /* LCDDPWR */
 172         at91_set_A_periph(AT91_PIN_PE2, 0);     /* LCDCC */
 173         at91_set_A_periph(AT91_PIN_PE3, 0);     /* LCDVSYNC */
 174         at91_set_A_periph(AT91_PIN_PE4, 0);     /* LCDHSYNC */
 175         at91_set_A_periph(AT91_PIN_PE5, 0);     /* LCDDOTCK */
 176
 177         at91_set_A_periph(AT91_PIN_PE7, 0);     /* LCDD0 */
 178         at91_set_A_periph(AT91_PIN_PE8, 0);     /* LCDD1 */
 179         at91_set_A_periph(AT91_PIN_PE9, 0);     /* LCDD2 */
 180         at91_set_A_periph(AT91_PIN_PE10, 0);    /* LCDD3 */
 181         at91_set_A_periph(AT91_PIN_PE11, 0);    /* LCDD4 */
 182         at91_set_A_periph(AT91_PIN_PE12, 0);    /* LCDD5 */
 183         at91_set_A_periph(AT91_PIN_PE13, 0);    /* LCDD6 */
 184         at91_set_A_periph(AT91_PIN_PE14, 0);    /* LCDD7 */
 185         at91_set_A_periph(AT91_PIN_PE15, 0);    /* LCDD8 */
 186         at91_set_A_periph(AT91_PIN_PE16, 0);    /* LCDD9 */
 187         at91_set_A_periph(AT91_PIN_PE17, 0);    /* LCDD10 */
 188         at91_set_A_periph(AT91_PIN_PE18, 0);    /* LCDD11 */
 189         at91_set_A_periph(AT91_PIN_PE19, 0);    /* LCDD12 */
 190         at91_set_B_periph(AT91_PIN_PE20, 0);    /* LCDD13 */
 191         at91_set_A_periph(AT91_PIN_PE21, 0);    /* LCDD14 */
 192         at91_set_A_periph(AT91_PIN_PE22, 0);    /* LCDD15 */
 193         at91_set_A_periph(AT91_PIN_PE23, 0);    /* LCDD16 */
 194         at91_set_A_periph(AT91_PIN_PE24, 0);    /* LCDD17 */
 195         at91_set_A_periph(AT91_PIN_PE25, 0);    /* LCDD18 */
 196         at91_set_A_periph(AT91_PIN_PE26, 0);    /* LCDD19 */
 197         at91_set_A_periph(AT91_PIN_PE27, 0);    /* LCDD20 */
 198         at91_set_B_periph(AT91_PIN_PE28, 0);    /* LCDD21 */
 199         at91_set_A_periph(AT91_PIN_PE29, 0);    /* LCDD22 */
 200         at91_set_A_periph(AT91_PIN_PE30, 0);    /* LCDD23 */
 201
 202         writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 203
 204         gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE;
 205 }
 206
 207 #ifdef CONFIG_LCD_INFO
 208 #include <nand.h>
 209 #include <version.h>
 210
 211 void lcd_show_board_info(void)
 212 {
 213         ulong dram_size, nand_size;
 214         int i;
 215         char temp[32];
 216
 217         lcd_printf ("%s\n", U_BOOT_VERSION);
 218         lcd_printf ("(C) 2008 ATMEL Corp\n");
 219         lcd_printf ("at91support@atmel.com\n");
 220         lcd_printf ("%s CPU at %s MHz\n",
 221                 ATMEL_CPU_NAME,
 222                 strmhz(temp, get_cpu_clk_rate()));
 223
 224         dram_size = 0;
 225         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 226                 dram_size += gd->bd->bi_dram[i].size;
 227         nand_size = 0;
 228         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 229                 nand_size += nand_info[i].size;
 230         lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 231                 dram_size >> 20,
 232                 nand_size >> 20 );
 233 }
 234 #endif /* CONFIG_LCD_INFO */
 235 #endif
 236
 237 int board_early_init_f(void)
 238 {
 239         at91_seriald_hw_init();
 240         return 0;
 241 }
 242
 243 int board_init(void)
 244 {
 245         /* arch number of AT91SAM9M10G45EK-Board */
 246 #ifdef CONFIG_AT91SAM9M10G45EK
 247         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9M10G45EK;
 248 #elif defined CONFIG_AT91SAM9G45EKES
 249         gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9G45EKES;
 250 #endif
 251
 252         /* adress of boot parameters */
 253         gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 254
 255 #ifdef CONFIG_CMD_NAND
 256         at91sam9m10g45ek_nand_hw_init();
 257 #endif
 258 #ifdef CONFIG_CMD_USB
 259         at91sam9m10g45ek_usb_hw_init();
 260 #endif
 261 #ifdef CONFIG_HAS_DATAFLASH
 262         at91_spi0_hw_init(1 << 0);
 263 #endif
 264 #ifdef CONFIG_ATMEL_SPI
 265         at91_spi0_hw_init(1 << 4);
 266 #endif
 267 #ifdef CONFIG_MACB
 268         at91sam9m10g45ek_macb_hw_init();
 269 #endif
 270 #ifdef CONFIG_LCD
 271         at91sam9m10g45ek_lcd_hw_init();
 272 #endif
 273         return 0;
 274 }
 275
 276 int dram_init(void)
 277 {
 278         gd->ram_size = get_ram_size((void *) CONFIG_SYS_SDRAM_BASE,
 279                                     CONFIG_SYS_SDRAM_SIZE);
 280         return 0;
 281 }
 282
 283 #ifdef CONFIG_RESET_PHY_R
 284 void reset_phy(void)
 285 {
 286 }
 287 #endif
 288
 289 int board_eth_init(bd_t *bis)
 290 {
 291         int rc = 0;
 292 #ifdef CONFIG_MACB
 293         rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 294 #endif
 295         return rc;
 296 }
 297
 298 /* SPI chip select control */
 299 #ifdef CONFIG_ATMEL_SPI
 300 #include <spi.h>
 301
 302 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
 303 {
 304         return bus == 0 && cs < 2;
 305 }
 306
 307 void spi_cs_activate(struct spi_slave *slave)
 308 {
 309         switch(slave->cs) {
 310                 case 1:
 311                         at91_set_gpio_output(AT91_PIN_PB18, 0);
 312                         break;
 313                 case 0:
 314                 default:
 315                         at91_set_gpio_output(AT91_PIN_PB3, 0);
 316                         break;
 317         }
 318 }
 319
 320 void spi_cs_deactivate(struct spi_slave *slave)
 321 {
 322         switch(slave->cs) {
 323                 case 1:
 324                         at91_set_gpio_output(AT91_PIN_PB18, 1);
 325                         break;
 326                 case 0:
 327                 default:
 328                         at91_set_gpio_output(AT91_PIN_PB3, 1);
 329                 break;
 330         }
 331 }
 332 #endif /* CONFIG_ATMEL_SPI */