board/bachmann/ot1200/ot1200.c

   1 /*
   2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
   3  * Copyright (C) 2014, Bachmann electronic GmbH
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <malloc.h>
  13 #include <asm/arch/mx6-pins.h>
  14 #include <asm/imx-common/iomux-v3.h>
  15 #include <asm/imx-common/sata.h>
  16 #include <asm/imx-common/mxc_i2c.h>
  17 #include <asm/imx-common/boot_mode.h>
  18 #include <asm/arch/crm_regs.h>
  19 #include <mmc.h>
  20 #include <fsl_esdhc.h>
  21 #include <netdev.h>
  22 #include <i2c.h>
  23 #include <pca953x.h>
  24 #include <asm/gpio.h>
  25 #include <phy.h>
  26
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define OUTPUT_40OHM    (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
  30
  31 #define UART_PAD_CTRL   (PAD_CTL_PUS_100K_UP |                  \
  32         OUTPUT_40OHM | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  33
  34 #define USDHC_PAD_CTRL  (PAD_CTL_PUS_47K_UP |                   \
  35         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  36         PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  37
  38 #define ENET_PAD_CTRL   (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |   \
  39         PAD_CTL_HYS)
  40
  41 #define SPI_PAD_CTRL    (PAD_CTL_HYS | OUTPUT_40OHM |           \
  42         PAD_CTL_SRE_FAST)
  43
  44 #define I2C_PAD_CTRL    (PAD_CTL_PUS_100K_UP | OUTPUT_40OHM |   \
  45         PAD_CTL_HYS | PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  46
  47 int dram_init(void)
  48 {
  49         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  50
  51         return 0;
  52 }
  53
  54 static iomux_v3_cfg_t const uart1_pads[] = {
  55         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  56         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  57 };
  58
  59 static void setup_iomux_uart(void)
  60 {
  61         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  62 }
  63
  64 static iomux_v3_cfg_t const enet_pads[] = {
  65         MX6_PAD_KEY_ROW1__ENET_COL | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_KEY_COL3__ENET_CRS | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
  69         MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  70         MX6_PAD_GPIO_18__ENET_RX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  71         MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  72         MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  73         MX6_PAD_KEY_COL2__ENET_RX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  74         MX6_PAD_KEY_COL0__ENET_RX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  75         MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  76         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
  77         MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  78         MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  79         MX6_PAD_KEY_ROW2__ENET_TX_DATA2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  80         MX6_PAD_KEY_ROW0__ENET_TX_DATA3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
  81         MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
  82 };
  83
  84 static void setup_iomux_enet(void)
  85 {
  86         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  87 }
  88
  89 static iomux_v3_cfg_t const ecspi1_pads[] = {
  90         MX6_PAD_DISP0_DAT3__ECSPI3_SS0  | MUX_PAD_CTRL(SPI_PAD_CTRL),
  91         MX6_PAD_DISP0_DAT4__ECSPI3_SS1  | MUX_PAD_CTRL(SPI_PAD_CTRL),
  92         MX6_PAD_DISP0_DAT2__ECSPI3_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
  93         MX6_PAD_DISP0_DAT1__ECSPI3_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
  94         MX6_PAD_DISP0_DAT0__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
  95 };
  96
  97 static void setup_iomux_spi(void)
  98 {
  99         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
 100 }
 101
 102 int board_spi_cs_gpio(unsigned bus, unsigned cs)
 103 {
 104         return (bus == 2 && cs == 0) ? (IMX_GPIO_NR(1, 3)) : -1;
 105 }
 106
 107 static iomux_v3_cfg_t const feature_pads[] = {
 108         /* SD card detect */
 109         MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_DOWN),
 110
 111         /* eMMC soldered? */
 112         MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(PAD_CTL_PUS_100K_UP),
 113 };
 114
 115 static void setup_iomux_features(void)
 116 {
 117         imx_iomux_v3_setup_multiple_pads(feature_pads,
 118                 ARRAY_SIZE(feature_pads));
 119 }
 120
 121 int board_early_init_f(void)
 122 {
 123         setup_iomux_uart();
 124         setup_iomux_spi();
 125         setup_iomux_features();
 126
 127         return 0;
 128 }
 129
 130 static iomux_v3_cfg_t const usdhc3_pads[] = {
 131         MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 132         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 133         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 134         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 141         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 142 };
 143
 144 iomux_v3_cfg_t const usdhc4_pads[] = {
 145         MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146         MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 151 };
 152
 153 int board_mmc_getcd(struct mmc *mmc)
 154 {
 155         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 156         int ret;
 157
 158         if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 159                 gpio_direction_input(IMX_GPIO_NR(4, 5));
 160                 ret = gpio_get_value(IMX_GPIO_NR(4, 5));
 161         } else {
 162                 gpio_direction_input(IMX_GPIO_NR(1, 5));
 163                 ret = !gpio_get_value(IMX_GPIO_NR(1, 5));
 164         }
 165
 166         return ret;
 167 }
 168
 169 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 170         {USDHC3_BASE_ADDR},
 171         {USDHC4_BASE_ADDR},
 172 };
 173
 174 int board_mmc_init(bd_t *bis)
 175 {
 176         int ret;
 177         u32 index = 0;
 178
 179         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 180         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 181
 182         usdhc_cfg[0].max_bus_width = 8;
 183         usdhc_cfg[1].max_bus_width = 4;
 184
 185         for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 186                 switch (index) {
 187                 case 0:
 188                         imx_iomux_v3_setup_multiple_pads(
 189                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 190                         break;
 191                 case 1:
 192                         imx_iomux_v3_setup_multiple_pads(
 193                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 194                         break;
 195                 default:
 196                         printf("Warning: you configured more USDHC controllers"
 197                                 "(%d) then supported by the board (%d)\n",
 198                                 index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 199                         return -EINVAL;
 200                 }
 201
 202                 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 203                 if (ret)
 204                         return ret;
 205         }
 206
 207         return 0;
 208 }
 209
 210 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 211
 212 /* I2C3 - IO expander  */
 213 static struct i2c_pads_info i2c_pad_info2 = {
 214         .scl = {
 215                 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
 216                 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
 217                 .gp = IMX_GPIO_NR(3, 17)
 218         },
 219         .sda = {
 220                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
 221                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
 222                 .gp = IMX_GPIO_NR(3, 18)
 223         }
 224 };
 225
 226 static iomux_v3_cfg_t const pwm_pad[] = {
 227         MX6_PAD_SD1_CMD__PWM4_OUT | MUX_PAD_CTRL(OUTPUT_40OHM),
 228 };
 229
 230 static void leds_on(void)
 231 {
 232         /* turn on all possible leds connected via GPIO expander */
 233         i2c_set_bus_num(2);
 234         pca953x_set_dir(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, PCA953X_DIR_OUT);
 235         pca953x_set_val(CONFIG_SYS_I2C_PCA953X_ADDR, 0xffff, 0x0);
 236 }
 237
 238 static void backlight_lcd_off(void)
 239 {
 240         unsigned gpio = IMX_GPIO_NR(2, 0);
 241         gpio_direction_output(gpio, 0);
 242
 243         gpio = IMX_GPIO_NR(2, 3);
 244         gpio_direction_output(gpio, 0);
 245 }
 246
 247 int board_eth_init(bd_t *bis)
 248 {
 249         uint32_t base = IMX_FEC_BASE;
 250         struct mii_dev *bus = NULL;
 251         struct phy_device *phydev = NULL;
 252         int ret;
 253
 254         setup_iomux_enet();
 255
 256         bus = fec_get_miibus(base, -1);
 257         if (!bus)
 258                 return 0;
 259
 260         /* scan phy 0 and 5 */
 261         phydev = phy_find_by_mask(bus, 0x21, PHY_INTERFACE_MODE_RGMII);
 262         if (!phydev) {
 263                 free(bus);
 264                 return 0;
 265         }
 266
 267         /* depending on the phy address we can detect our board version */
 268         if (phydev->addr == 0)
 269                 setenv("boardver", "");
 270         else
 271                 setenv("boardver", "mr");
 272
 273         printf("using phy at %d\n", phydev->addr);
 274         ret = fec_probe(bis, -1, base, bus, phydev);
 275         if (ret) {
 276                 printf("FEC MXC: %s:failed\n", __func__);
 277                 free(phydev);
 278                 free(bus);
 279         }
 280         return 0;
 281 }
 282
 283 int board_init(void)
 284 {
 285         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 286
 287         backlight_lcd_off();
 288
 289         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 290
 291         leds_on();
 292
 293         /* enable ecspi3 clocks */
 294         enable_cspi_clock(1, 2);
 295
 296 #ifdef CONFIG_CMD_SATA
 297         setup_sata();
 298 #endif
 299
 300         return 0;
 301 }
 302
 303 int checkboard(void)
 304 {
 305         puts("Board: "CONFIG_SYS_BOARD"\n");
 306         return 0;
 307 }
 308
 309 #ifdef CONFIG_CMD_BMODE
 310 static const struct boot_mode board_boot_modes[] = {
 311         /* 4 bit bus width */
 312         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 313         {NULL,          0},
 314 };
 315 #endif
 316
 317 int misc_init_r(void)
 318 {
 319 #ifdef CONFIG_CMD_BMODE
 320         add_board_boot_modes(board_boot_modes);
 321 #endif
 322         return 0;
 323 }