board/balloon3/balloon3.c

   1 /*
   2  * Balloon3 Support
   3  *
   4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation; either version 2 of
   9  * the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  19  * MA 02111-1307 USA
  20  */
  21
  22 #include <common.h>
  23 #include <asm/arch/hardware.h>
  24 #include <asm/arch/pxa.h>
  25 #include <serial.h>
  26 #include <asm/io.h>
  27 #include <spartan3.h>
  28 #include <command.h>
  29
  30 DECLARE_GLOBAL_DATA_PTR;
  31
  32 void balloon3_init_fpga(void);
  33
  34 /*
  35  * Miscelaneous platform dependent initialisations
  36  */
  37
  38 int board_init(void)
  39 {
  40         /* We have RAM, disable cache */
  41         dcache_disable();
  42         icache_disable();
  43
  44         /* arch number of vpac270 */
  45         gd->bd->bi_arch_number = MACH_TYPE_BALLOON3;
  46
  47         /* adress of boot parameters */
  48         gd->bd->bi_boot_params = 0xa0000100;
  49
  50         /* Init the FPGA */
  51         balloon3_init_fpga();
  52
  53         return 0;
  54 }
  55
  56 int dram_init(void)
  57 {
  58         pxa2xx_dram_init();
  59         gd->ram_size = PHYS_SDRAM_1_SIZE;
  60         return 0;
  61 }
  62
  63 void dram_init_banksize(void)
  64 {
  65         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  66         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  67         gd->bd->bi_dram[2].start = PHYS_SDRAM_3;
  68
  69         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  70         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  71         gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE;
  72 }
  73
  74 #ifdef  CONFIG_CMD_USB
  75 int usb_board_init(void)
  76 {
  77         writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
  78                 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
  79                 UHCHR);
  80
  81         writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
  82
  83         while (readl(UHCHR) & UHCHR_FSBIR)
  84                 ;
  85
  86         writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
  87         writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
  88
  89         /* Clear any OTG Pin Hold */
  90         if (readl(PSSR) & PSSR_OTGPH)
  91                 writel(readl(PSSR) | PSSR_OTGPH, PSSR);
  92
  93         writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
  94         writel(readl(UHCRHDA) | 0x100, UHCRHDA);
  95
  96         /* Set port power control mask bits, only 3 ports. */
  97         writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
  98
  99         /* enable port 2 */
 100         writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
 101                 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
 102
 103         return 0;
 104 }
 105
 106 void usb_board_init_fail(void)
 107 {
 108         return;
 109 }
 110
 111 void usb_board_stop(void)
 112 {
 113         writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
 114         udelay(11);
 115         writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
 116
 117         writel(readl(UHCCOMS) | 1, UHCCOMS);
 118         udelay(10);
 119
 120         writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
 121
 122         return;
 123 }
 124 #endif
 125
 126 #if defined(CONFIG_FPGA)
 127 /* Toggle GPIO103 and GPIO104 --  PROGB and RDnWR */
 128 int fpga_pgm_fn(int nassert, int nflush, int cookie)
 129 {
 130         if (nassert)
 131                 writel(0x80, GPCR3);
 132         else
 133                 writel(0x80, GPSR3);
 134         if (nflush)
 135                 writel(0x100, GPCR3);
 136         else
 137                 writel(0x100, GPSR3);
 138         return nassert;
 139 }
 140
 141 /* Check GPIO83 -- INITB */
 142 int fpga_init_fn(int cookie)
 143 {
 144         return !(readl(GPLR2) & 0x80000);
 145 }
 146
 147 /* Check GPIO84 -- BUSY */
 148 int fpga_busy_fn(int cookie)
 149 {
 150         return !(readl(GPLR2) & 0x100000);
 151 }
 152
 153 /* Check GPIO111 -- DONE */
 154 int fpga_done_fn(int cookie)
 155 {
 156         return readl(GPLR3) & 0x8000;
 157 }
 158
 159 /* Configure GPIO104 as GPIO and deassert it */
 160 int fpga_pre_config_fn(int cookie)
 161 {
 162         writel(readl(GAFR3_L) & ~0x30000, GAFR3_L);
 163         writel(0x100, GPCR3);
 164         return 0;
 165 }
 166
 167 /* Configure GPIO104 as nSKTSEL */
 168 int fpga_post_config_fn(int cookie)
 169 {
 170         writel(readl(GAFR3_L) | 0x10000, GAFR3_L);
 171         return 0;
 172 }
 173
 174 /* Toggle RDnWR */
 175 int fpga_wr_fn(int nassert_write, int flush, int cookie)
 176 {
 177         udelay(1000);
 178
 179         if (nassert_write)
 180                 writel(0x100, GPCR3);
 181         else
 182                 writel(0x100, GPSR3);
 183
 184         return nassert_write;
 185 }
 186
 187 /* Write program to the FPGA */
 188 int fpga_wdata_fn(uchar data, int flush, int cookie)
 189 {
 190         writeb(data, 0x10f00000);
 191         return 0;
 192 }
 193
 194 /* Toggle Clock pin -- NO-OP */
 195 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 196 {
 197         return assert_clk;
 198 }
 199
 200 /* Toggle ChipSelect pin -- NO-OP */
 201 int fpga_cs_fn(int assert_clk, int flush, int cookie)
 202 {
 203         return assert_clk;
 204 }
 205
 206 Xilinx_Spartan3_Slave_Parallel_fns balloon3_fpga_fns = {
 207         fpga_pre_config_fn,
 208         fpga_pgm_fn,
 209         fpga_init_fn,
 210         NULL,   /* err */
 211         fpga_done_fn,
 212         fpga_clk_fn,
 213         fpga_cs_fn,
 214         fpga_wr_fn,
 215         NULL,   /* rdata */
 216         fpga_wdata_fn,
 217         fpga_busy_fn,
 218         NULL,   /* abort */
 219         fpga_post_config_fn,
 220 };
 221
 222 Xilinx_desc fpga = XILINX_XC3S1000_DESC(slave_parallel,
 223                         (void *)&balloon3_fpga_fns, 0);
 224
 225 /* Initialize the FPGA */
 226 void balloon3_init_fpga(void)
 227 {
 228         fpga_init();
 229         fpga_add(fpga_xilinx, &fpga);
 230 }
 231 #else
 232 void balloon3_init_fpga(void) {}
 233 #endif /* CONFIG_FPGA */