board/calao/sbc35_a9g20/sbc35_a9g20.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  *
   6  * Copyright (C) 2009
   7  * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 #include <common.h>
  29 #include <asm/arch/at91sam9260.h>
  30 #include <asm/arch/at91sam9260_matrix.h>
  31 #include <asm/arch/at91sam9_smc.h>
  32 #include <asm/arch/at91_common.h>
  33 #include <asm/arch/at91_pmc.h>
  34 #include <asm/arch/at91_rstc.h>
  35 #include <asm/arch/gpio.h>
  36 #include <asm/arch/io.h>
  37 #include <asm/arch/hardware.h>
  38 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  39 #include <net.h>
  40 #endif
  41 #include <netdev.h>
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 /* ------------------------------------------------------------------------- */
  46 /*
  47  * Miscelaneous platform dependent initialisations
  48  */
  49
  50 #ifdef CONFIG_CMD_NAND
  51 static void sbc35_a9g20_nand_hw_init(void)
  52 {
  53         unsigned long csa;
  54
  55         /* Enable CS3 */
  56         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  57         at91_sys_write(AT91_MATRIX_EBICSA,
  58                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  59
  60         /* Configure SMC CS3 for NAND/SmartMedia */
  61         at91_sys_write(AT91_SMC_SETUP(3),
  62                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  63                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  64         at91_sys_write(AT91_SMC_PULSE(3),
  65                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  66                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  67         at91_sys_write(AT91_SMC_CYCLE(3),
  68                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  69         at91_sys_write(AT91_SMC_MODE(3),
  70                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  71                        AT91_SMC_EXNWMODE_DISABLE |
  72 #ifdef CONFIG_SYS_NAND_DBW_16
  73                        AT91_SMC_DBW_16 |
  74 #else /* CONFIG_SYS_NAND_DBW_8 */
  75                        AT91_SMC_DBW_8 |
  76 #endif
  77                        AT91_SMC_TDF_(2));
  78
  79         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
  80
  81         /* Configure RDY/BSY */
  82         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  83
  84         /* Enable NandFlash */
  85         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  86 }
  87 #endif
  88
  89 #ifdef CONFIG_MACB
  90 static void sbc35_a9g20_macb_hw_init(void)
  91 {
  92         unsigned long rstc;
  93
  94         /* Enable clock */
  95         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
  96
  97         /*
  98          * Disable pull-up on:
  99          *      RXDV (PA17) => PHY normal mode (not Test mode)
 100          *      ERX0 (PA14) => PHY ADDR0
 101          *      ERX1 (PA15) => PHY ADDR1
 102          *      ERX2 (PA25) => PHY ADDR2
 103          *      ERX3 (PA26) => PHY ADDR3
 104          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
 105          *
 106          * PHY has internal pull-down
 107          */
 108         writel(pin_to_mask(AT91_PIN_PA14) |
 109                pin_to_mask(AT91_PIN_PA15) |
 110                pin_to_mask(AT91_PIN_PA17) |
 111                pin_to_mask(AT91_PIN_PA25) |
 112                pin_to_mask(AT91_PIN_PA26) |
 113                pin_to_mask(AT91_PIN_PA28),
 114                pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 115
 116         rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
 117
 118         /* Need to reset PHY -> 500ms reset */
 119         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 120                                      (AT91_RSTC_ERSTL & (0x0D << 8)) |
 121                                      AT91_RSTC_URSTEN);
 122
 123         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 124
 125         /* Wait for end hardware reset */
 126         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL));
 127
 128         /* Restore NRST value */
 129         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 130                                      (rstc) |
 131                                      AT91_RSTC_URSTEN);
 132
 133         /* Re-enable pull-up */
 134         writel(pin_to_mask(AT91_PIN_PA14) |
 135                pin_to_mask(AT91_PIN_PA15) |
 136                pin_to_mask(AT91_PIN_PA17) |
 137                pin_to_mask(AT91_PIN_PA25) |
 138                pin_to_mask(AT91_PIN_PA26) |
 139                pin_to_mask(AT91_PIN_PA28),
 140                pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 141
 142         at91_macb_hw_init();
 143 }
 144 #endif
 145
 146 int board_init(void)
 147 {
 148         /* Enable Ctrlc */
 149         console_init_f();
 150
 151         gd->bd->bi_arch_number = MACH_TYPE_SBC35_A9G20;
 152         /* adress of boot parameters */
 153         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 154
 155         at91_serial_hw_init();
 156         sbc35_a9g20_nand_hw_init();
 157 #ifdef CONFIG_ATMEL_SPI
 158         at91_spi0_hw_init(1 << 4 | 1 << 5);
 159 #endif
 160 #ifdef CONFIG_MACB
 161         sbc35_a9g20_macb_hw_init();
 162 #endif
 163
 164         return 0;
 165 }
 166
 167 int dram_init(void)
 168 {
 169         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 170         if(get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) != PHYS_SDRAM_SIZE)
 171                 return -1;
 172
 173         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 174         return 0;
 175 }
 176
 177 #ifdef CONFIG_RESET_PHY_R
 178 void reset_phy(void)
 179 {
 180 #ifdef CONFIG_MACB
 181         /*
 182          * Initialize ethernet HW addr prior to starting Linux,
 183          * needed for nfsroot
 184          */
 185         eth_init(gd->bd);
 186 #endif
 187 }
 188 #endif
 189
 190 int board_eth_init(bd_t *bis)
 191 {
 192         int rc = 0;
 193 #ifdef CONFIG_MACB
 194         rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
 195 #endif
 196         return rc;
 197 }