board/cloudengines/pogo_e02/pogo_e02.c

   1 /*
   2  * Copyright (C) 2012
   3  * David Purdy <david.c.purdy@gmail.com>
   4  *
   5  * Based on Kirkwood support:
   6  * (C) Copyright 2009
   7  * Marvell Semiconductor <www.marvell.com>
   8  * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <miiphy.h>
  15 #include <asm/arch/cpu.h>
  16 #include <asm/arch/soc.h>
  17 #include <asm/arch/mpp.h>
  18 #include "pogo_e02.h"
  19
  20 DECLARE_GLOBAL_DATA_PTR;
  21
  22 int board_early_init_f(void)
  23 {
  24         /*
  25          * default gpio configuration
  26          * There are maximum 64 gpios controlled through 2 sets of registers
  27          * the  below configuration configures mainly initial LED status
  28          */
  29         mvebu_config_gpio(POGO_E02_OE_VAL_LOW,
  30                           POGO_E02_OE_VAL_HIGH,
  31                           POGO_E02_OE_LOW, POGO_E02_OE_HIGH);
  32
  33         /* Multi-Purpose Pins Functionality configuration */
  34         static const u32 kwmpp_config[] = {
  35                 MPP0_NF_IO2,
  36                 MPP1_NF_IO3,
  37                 MPP2_NF_IO4,
  38                 MPP3_NF_IO5,
  39                 MPP4_NF_IO6,
  40                 MPP5_NF_IO7,
  41                 MPP6_SYSRST_OUTn,
  42                 MPP7_GPO,
  43                 MPP8_UART0_RTS,
  44                 MPP9_UART0_CTS,
  45                 MPP10_UART0_TXD,
  46                 MPP11_UART0_RXD,
  47                 MPP12_SD_CLK,
  48                 MPP13_SD_CMD,
  49                 MPP14_SD_D0,
  50                 MPP15_SD_D1,
  51                 MPP16_SD_D2,
  52                 MPP17_SD_D3,
  53                 MPP18_NF_IO0,
  54                 MPP19_NF_IO1,
  55                 MPP29_TSMP9,    /* USB Power Enable */
  56                 MPP48_GPIO,     /* LED green */
  57                 MPP49_GPIO,     /* LED orange */
  58                 0
  59         };
  60         kirkwood_mpp_conf(kwmpp_config, NULL);
  61         return 0;
  62 }
  63
  64 int board_init(void)
  65 {
  66         /* Boot parameters address */
  67         gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
  68
  69         return 0;
  70 }
  71
  72 #ifdef CONFIG_RESET_PHY_R
  73 /* Configure and initialize PHY */
  74 void reset_phy(void)
  75 {
  76         u16 reg;
  77         u16 devadr;
  78         char *name = "egiga0";
  79
  80         if (miiphy_set_current_dev(name))
  81                 return;
  82
  83         /* command to read PHY dev address */
  84         if (miiphy_read(name, 0xEE, 0xEE, (u16 *) &devadr)) {
  85                 printf("Err..(%s) could not read PHY dev address\n", __func__);
  86                 return;
  87         }
  88
  89         /*
  90          * Enable RGMII delay on Tx and Rx for CPU port
  91          * Ref: sec 4.7.2 of chip datasheet
  92          */
  93         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
  94         miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
  95         reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
  96         miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
  97         miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
  98
  99         /* reset the phy */
 100         miiphy_reset(name, devadr);
 101
 102         debug("88E1116 Initialized on %s\n", name);
 103 }
 104 #endif /* CONFIG_RESET_PHY_R */