board/eNET/eNET.c

   1 /*
   2  * (C) Copyright 2008
   3  * Graeme Russ, graeme.russ@gmail.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/ic/sc520.h>
  27 #include <net.h>
  28 #include <netdev.h>
  29
  30 #ifdef CONFIG_HW_WATCHDOG
  31 #include <watchdog.h>
  32 #endif
  33
  34 #include "hardware.h"
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 static void enet_timer_isr(void);
  39 static void enet_toggle_run_led(void);
  40 static void enet_setup_pars(void);
  41
  42 /*
  43  * Miscellaneous platform dependent initializations
  44  */
  45 int board_early_init_f(void)
  46 {
  47         u16 pio_out_cfg = 0x0000;
  48
  49         /* Configure General Purpose Bus timing */
  50         writeb(CONFIG_SYS_SC520_GPCSRT, &sc520_mmcr->gpcsrt);
  51         writeb(CONFIG_SYS_SC520_GPCSPW, &sc520_mmcr->gpcspw);
  52         writeb(CONFIG_SYS_SC520_GPCSOFF, &sc520_mmcr->gpcsoff);
  53         writeb(CONFIG_SYS_SC520_GPRDW, &sc520_mmcr->gprdw);
  54         writeb(CONFIG_SYS_SC520_GPRDOFF, &sc520_mmcr->gprdoff);
  55         writeb(CONFIG_SYS_SC520_GPWRW, &sc520_mmcr->gpwrw);
  56         writeb(CONFIG_SYS_SC520_GPWROFF, &sc520_mmcr->gpwroff);
  57
  58         /* Configure Programmable Input/Output Pins */
  59         writew(CONFIG_SYS_SC520_PIODIR15_0, &sc520_mmcr->piodir15_0);
  60         writew(CONFIG_SYS_SC520_PIODIR31_16, &sc520_mmcr->piodir31_16);
  61         writew(CONFIG_SYS_SC520_PIOPFS31_16, &sc520_mmcr->piopfs31_16);
  62         writew(CONFIG_SYS_SC520_PIOPFS15_0, &sc520_mmcr->piopfs15_0);
  63         writeb(CONFIG_SYS_SC520_CSPFS, &sc520_mmcr->cspfs);
  64         writeb(CONFIG_SYS_SC520_CLKSEL, &sc520_mmcr->clksel);
  65
  66         /*
  67          * Turn off top board
  68          * Set StrataFlash chips to 16-bit width
  69          * Set StrataFlash chips to normal (non reset/power down) mode
  70          */
  71         pio_out_cfg |= CONFIG_SYS_ENET_TOP_BRD_PWR;
  72         pio_out_cfg |= CONFIG_SYS_ENET_SF_WIDTH;
  73         pio_out_cfg |= CONFIG_SYS_ENET_SF1_MODE;
  74         pio_out_cfg |= CONFIG_SYS_ENET_SF2_MODE;
  75         writew(pio_out_cfg, &sc520_mmcr->pioset15_0);
  76
  77         /* Turn off auxiliary power output */
  78         writew(CONFIG_SYS_ENET_AUX_PWR, &sc520_mmcr->pioclr15_0);
  79
  80         /* Clear FPGA program mode */
  81         writew(CONFIG_SYS_ENET_FPGA_PROG, &sc520_mmcr->pioset31_16);
  82
  83         enet_setup_pars();
  84
  85         /* Disable Watchdog */
  86         writew(0x3333, &sc520_mmcr->wdtmrctl);
  87         writew(0xcccc, &sc520_mmcr->wdtmrctl);
  88         writew(0x0000, &sc520_mmcr->wdtmrctl);
  89
  90         /* Chip Select Configuration */
  91         writew(CONFIG_SYS_SC520_BOOTCS_CTRL, &sc520_mmcr->bootcsctl);
  92         writew(CONFIG_SYS_SC520_ROMCS1_CTRL, &sc520_mmcr->romcs1ctl);
  93         writew(CONFIG_SYS_SC520_ROMCS2_CTRL, &sc520_mmcr->romcs2ctl);
  94
  95         writeb(CONFIG_SYS_SC520_ADDDECCTL, &sc520_mmcr->adddecctl);
  96         writeb(CONFIG_SYS_SC520_UART1CTL, &sc520_mmcr->uart1ctl);
  97         writeb(CONFIG_SYS_SC520_UART2CTL, &sc520_mmcr->uart2ctl);
  98
  99         writeb(CONFIG_SYS_SC520_SYSARBCTL, &sc520_mmcr->sysarbctl);
 100         writew(CONFIG_SYS_SC520_SYSARBMENB, &sc520_mmcr->sysarbmenb);
 101
 102         /* enable posted-writes */
 103         writeb(CONFIG_SYS_SC520_HBCTL, &sc520_mmcr->hbctl);
 104
 105         return 0;
 106 }
 107
 108 static void enet_setup_pars(void)
 109 {
 110         /*
 111          * PARs 11 and 12 are 2MB SRAM @ 0x19000000
 112          *
 113          * These are setup now because older version of U-Boot have them
 114          * mapped to a different PAR which gets clobbered which prevents
 115          * using SRAM for warm-booting a new image
 116          */
 117         writel(CONFIG_SYS_SC520_SRAM1_PAR, &sc520_mmcr->par[11]);
 118         writel(CONFIG_SYS_SC520_SRAM2_PAR, &sc520_mmcr->par[12]);
 119
 120         /* PARs 0 and 1 are Compact Flash slots (4kB each) */
 121         writel(CONFIG_SYS_SC520_CF1_PAR, &sc520_mmcr->par[0]);
 122         writel(CONFIG_SYS_SC520_CF2_PAR, &sc520_mmcr->par[1]);
 123
 124         /* PAR 2 is used for Cache-As-RAM */
 125
 126         /*
 127          * PARs 5 through 8 are additional NS16550 UARTS
 128          * 8 bytes each @ 0x013f8, 0x012f8, 0x011f8 and 0x010f8
 129          */
 130         writel(CONFIG_SYS_SC520_UARTA_PAR, &sc520_mmcr->par[5]);
 131         writel(CONFIG_SYS_SC520_UARTB_PAR, &sc520_mmcr->par[6]);
 132         writel(CONFIG_SYS_SC520_UARTC_PAR, &sc520_mmcr->par[7]);
 133         writel(CONFIG_SYS_SC520_UARTD_PAR, &sc520_mmcr->par[8]);
 134
 135         /* PARs 9 and 10 are 32MB StrataFlash @ 0x10000000 */
 136         writel(CONFIG_SYS_SC520_SF1_PAR, &sc520_mmcr->par[9]);
 137         writel(CONFIG_SYS_SC520_SF2_PAR, &sc520_mmcr->par[10]);
 138
 139         /* PAR 13 is 4kB DPRAM @ 0x18100000 (implemented in FPGA) */
 140         writel(CONFIG_SYS_SC520_DPRAM_PAR, &sc520_mmcr->par[13]);
 141
 142         /*
 143          * PAR 14 is Low Level I/O (LEDs, Hex Switches etc)
 144          * Already configured in board_init16 (eNET_start16.S)
 145          *
 146          * PAR 15 is Boot ROM
 147          * Already configured in board_init16 (eNET_start16.S)
 148          */
 149 }
 150
 151
 152 int board_early_init_r(void)
 153 {
 154         /* CPU Speed to 100MHz */
 155         gd->cpu_clk = 100000000;
 156
 157         /* Crystal is 33.000MHz */
 158         gd->bus_clk = 33000000;
 159
 160         return 0;
 161 }
 162
 163 void show_boot_progress(int val)
 164 {
 165         uchar led_mask;
 166
 167         led_mask = 0x00;
 168
 169         if (val < 0)
 170                 led_mask |= LED_ERR_BITMASK;
 171
 172         led_mask |= (uchar)(val & 0x001f);
 173         outb(led_mask, LED_LATCH_ADDRESS);
 174 }
 175
 176
 177 int last_stage_init(void)
 178 {
 179         int minor;
 180         int major;
 181
 182         major = minor = 0;
 183
 184         outb(0x00, LED_LATCH_ADDRESS);
 185
 186         register_timer_isr(enet_timer_isr);
 187
 188         printf("Serck Controls eNET\n");
 189
 190         return 0;
 191 }
 192
 193 ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
 194 {
 195         if (banknum == 0) {     /* non-CFI boot flash */
 196                 info->portwidth = FLASH_CFI_8BIT;
 197                 info->chipwidth = FLASH_CFI_BY8;
 198                 info->interface = FLASH_CFI_X8;
 199                 return 1;
 200         } else {
 201                 return 0;
 202         }
 203 }
 204
 205 int board_eth_init(bd_t *bis)
 206 {
 207         return pci_eth_init(bis);
 208 }
 209
 210 void setup_pcat_compatibility()
 211 {
 212         /* disable global interrupt mode */
 213         writeb(0x40, &sc520_mmcr->picicr);
 214
 215         /* set all irqs to edge */
 216         writeb(0x00, &sc520_mmcr->pic_mode[0]);
 217         writeb(0x00, &sc520_mmcr->pic_mode[1]);
 218         writeb(0x00, &sc520_mmcr->pic_mode[2]);
 219
 220         /*
 221          *  active low polarity on PIC interrupt pins,
 222          *  active high polarity on all other irq pins
 223          */
 224         writew(0x0000,&sc520_mmcr->intpinpol);
 225
 226         /*
 227          * PIT 0 -> IRQ0
 228          * RTC -> IRQ8
 229          * FP error -> IRQ13
 230          * UART1 -> IRQ4
 231          * UART2 -> IRQ3
 232          */
 233         writeb(SC520_IRQ0, &sc520_mmcr->pit_int_map[0]);
 234         writeb(SC520_IRQ8, &sc520_mmcr->rtcmap);
 235         writeb(SC520_IRQ13, &sc520_mmcr->ferrmap);
 236         writeb(SC520_IRQ4, &sc520_mmcr->uart_int_map[0]);
 237         writeb(SC520_IRQ3, &sc520_mmcr->uart_int_map[1]);
 238
 239         /* Disable all other interrupt sources */
 240         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[0]);
 241         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[1]);
 242         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->gp_tmr_int_map[2]);
 243         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[1]);
 244         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->pit_int_map[2]);
 245         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->ssimap);
 246         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wdtmap);
 247         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->wpvmap);
 248         writeb(SC520_IRQ_DISABLED, &sc520_mmcr->icemap);
 249 }
 250
 251 void enet_timer_isr(void)
 252 {
 253         static long enet_ticks = 0;
 254
 255         enet_ticks++;
 256
 257         /* Toggle Watchdog every 100ms */
 258         if ((enet_ticks % 100) == 0)
 259                 hw_watchdog_reset();
 260
 261         /* Toggle Run LED every 500ms */
 262         if ((enet_ticks % 500) == 0)
 263                 enet_toggle_run_led();
 264 }
 265
 266 void hw_watchdog_reset(void)
 267 {
 268         /* Watchdog Reset must be atomic */
 269         long flag = disable_interrupts();
 270
 271         if (sc520_mmcr->piodata15_0 & WATCHDOG_PIO_BIT)
 272                 sc520_mmcr->pioclr15_0 = WATCHDOG_PIO_BIT;
 273         else
 274                 sc520_mmcr->pioset15_0 = WATCHDOG_PIO_BIT;
 275
 276         if (flag)
 277                 enable_interrupts();
 278 }
 279
 280 void enet_toggle_run_led(void)
 281 {
 282         unsigned char leds_state= inb(LED_LATCH_ADDRESS);
 283         if (leds_state & LED_RUN_BITMASK)
 284                 outb(leds_state &~ LED_RUN_BITMASK, LED_LATCH_ADDRESS);
 285         else
 286                 outb(leds_state | LED_RUN_BITMASK, LED_LATCH_ADDRESS);
 287 }