board/eNET/eNET.c

   1 /*
   2  * (C) Copyright 2008
   3  * Graeme Russ, graeme.russ@gmail.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/ic/sc520.h>
  27
  28 #ifdef CONFIG_HW_WATCHDOG
  29 #include <watchdog.h>
  30 #endif
  31
  32 #include "hardware.h"
  33
  34 DECLARE_GLOBAL_DATA_PTR;
  35
  36 #undef SC520_CDP_DEBUG
  37
  38 #ifdef  SC520_CDP_DEBUG
  39 #define PRINTF(fmt,args...)     printf (fmt ,##args)
  40 #else
  41 #define PRINTF(fmt,args...)
  42 #endif
  43
  44 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
  45
  46 void init_sc520_enet (void)
  47 {
  48         /* Set CPU Speed to 100MHz */
  49         writeb(0x01, &sc520_mmcr->cpuctl);
  50
  51         /* wait at least one millisecond */
  52         asm("movl       $0x2000,%%ecx\n"
  53             "0: pushl %%ecx\n"
  54             "popl       %%ecx\n"
  55             "loop 0b\n": : : "ecx");
  56
  57         /* turn on the SDRAM write buffer */
  58         writeb(0x11, &sc520_mmcr->dbctl);
  59
  60         /* turn on the cache and disable write through */
  61         asm("movl       %%cr0, %%eax\n"
  62             "andl       $0x9fffffff, %%eax\n"
  63             "movl       %%eax, %%cr0\n"  : : : "eax");
  64 }
  65
  66 /*
  67  * Miscellaneous platform dependent initializations
  68  */
  69 int board_early_init_f(void)
  70 {
  71         init_sc520_enet();
  72
  73         writeb(0x01, &sc520_mmcr->gpcsrt);              /* GP Chip Select Recovery Time */
  74         writeb(0x07, &sc520_mmcr->gpcspw);              /* GP Chip Select Pulse Width */
  75         writeb(0x00, &sc520_mmcr->gpcsoff);             /* GP Chip Select Offset */
  76         writeb(0x05, &sc520_mmcr->gprdw);               /* GP Read pulse width */
  77         writeb(0x01, &sc520_mmcr->gprdoff);             /* GP Read offset */
  78         writeb(0x05, &sc520_mmcr->gpwrw);               /* GP Write pulse width */
  79         writeb(0x01, &sc520_mmcr->gpwroff);             /* GP Write offset */
  80
  81         writew(0x0630, &sc520_mmcr->piodata15_0);       /* PIO15_PIO0 Data */
  82         writew(0x2000, &sc520_mmcr->piodata31_16);      /* PIO31_PIO16 Data */
  83         writew(0x2000, &sc520_mmcr->piodir31_16);       /* GPIO Direction */
  84         writew(0x87b5, &sc520_mmcr->piodir15_0);        /* GPIO Direction */
  85         writew(0x0dfe, &sc520_mmcr->piopfs31_16);       /* GPIO pin function 31-16 reg */
  86         writew(0x200a, &sc520_mmcr->piopfs15_0);        /* GPIO pin function 15-0 reg */
  87         writeb(0xf8, &sc520_mmcr->cspfs);               /* Chip Select Pin Function Select */
  88
  89         writel(0x200713f8, &sc520_mmcr->par[2]);        /* Uart A (GPCS0, 0x013f8, 8 Bytes) */
  90         writel(0x2c0712f8, &sc520_mmcr->par[3]);        /* Uart B (GPCS3, 0x012f8, 8 Bytes) */
  91         writel(0x300711f8, &sc520_mmcr->par[4]);        /* Uart C (GPCS4, 0x011f8, 8 Bytes) */
  92         writel(0x340710f8, &sc520_mmcr->par[5]);        /* Uart D (GPCS5, 0x010f8, 8 Bytes) */
  93         writel(0xe3ffc000, &sc520_mmcr->par[6]);        /* SDRAM (0x00000000, 128MB) */
  94         writel(0xaa3fd000, &sc520_mmcr->par[7]);        /* StrataFlash (ROMCS1, 0x10000000, 16MB) */
  95         writel(0xca3fd100, &sc520_mmcr->par[8]);        /* StrataFlash (ROMCS2, 0x11000000, 16MB) */
  96         writel(0x4203d900, &sc520_mmcr->par[9]);        /* SRAM (GPCS0, 0x19000000, 1MB) */
  97         writel(0x4e03d910, &sc520_mmcr->par[10]);       /* SRAM (GPCS3, 0x19100000, 1MB) */
  98         writel(0x50018100, &sc520_mmcr->par[11]);       /* DP-RAM (GPCS4, 0x18100000, 4kB) */
  99         writel(0x54020000, &sc520_mmcr->par[12]);       /* CFLASH1 (0x200000000, 4kB) */
 100         writel(0x5c020001, &sc520_mmcr->par[13]);       /* CFLASH2 (0x200010000, 4kB) */
 101 /*      writel(0x8bfff800, &sc520_mmcr->par14); */      /* BOOTCS at  0x18000000 */
 102 /*      writel(0x38201000, &sc520_mmcr->par15); */      /* LEDs etc (GPCS6, 0x1000, 20 Bytes */
 103
 104         /* Disable Watchdog */
 105         writew(0x3333, &sc520_mmcr->wdtmrctl);
 106         writew(0xcccc, &sc520_mmcr->wdtmrctl);
 107         writew(0x0000, &sc520_mmcr->wdtmrctl);
 108
 109         /* Chip Select Configuration */
 110         writew(0x0033, &sc520_mmcr->bootcsctl);
 111         writew(0x0615, &sc520_mmcr->romcs1ctl);
 112         writew(0x0615, &sc520_mmcr->romcs2ctl);
 113
 114         writeb(0x00, &sc520_mmcr->adddecctl);
 115         writeb(0x07, &sc520_mmcr->uart1ctl);
 116         writeb(0x07, &sc520_mmcr->uart2ctl);
 117         writeb(0x06, &sc520_mmcr->sysarbctl);
 118         writew(0x0003, &sc520_mmcr->sysarbmenb);
 119
 120         return 0;
 121 }
 122
 123 int board_early_init_r(void)
 124 {
 125         /* CPU Speed to 100MHz */
 126         gd->cpu_clk = 100000000;
 127
 128         /* Crystal is 33.000MHz */
 129         gd->bus_clk = 33000000;
 130
 131         return 0;
 132 }
 133
 134 int dram_init(void)
 135 {
 136         init_sc520_dram();
 137         return 0;
 138 }
 139
 140 void show_boot_progress(int val)
 141 {
 142         uchar led_mask;
 143
 144         led_mask = 0x00;
 145
 146         if (val < 0)
 147                 led_mask |= LED_ERR_BITMASK;
 148
 149         led_mask |= (uchar)(val & 0x001f);
 150         outb(led_mask, LED_LATCH_ADDRESS);
 151 }
 152
 153
 154 int last_stage_init(void)
 155 {
 156         int minor;
 157         int major;
 158
 159         major = minor = 0;
 160
 161         printf("Serck Controls eNET\n");
 162
 163         return 0;
 164 }
 165
 166 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 167 {
 168         if (banknum == 0) {     /* non-CFI boot flash */
 169                 info->portwidth = FLASH_CFI_8BIT;
 170                 info->chipwidth = FLASH_CFI_BY8;
 171                 info->interface = FLASH_CFI_X8;
 172                 return 1;
 173         } else
 174                 return 0;
 175 }