board/efikamx/efikamx.c

   1 /*
   2  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
   3  *
   4  * (C) Copyright 2009 Freescale Semiconductor, Inc.
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #include <common.h>
  26 #include <asm/io.h>
  27 #include <asm/arch/imx-regs.h>
  28 #include <asm/arch/mx5x_pins.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/gpio.h>
  31 #include <asm/errno.h>
  32 #include <asm/arch/sys_proto.h>
  33 #include <asm/arch/crm_regs.h>
  34 #include <i2c.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <pmic.h>
  38 #include <fsl_pmic.h>
  39 #include <mc13892.h>
  40
  41 DECLARE_GLOBAL_DATA_PTR;
  42
  43 /*
  44  * Compile-time error checking
  45  */
  46 #ifndef CONFIG_MXC_SPI
  47 #error "CONFIG_MXC_SPI not set, this is essential for board's operation!"
  48 #endif
  49
  50 /*
  51  * Shared variables / local defines
  52  */
  53 /* LED */
  54 #define EFIKAMX_LED_BLUE        0x1
  55 #define EFIKAMX_LED_GREEN       0x2
  56 #define EFIKAMX_LED_RED         0x4
  57
  58 void efikamx_toggle_led(uint32_t mask);
  59
  60 /* Board revisions */
  61 #define EFIKAMX_BOARD_REV_11    0x1
  62 #define EFIKAMX_BOARD_REV_12    0x2
  63 #define EFIKAMX_BOARD_REV_13    0x3
  64 #define EFIKAMX_BOARD_REV_14    0x4
  65
  66 #define EFIKASB_BOARD_REV_13    0x1
  67 #define EFIKASB_BOARD_REV_20    0x2
  68
  69 /*
  70  * Board identification
  71  */
  72 u32 get_efikamx_rev(void)
  73 {
  74         u32 rev = 0;
  75         /*
  76          * Retrieve board ID:
  77          *      rev1.1: 1,1,1
  78          *      rev1.2: 1,1,0
  79          *      rev1.3: 1,0,1
  80          *      rev1.4: 1,0,0
  81          */
  82         mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
  83         /* set to 1 in order to get correct value on board rev1.1 */
  84         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
  85
  86         mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
  87         mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
  88         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
  89         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
  90
  91         mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
  92         mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
  93         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
  94         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
  95
  96         mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
  97         mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
  98         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
  99         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
 100
 101         return (~rev & 0x7) + 1;
 102 }
 103
 104 inline u32 get_efikasb_rev(void)
 105 {
 106         u32 rev = 0;
 107
 108         mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO);
 109         mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU);
 110         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3));
 111         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0;
 112
 113         mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO);
 114         mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU);
 115         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4));
 116         rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1;
 117
 118         return rev;
 119 }
 120
 121 inline uint32_t get_efika_rev(void)
 122 {
 123         if (machine_is_efikamx())
 124                 return get_efikamx_rev();
 125         else
 126                 return get_efikasb_rev();
 127 }
 128
 129 u32 get_board_rev(void)
 130 {
 131         return get_cpu_rev() | (get_efika_rev() << 8);
 132 }
 133
 134 /*
 135  * DRAM initialization
 136  */
 137 int dram_init(void)
 138 {
 139         /* dram_init must store complete ramsize in gd->ram_size */
 140         gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
 141                                 PHYS_SDRAM_1_SIZE);
 142         return 0;
 143 }
 144
 145 /*
 146  * UART configuration
 147  */
 148 static void setup_iomux_uart(void)
 149 {
 150         unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
 151                         PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;
 152
 153         mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
 154         mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
 155         mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
 156         mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
 157         mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
 158         mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
 159         mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
 160         mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
 161 }
 162
 163 /*
 164  * SPI configuration
 165  */
 166 #ifdef CONFIG_MXC_SPI
 167 static void setup_iomux_spi(void)
 168 {
 169         /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
 170         mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
 171         mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
 172                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 173
 174         /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
 175         mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
 176         mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
 177                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 178
 179         /* Configure SS0 as a GPIO */
 180         mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
 181         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
 182
 183         /* Configure SS1 as a GPIO */
 184         mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
 185         gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
 186
 187         /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
 188         mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
 189         mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
 190                 PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 191
 192         /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
 193         mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
 194         mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
 195                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 196 }
 197 #else
 198 static inline void setup_iomux_spi(void) { }
 199 #endif
 200
 201 /*
 202  * PMIC configuration
 203  */
 204 #ifdef CONFIG_MXC_SPI
 205 static void power_init(void)
 206 {
 207         unsigned int val;
 208         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
 209         struct pmic *p;
 210
 211         pmic_init();
 212         p = get_pmic();
 213
 214         /* Write needed to Power Gate 2 register */
 215         pmic_reg_read(p, REG_POWER_MISC, &val);
 216         val &= ~PWGT2SPIEN;
 217         pmic_reg_write(p, REG_POWER_MISC, val);
 218
 219         /* Externally powered */
 220         pmic_reg_read(p, REG_CHARGE, &val);
 221         val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB;
 222         pmic_reg_write(p, REG_CHARGE, val);
 223
 224         /* power up the system first */
 225         pmic_reg_write(p, REG_POWER_MISC, PWUP);
 226
 227         /* Set core voltage to 1.1V */
 228         pmic_reg_read(p, REG_SW_0, &val);
 229         val = (val & ~SWx_VOLT_MASK) | SWx_1_200V;
 230         pmic_reg_write(p, REG_SW_0, val);
 231
 232         /* Setup VCC (SW2) to 1.25 */
 233         pmic_reg_read(p, REG_SW_1, &val);
 234         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 235         pmic_reg_write(p, REG_SW_1, val);
 236
 237         /* Setup 1V2_DIG1 (SW3) to 1.25 */
 238         pmic_reg_read(p, REG_SW_2, &val);
 239         val = (val & ~SWx_VOLT_MASK) | SWx_1_250V;
 240         pmic_reg_write(p, REG_SW_2, val);
 241         udelay(50);
 242
 243         /* Raise the core frequency to 800MHz */
 244         writel(0x0, &mxc_ccm->cacrr);
 245
 246         /* Set switchers in Auto in NORMAL mode & STANDBY mode */
 247         /* Setup the switcher mode for SW1 & SW2*/
 248         pmic_reg_read(p, REG_SW_4, &val);
 249         val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) |
 250                 (SWMODE_MASK << SWMODE2_SHIFT)));
 251         val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) |
 252                 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT);
 253         pmic_reg_write(p, REG_SW_4, val);
 254
 255         /* Setup the switcher mode for SW3 & SW4 */
 256         pmic_reg_read(p, REG_SW_5, &val);
 257         val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) |
 258                 (SWMODE_MASK << SWMODE4_SHIFT)));
 259         val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) |
 260                 (SWMODE_AUTO_AUTO << SWMODE4_SHIFT);
 261         pmic_reg_write(p, REG_SW_5, val);
 262
 263         /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */
 264         pmic_reg_read(p, REG_SETTING_0, &val);
 265         val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK);
 266         val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6;
 267         pmic_reg_write(p, REG_SETTING_0, val);
 268
 269         /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */
 270         pmic_reg_read(p, REG_SETTING_1, &val);
 271         val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK);
 272         val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15;
 273         pmic_reg_write(p, REG_SETTING_1, val);
 274
 275         /* Enable VGEN1, VGEN2, VDIG, VPLL */
 276         pmic_reg_read(p, REG_MODE_0, &val);
 277         val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN;
 278         pmic_reg_write(p, REG_MODE_0, val);
 279
 280         /* Configure VGEN3 and VCAM regulators to use external PNP */
 281         val = VGEN3CONFIG | VCAMCONFIG;
 282         pmic_reg_write(p, REG_MODE_1, val);
 283         udelay(200);
 284
 285         /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */
 286         val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG |
 287                 VVIDEOEN | VAUDIOEN | VSDEN;
 288         pmic_reg_write(p, REG_MODE_1, val);
 289
 290         pmic_reg_read(p, REG_POWER_CTL2, &val);
 291         val |= WDIRESET;
 292         pmic_reg_write(p, REG_POWER_CTL2, val);
 293
 294         udelay(2500);
 295 }
 296 #else
 297 static inline void power_init(void) { }
 298 #endif
 299
 300 /*
 301  * MMC configuration
 302  */
 303 #ifdef CONFIG_FSL_ESDHC
 304 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 305         {MMC_SDHC1_BASE_ADDR, 1},
 306         {MMC_SDHC2_BASE_ADDR, 1},
 307 };
 308
 309 static inline uint32_t efika_mmc_cd(void)
 310 {
 311         if (machine_is_efikamx())
 312                 return MX51_PIN_GPIO1_0;
 313         else
 314                 return MX51_PIN_EIM_CS2;
 315 }
 316
 317 int board_mmc_getcd(struct mmc *mmc)
 318 {
 319         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 320         uint32_t cd = efika_mmc_cd();
 321         int ret;
 322
 323         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 324                 ret = !gpio_get_value(IOMUX_TO_GPIO(cd));
 325         else
 326                 ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
 327
 328         return ret;
 329 }
 330
 331 int board_mmc_init(bd_t *bis)
 332 {
 333         int ret;
 334         uint32_t cd = efika_mmc_cd();
 335
 336         /* SDHC1 is used on all revisions, setup control pins first */
 337         mxc_request_iomux(cd,
 338                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 339         mxc_iomux_set_pad(cd,
 340                 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 341                 PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
 342                 PAD_CTL_ODE_OPENDRAIN_NONE |
 343                 PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 344         mxc_request_iomux(MX51_PIN_GPIO1_1,
 345                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 346         mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
 347                 PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 348                 PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
 349                 PAD_CTL_SRE_FAST);
 350
 351         gpio_direction_input(IOMUX_TO_GPIO(cd));
 352         gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
 353
 354         /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
 355         if (machine_is_efikasb() || (machine_is_efikamx() &&
 356                 (get_efika_rev() < EFIKAMX_BOARD_REV_12))) {
 357                 /* SDHC1 IOMUX */
 358                 mxc_request_iomux(MX51_PIN_SD1_CMD,
 359                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 360                 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 361                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 362                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 363
 364                 mxc_request_iomux(MX51_PIN_SD1_CLK,
 365                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 366                 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 367                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 368                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 369
 370                 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
 371                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 372                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 373                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 374
 375                 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
 376                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 377                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 378                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 379
 380                 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
 381                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 382                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 383                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 384
 385                 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
 386                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 387                         PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |
 388                         PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);
 389
 390                 /* SDHC2 IOMUX */
 391                 mxc_request_iomux(MX51_PIN_SD2_CMD,
 392                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 393                 mxc_iomux_set_pad(MX51_PIN_SD2_CMD,
 394                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 395
 396                 mxc_request_iomux(MX51_PIN_SD2_CLK,
 397                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 398                 mxc_iomux_set_pad(MX51_PIN_SD2_CLK,
 399                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 400
 401                 mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);
 402                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,
 403                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 404
 405                 mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);
 406                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,
 407                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 408
 409                 mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);
 410                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,
 411                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 412
 413                 mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);
 414                 mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,
 415                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 416
 417                 /* SDHC2 Control lines IOMUX */
 418                 mxc_request_iomux(MX51_PIN_GPIO1_7,
 419                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 420                 mxc_iomux_set_pad(MX51_PIN_GPIO1_7,
 421                         PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 422                         PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |
 423                         PAD_CTL_ODE_OPENDRAIN_NONE |
 424                         PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);
 425                 mxc_request_iomux(MX51_PIN_GPIO1_8,
 426                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 427                 mxc_iomux_set_pad(MX51_PIN_GPIO1_8,
 428                         PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |
 429                         PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |
 430                         PAD_CTL_SRE_FAST);
 431
 432                 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
 433                 gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));
 434
 435                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 436                 if (!ret)
 437                         ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);
 438         } else {        /* New boards use only SDHC1 */
 439                 /* SDHC1 IOMUX */
 440                 mxc_request_iomux(MX51_PIN_SD1_CMD,
 441                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 442                 mxc_iomux_set_pad(MX51_PIN_SD1_CMD,
 443                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 444
 445                 mxc_request_iomux(MX51_PIN_SD1_CLK,
 446                         IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 447                 mxc_iomux_set_pad(MX51_PIN_SD1_CLK,
 448                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 449
 450                 mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);
 451                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,
 452                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 453
 454                 mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);
 455                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,
 456                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 457
 458                 mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);
 459                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,
 460                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 461
 462                 mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);
 463                 mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,
 464                         PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);
 465
 466                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
 467         }
 468
 469         return ret;
 470 }
 471 #endif
 472
 473 /*
 474  * ATA
 475  */
 476 #ifdef  CONFIG_MX51_PATA
 477 #define ATA_PAD_CONFIG  (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH)
 478 void setup_iomux_ata(void)
 479 {
 480         mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
 481         mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
 482         mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
 483         mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
 484         mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
 485         mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
 486         mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
 487         mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
 488         mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
 489         mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
 490         mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
 491         mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
 492         mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
 493         mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
 494         mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
 495         mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
 496         mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
 497         mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
 498         mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
 499         mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
 500         mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
 501         mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
 502         mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
 503         mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
 504         mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
 505         mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
 506         mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
 507         mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
 508         mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
 509         mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
 510         mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
 511         mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
 512         mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
 513         mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
 514         mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
 515         mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
 516         mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
 517         mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
 518         mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
 519         mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
 520         mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
 521         mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
 522         mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
 523         mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
 524         mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
 525         mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
 526         mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
 527         mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
 528         mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
 529         mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
 530         mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
 531         mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
 532         mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
 533         mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
 534         mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
 535         mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
 536         mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
 537         mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
 538 }
 539 #else
 540 static inline void setup_iomux_ata(void) { }
 541 #endif
 542
 543 /*
 544  * EHCI USB
 545  */
 546 #ifdef  CONFIG_CMD_USB
 547 extern void setup_iomux_usb(void);
 548 #else
 549 static inline void setup_iomux_usb(void) { }
 550 #endif
 551
 552 /*
 553  * LED configuration
 554  */
 555 void setup_iomux_led(void)
 556 {
 557         if (machine_is_efikamx()) {
 558                 /* Blue LED */
 559                 mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);
 560                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);
 561
 562                 /* Green LED */
 563                 mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);
 564                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);
 565
 566                 /* Red LED */
 567                 mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);
 568                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);
 569         } else {
 570                 /* CAPS-LOCK LED */
 571                 mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO);
 572                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0);
 573
 574                 /* ALARM-LED LED */
 575                 mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO);
 576                 gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);
 577         }
 578 }
 579
 580 void efikamx_toggle_led(uint32_t mask)
 581 {
 582         if (machine_is_efikamx()) {
 583                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),
 584                                 mask & EFIKAMX_LED_BLUE);
 585                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),
 586                                 mask & EFIKAMX_LED_GREEN);
 587                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),
 588                                 mask & EFIKAMX_LED_RED);
 589         } else {
 590                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0),
 591                                 mask & EFIKAMX_LED_BLUE);
 592                 gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3),
 593                                 !(mask & EFIKAMX_LED_GREEN));
 594         }
 595 }
 596
 597 /*
 598  * Board initialization
 599  */
 600 static void init_drive_strength(void)
 601 {
 602         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS);
 603         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE);
 604         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER);
 605         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU);
 606         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST);
 607         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH);
 608         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH);
 609         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS,
 610                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 611         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS,
 612                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 613         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE);
 614         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER);
 615         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE);
 616         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE);
 617         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE);
 618         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE);
 619         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST);
 620         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST);
 621         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST);
 622         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST);
 623         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU);
 624         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS);
 625         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM);
 626         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM);
 627         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM);
 628         mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM);
 629
 630         /* Setting pad options */
 631         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE,
 632                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 633                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 634         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0,
 635                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 636                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 637         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1,
 638                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 639                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 640         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK,
 641                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 642                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 643         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0,
 644                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 645                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 646         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1,
 647                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 648                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 649         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2,
 650                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 651                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 652         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3,
 653                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 654                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 655         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0,
 656                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 657                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 658         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1,
 659                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 660                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 661         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0,
 662                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 663                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 664         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1,
 665                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 666                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 667         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2,
 668                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 669                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 670         mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3,
 671                 PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER |
 672                 PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);
 673 }
 674
 675 int board_early_init_f(void)
 676 {
 677         init_drive_strength();
 678
 679         setup_iomux_uart();
 680         setup_iomux_spi();
 681         setup_iomux_led();
 682
 683         return 0;
 684 }
 685
 686 int board_init(void)
 687 {
 688         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 689
 690         return 0;
 691 }
 692
 693 int board_late_init(void)
 694 {
 695         setup_iomux_spi();
 696
 697         power_init();
 698
 699         setup_iomux_led();
 700         setup_iomux_ata();
 701         setup_iomux_usb();
 702
 703         if (machine_is_efikasb())
 704                 setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
 705
 706         setup_iomux_led();
 707
 708         efikamx_toggle_led(EFIKAMX_LED_BLUE);
 709
 710         return 0;
 711 }
 712
 713 int checkboard(void)
 714 {
 715         u32 rev = get_efika_rev();
 716
 717         if (machine_is_efikamx()) {
 718                 printf("Board: Efika MX, rev1.%i\n", rev & 0xf);
 719                 return 0;
 720         } else {
 721                 switch (rev) {
 722                 case EFIKASB_BOARD_REV_13:
 723                         printf("Board: Efika SB rev1.3\n");
 724                         break;
 725                 case EFIKASB_BOARD_REV_20:
 726                         printf("Board: Efika SB rev2.0\n");
 727                         break;
 728                 default:
 729                         printf("Board: Efika SB, rev Unknown\n");
 730                         break;
 731                 }
 732         }
 733
 734         return 0;
 735 }