board/esd/cpci750/cpci750.c

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  *
  23  * modifications for the DB64360 eval board based by Ingo.Assmus@keymile.com
  24  * modifications for the cpci750 by reinhard.arlt@esd-electronics.com
  25  */
  26
  27 /*
  28  * cpci750.c - main board support/init for the esd cpci750.
  29  */
  30
  31 #include <common.h>
  32 #include <command.h>
  33 #include <74xx_7xx.h>
  34 #include "../../Marvell/include/memory.h"
  35 #include "../../Marvell/include/pci.h"
  36 #include "../../Marvell/include/mv_gen_reg.h"
  37 #include <net.h>
  38
  39 #include "eth.h"
  40 #include "mpsc.h"
  41 #include "i2c.h"
  42 #include "64360.h"
  43 #include "mv_regs.h"
  44
  45 #undef  DEBUG
  46 /*#define       DEBUG */
  47
  48 #ifdef CONFIG_PCI
  49 #define MAP_PCI
  50 #endif /* of CONFIG_PCI */
  51
  52 #ifdef DEBUG
  53 #define DP(x) x
  54 #else
  55 #define DP(x)
  56 #endif
  57
  58 static char show_config_tab[][15] = {{"PCI0DLL_2     "},  /* 31 */
  59                                      {"PCI0DLL_1     "},  /* 30 */
  60                                      {"PCI0DLL_0     "},  /* 29 */
  61                                      {"PCI1DLL_2     "},  /* 28 */
  62                                      {"PCI1DLL_1     "},  /* 27 */
  63                                      {"PCI1DLL_0     "},  /* 26 */
  64                                      {"BbEP2En       "},  /* 25 */
  65                                      {"SDRAMRdDataDel"},  /* 24 */
  66                                      {"SDRAMRdDel    "},  /* 23 */
  67                                      {"SDRAMSync     "},  /* 22 */
  68                                      {"SDRAMPipeSel_1"},  /* 21 */
  69                                      {"SDRAMPipeSel_0"},  /* 20 */
  70                                      {"SDRAMAddDel   "},  /* 19 */
  71                                      {"SDRAMClkSel   "},  /* 18 */
  72                                      {"Reserved(1!)  "},  /* 17 */
  73                                      {"PCIRty        "},  /* 16 */
  74                                      {"BootCSWidth_1 "},  /* 15 */
  75                                      {"BootCSWidth_0 "},  /* 14 */
  76                                      {"PCI1PadsCal   "},  /* 13 */
  77                                      {"PCI0PadsCal   "},  /* 12 */
  78                                      {"MultiMVId_1   "},  /* 11 */
  79                                      {"MultiMVId_0   "},  /* 10 */
  80                                      {"MultiGTEn     "},  /* 09 */
  81                                      {"Int60xArb     "},  /* 08 */
  82                                      {"CPUBusConfig_1"},  /* 07 */
  83                                      {"CPUBusConfig_0"},  /* 06 */
  84                                      {"DefIntSpc     "},  /* 05 */
  85                                      {0               },  /* 04 */
  86                                      {"SROMAdd_1     "},  /* 03 */
  87                                      {"SROMAdd_0     "},  /* 02 */
  88                                      {"DRAMPadCal    "},  /* 01 */
  89                                      {"SInitEn       "},  /* 00 */
  90                                      {0               },  /* 31 */
  91                                      {0               },  /* 30 */
  92                                      {0               },  /* 29 */
  93                                      {0               },  /* 28 */
  94                                      {0               },  /* 27 */
  95                                      {0               },  /* 26 */
  96                                      {0               },  /* 25 */
  97                                      {0               },  /* 24 */
  98                                      {0               },  /* 23 */
  99                                      {0               },  /* 22 */
 100                                      {"JTAGCalBy     "},  /* 21 */
 101                                      {"GB2Sel        "},  /* 20 */
 102                                      {"GB1Sel        "},  /* 19 */
 103                                      {"DRAMPLL_MDiv_5"},  /* 18 */
 104                                      {"DRAMPLL_MDiv_4"},  /* 17 */
 105                                      {"DRAMPLL_MDiv_3"},  /* 16 */
 106                                      {"DRAMPLL_MDiv_2"},  /* 15 */
 107                                      {"DRAMPLL_MDiv_1"},  /* 14 */
 108                                      {"DRAMPLL_MDiv_0"},  /* 13 */
 109                                      {"GB0Sel        "},  /* 12 */
 110                                      {"DRAMPLLPU     "},  /* 11 */
 111                                      {"DRAMPLL_HIKVCO"},  /* 10 */
 112                                      {"DRAMPLLNP     "},  /* 09 */
 113                                      {"DRAMPLL_NDiv_7"},  /* 08 */
 114                                      {"DRAMPLL_NDiv_6"},  /* 07 */
 115                                      {"CPUPadCal     "},  /* 06 */
 116                                      {"DRAMPLL_NDiv_5"},  /* 05 */
 117                                      {"DRAMPLL_NDiv_4"},  /* 04 */
 118                                      {"DRAMPLL_NDiv_3"},  /* 03 */
 119                                      {"DRAMPLL_NDiv_2"},  /* 02 */
 120                                      {"DRAMPLL_NDiv_1"},  /* 01 */
 121                                      {"DRAMPLL_NDiv_0"}}; /* 00 */
 122
 123 extern flash_info_t flash_info[];
 124
 125 /* ------------------------------------------------------------------------- */
 126
 127 /* this is the current GT register space location */
 128 /* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 129
 130 /* Unfortunately, we cant change it while we are in flash, so we initialize it
 131  * to the "final" value. This means that any debug_led calls before
 132  * board_early_init_f wont work right (like in cpu_init_f).
 133  * See also my_remap_gt_regs below. (NTL)
 134  */
 135
 136 void board_prebootm_init (void);
 137 unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 138 int display_mem_map (void);
 139
 140 /* ------------------------------------------------------------------------- */
 141
 142 /*
 143  * This is a version of the GT register space remapping function that
 144  * doesn't touch globals (meaning, it's ok to run from flash.)
 145  *
 146  * Unfortunately, this has the side effect that a writable
 147  * INTERNAL_REG_BASE_ADDR is impossible. Oh well.
 148  */
 149
 150 void my_remap_gt_regs (u32 cur_loc, u32 new_loc)
 151 {
 152         u32 temp;
 153
 154         /* check and see if it's already moved */
 155
 156 /* original ppcboot 1.1.6 source
 157
 158         temp = in_le32((u32 *)(new_loc + INTERNAL_SPACE_DECODE));
 159         if ((temp & 0xffff) == new_loc >> 20)
 160                 return;
 161
 162         temp = (in_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE)) &
 163                 0xffff0000) | (new_loc >> 20);
 164
 165         out_le32((u32 *)(cur_loc + INTERNAL_SPACE_DECODE), temp);
 166
 167         while (GTREGREAD(INTERNAL_SPACE_DECODE) != temp);
 168 original ppcboot 1.1.6 source end */
 169
 170         temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
 171         if ((temp & 0xffff) == new_loc >> 16)
 172                 return;
 173
 174         temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
 175                 0xffff0000) | (new_loc >> 16);
 176
 177         out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
 178
 179         while (GTREGREAD (INTERNAL_SPACE_DECODE) != temp);
 180 }
 181
 182 #ifdef CONFIG_PCI
 183
 184 static void gt_pci_config (void)
 185 {
 186         unsigned int stat;
 187         unsigned int val = 0x00fff864;  /* DINK32: BusNum 23:16,  DevNum 15:11, FuncNum 10:8, RegNum 7:2 */
 188
 189         /* In PCIX mode devices provide their own bus and device numbers. We query the Discovery II's
 190          * config registers by writing ones to the bus and device.
 191          * We then update the Virtual register with the correct value for the bus and device.
 192          */
 193         if ((GTREGREAD (PCI_0_MODE) & (BIT4 | BIT5)) != 0) {    /*if  PCI-X */
 194                 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 195
 196                 GT_REG_READ (PCI_0_CONFIG_DATA_VIRTUAL_REG, &stat);
 197
 198                 GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 199                 GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
 200                               (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 201
 202         }
 203         if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {    /*if  PCI-X */
 204                 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 205                 GT_REG_READ (PCI_1_CONFIG_DATA_VIRTUAL_REG, &stat);
 206
 207                 GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 208                 GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
 209                               (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 210         }
 211
 212         /* Enable master */
 213         PCI_MASTER_ENABLE (0, SELF);
 214         PCI_MASTER_ENABLE (1, SELF);
 215
 216         /* Enable PCI0/1 Mem0 and IO 0 disable all others */
 217         GT_REG_READ (BASE_ADDR_ENABLE, &stat);
 218         stat |= (1 << 11) | (1 << 12) | (1 << 13) | (1 << 16) | (1 << 17) | (1
 219                                                                              <<
 220                                                                              18);
 221         stat &= ~((1 << 9) | (1 << 10) | (1 << 14) | (1 << 15));
 222         GT_REG_WRITE (BASE_ADDR_ENABLE, stat);
 223
 224         /* ronen- add write to pci remap registers for 64460.
 225            in 64360 when writing to pci base go and overide remap automaticaly,
 226            in 64460 it doesn't */
 227         GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
 228         GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
 229         GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 230
 231         GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
 232         GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
 233         GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 234
 235         GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
 236         GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
 237         GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 238
 239         GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
 240         GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
 241         GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 242
 243         /* PCI interface settings */
 244         /* Timeout set to retry forever */
 245         GT_REG_WRITE (PCI_0TIMEOUT_RETRY, 0x0);
 246         GT_REG_WRITE (PCI_1TIMEOUT_RETRY, 0x0);
 247
 248         /* ronen - enable only CS0 and Internal reg!! */
 249         GT_REG_WRITE (PCI_0BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
 250         GT_REG_WRITE (PCI_1BASE_ADDRESS_REGISTERS_ENABLE, 0xfffffdfe);
 251
 252 /*ronen update the pci internal registers base address.*/
 253 #ifdef MAP_PCI
 254         for (stat = 0; stat <= PCI_HOST1; stat++)
 255                 pciWriteConfigReg (stat,
 256                                    PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
 257                                    SELF, CONFIG_SYS_GT_REGS);
 258 #endif
 259
 260 }
 261 #endif
 262
 263 /* Setup CPU interface paramaters */
 264 static void gt_cpu_config (void)
 265 {
 266         cpu_t cpu = get_cpu_type ();
 267         ulong tmp;
 268
 269         /* cpu configuration register */
 270         tmp = GTREGREAD (CPU_CONFIGURATION);
 271
 272         /* set the SINGLE_CPU bit  see MV64360 P.399 */
 273 #ifndef CONFIG_SYS_GT_DUAL_CPU          /* SINGLE_CPU seems to cause JTAG problems */
 274         tmp |= CPU_CONF_SINGLE_CPU;
 275 #endif
 276
 277         tmp &= ~CPU_CONF_AACK_DELAY_2;
 278
 279         tmp |= CPU_CONF_DP_VALID;
 280         tmp |= CPU_CONF_AP_VALID;
 281
 282         tmp |= CPU_CONF_PIPELINE;
 283
 284         GT_REG_WRITE (CPU_CONFIGURATION, tmp);  /* Marvell (VXWorks) writes 0x20220FF */
 285
 286         /* CPU master control register */
 287         tmp = GTREGREAD (CPU_MASTER_CONTROL);
 288
 289         tmp |= CPU_MAST_CTL_ARB_EN;
 290
 291         if ((cpu == CPU_7400) ||
 292             (cpu == CPU_7410) || (cpu == CPU_7455) || (cpu == CPU_7450)) {
 293
 294                 tmp |= CPU_MAST_CTL_CLEAN_BLK;
 295                 tmp |= CPU_MAST_CTL_FLUSH_BLK;
 296
 297         } else {
 298                 /* cleanblock must be cleared for CPUs
 299                  * that do not support this command (603e, 750)
 300                  * see Res#1 */
 301                 tmp &= ~CPU_MAST_CTL_CLEAN_BLK;
 302                 tmp &= ~CPU_MAST_CTL_FLUSH_BLK;
 303         }
 304         GT_REG_WRITE (CPU_MASTER_CONTROL, tmp);
 305 }
 306
 307 /*
 308  * board_early_init_f.
 309  *
 310  * set up gal. device mappings, etc.
 311  */
 312 int board_early_init_f (void)
 313 {
 314
 315         /*
 316          * set up the GT the way the kernel wants it
 317          * the call to move the GT register space will obviously
 318          * fail if it has already been done, but we're going to assume
 319          * that if it's not at the power-on location, it's where we put
 320          * it last time. (huber)
 321          */
 322
 323         my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 324
 325         /* No PCI in first release of Port To_do: enable it. */
 326 #ifdef CONFIG_PCI
 327         gt_pci_config ();
 328 #endif
 329         /* mask all external interrupt sources */
 330         GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_LOW, 0);
 331         GT_REG_WRITE (CPU_INTERRUPT_MASK_REGISTER_HIGH, 0);
 332         /* new in MV6436x */
 333         GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_LOW, 0);
 334         GT_REG_WRITE (CPU_INTERRUPT_1_MASK_REGISTER_HIGH, 0);
 335         /* --------------------- */
 336         GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
 337         GT_REG_WRITE (PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
 338         GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW, 0);
 339         GT_REG_WRITE (PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH, 0);
 340         /* does not exist in MV6436x
 341            GT_REG_WRITE(CPU_INT_0_MASK, 0);
 342            GT_REG_WRITE(CPU_INT_1_MASK, 0);
 343            GT_REG_WRITE(CPU_INT_2_MASK, 0);
 344            GT_REG_WRITE(CPU_INT_3_MASK, 0);
 345            --------------------- */
 346
 347
 348         /* ----- DEVICE BUS SETTINGS ------ */
 349
 350         /*
 351          * EVB
 352          * 0 - SRAM   ????
 353          * 1 - RTC      ????
 354          * 2 - UART     ????
 355          * 3 - Flash    checked 32Bit Intel Strata
 356          * boot - BootCS checked 8Bit 29LV040B
 357          *
 358          */
 359
 360         /*
 361          * the dual 7450 module requires burst access to the boot
 362          * device, so the serial rom copies the boot device to the
 363          * on-board sram on the eval board, and updates the correct
 364          * registers to boot from the sram. (device0)
 365          */
 366
 367         memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 368         memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
 369         memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
 370         memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 371
 372
 373         /* configure device timing */
 374         GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 375         GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 376         GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 377         GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
 378
 379 #ifdef CONFIG_SYS_32BIT_BOOT_PAR        /* set port parameters for Flash device module access */
 380         /* detect if we are booting from the 32 bit flash */
 381         if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 382                 /* 32 bit boot flash */
 383                 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 384                 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
 385                               CONFIG_SYS_32BIT_BOOT_PAR);
 386         } else {
 387                 /* 8 bit boot flash */
 388                 GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
 389                 GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 390         }
 391 #else
 392         /* 8 bit boot flash only */
 393 /*      GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
 394 #endif
 395
 396
 397         gt_cpu_config ();
 398
 399         /* MPP setup */
 400         GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
 401         GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
 402         GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
 403         GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 404
 405         GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 406         DEBUG_LED0_ON ();
 407         DEBUG_LED1_ON ();
 408         DEBUG_LED2_ON ();
 409
 410         return 0;
 411 }
 412
 413 /* various things to do after relocation */
 414
 415 int misc_init_r ()
 416 {
 417         icache_enable ();
 418 #ifdef CONFIG_SYS_L2
 419         l2cache_enable ();
 420 #endif
 421 #ifdef CONFIG_MPSC
 422
 423         mpsc_sdma_init ();
 424         mpsc_init2 ();
 425 #endif
 426
 427 #if 0
 428         /* disable the dcache and MMU */
 429         dcache_lock ();
 430 #endif
 431         if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
 432                 unsigned int flash_offset;
 433                 unsigned int l;
 434
 435                 flash_offset =  CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
 436                 for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
 437                         if (flash_info[3].start[l] != 0) {
 438                               flash_info[3].start[l] += flash_offset;
 439                         }
 440                 }
 441                 flash_protect (FLAG_PROTECT_SET,
 442                                CONFIG_SYS_MONITOR_BASE,
 443                                CONFIG_SYS_MONITOR_BASE + monitor_flash_len  - 1,
 444                                &flash_info[3]);
 445         }
 446         return 0;
 447 }
 448
 449 void after_reloc (ulong dest_addr, gd_t * gd)
 450 {
 451
 452   memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
 453
 454   display_mem_map ();
 455   /* now, jump to the main ppcboot board init code */
 456   board_init_r (gd, dest_addr);
 457   /* NOTREACHED */
 458 }
 459
 460 /* ------------------------------------------------------------------------- */
 461
 462 /*
 463  * Check Board Identity:
 464  *
 465  * right now, assume borad type. (there is just one...after all)
 466  */
 467
 468 int checkboard (void)
 469 {
 470         int l_type = 0;
 471
 472         printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 473         return (l_type);
 474 }
 475
 476 /* utility functions */
 477 void debug_led (int led, int mode)
 478 {
 479 }
 480
 481 int display_mem_map (void)
 482 {
 483         int i, j;
 484         unsigned int base, size, width;
 485
 486         /* SDRAM */
 487         printf ("SD (DDR) RAM\n");
 488         for (i = 0; i <= BANK3; i++) {
 489                 base = memoryGetBankBaseAddress (i);
 490                 size = memoryGetBankSize (i);
 491                 if (size != 0) {
 492                         printf ("BANK%d: base - 0x%08x\tsize - %dM bytes\n",
 493                                 i, base, size >> 20);
 494                 }
 495         }
 496 #ifdef CONFIG_PCI
 497         /* CPU's PCI windows */
 498         for (i = 0; i <= PCI_HOST1; i++) {
 499                 printf ("\nCPU's PCI %d windows\n", i);
 500                 base = pciGetSpaceBase (i, PCI_IO);
 501                 size = pciGetSpaceSize (i, PCI_IO);
 502                 printf ("      IO: base - 0x%08x\tsize - %dM bytes\n", base,
 503                         size >> 20);
 504                 for (j = 0;
 505                      j <=
 506                      PCI_REGION0
 507                      /*ronen currently only first PCI MEM is used 3 */ ;
 508                      j++) {
 509                         base = pciGetSpaceBase (i, j);
 510                         size = pciGetSpaceSize (i, j);
 511                         printf ("MEMORY %d: base - 0x%08x\tsize - %dM bytes\n", j, base, size >> 20);
 512                 }
 513         }
 514 #endif /* of CONFIG_PCI */
 515         /* Devices */
 516         printf ("\nDEVICES\n");
 517         for (i = 0; i <= DEVICE3; i++) {
 518                 base = memoryGetDeviceBaseAddress (i);
 519                 size = memoryGetDeviceSize (i);
 520                 width = memoryGetDeviceWidth (i) * 8;
 521                 printf ("DEV %d:  base - 0x%08x  size - %dM bytes\twidth - %d bits", i, base, size >> 20, width);
 522                 if (i == 0)
 523                         printf ("\t- FLASH\n");
 524                 else if (i == 1)
 525                         printf ("\t- FLASH\n");
 526                 else if (i == 2)
 527                         printf ("\t- FLASH\n");
 528                 else
 529                         printf ("\t- RTC/REGS/CAN\n");
 530         }
 531
 532         /* Bootrom */
 533         base = memoryGetDeviceBaseAddress (BOOT_DEVICE);        /* Boot */
 534         size = memoryGetDeviceSize (BOOT_DEVICE);
 535         width = memoryGetDeviceWidth (BOOT_DEVICE) * 8;
 536         printf (" BOOT:  base - 0x%08x  size - %dM bytes\twidth - %d bits\t- FLASH\n",
 537                 base, size >> 20, width);
 538         return (0);
 539 }
 540
 541 /* DRAM check routines copied from gw8260 */
 542
 543 #if defined (CONFIG_SYS_DRAM_TEST)
 544
 545 /*********************************************************************/
 546 /* NAME:  move64() -  moves a double word (64-bit)                   */
 547 /*                                                                   */
 548 /* DESCRIPTION:                                                      */
 549 /*   this function performs a double word move from the data at      */
 550 /*   the source pointer to the location at the destination pointer.  */
 551 /*                                                                   */
 552 /* INPUTS:                                                           */
 553 /*   unsigned long long *src  - pointer to data to move              */
 554 /*                                                                   */
 555 /* OUTPUTS:                                                          */
 556 /*   unsigned long long *dest - pointer to locate to move data       */
 557 /*                                                                   */
 558 /* RETURNS:                                                          */
 559 /*   None                                                            */
 560 /*                                                                   */
 561 /* RESTRICTIONS/LIMITATIONS:                                         */
 562 /*   May cloober fr0.                                                */
 563 /*                                                                   */
 564 /*********************************************************************/
 565 static void move64 (unsigned long long *src, unsigned long long *dest)
 566 {
 567         asm ("lfd  0, 0(3)\n\t" /* fpr0   =  *scr       */
 568              "stfd 0, 0(4)"     /* *dest  =  fpr0       */
 569       : : : "fr0");             /* Clobbers fr0         */
 570         return;
 571 }
 572
 573
 574 #if defined (CONFIG_SYS_DRAM_TEST_DATA)
 575
 576 unsigned long long pattern[] = {
 577         0xaaaaaaaaaaaaaaaaLL,
 578         0xccccccccccccccccLL,
 579         0xf0f0f0f0f0f0f0f0LL,
 580         0xff00ff00ff00ff00LL,
 581         0xffff0000ffff0000LL,
 582         0xffffffff00000000LL,
 583         0x00000000ffffffffLL,
 584         0x0000ffff0000ffffLL,
 585         0x00ff00ff00ff00ffLL,
 586         0x0f0f0f0f0f0f0f0fLL,
 587         0x3333333333333333LL,
 588         0x5555555555555555LL,
 589 };
 590
 591 /*********************************************************************/
 592 /* NAME:  mem_test_data() -  test data lines for shorts and opens    */
 593 /*                                                                   */
 594 /* DESCRIPTION:                                                      */
 595 /*   Tests data lines for shorts and opens by forcing adjacent data  */
 596 /*   to opposite states. Because the data lines could be routed in   */
 597 /*   an arbitrary manner the must ensure test patterns ensure that   */
 598 /*   every case is tested. By using the following series of binary   */
 599 /*   patterns every combination of adjacent bits is test regardless  */
 600 /*   of routing.                                                     */
 601 /*                                                                   */
 602 /*     ...101010101010101010101010                                   */
 603 /*     ...110011001100110011001100                                   */
 604 /*     ...111100001111000011110000                                   */
 605 /*     ...111111110000000011111111                                   */
 606 /*                                                                   */
 607 /*   Carrying this out, gives us six hex patterns as follows:        */
 608 /*                                                                   */
 609 /*     0xaaaaaaaaaaaaaaaa                                            */
 610 /*     0xcccccccccccccccc                                            */
 611 /*     0xf0f0f0f0f0f0f0f0                                            */
 612 /*     0xff00ff00ff00ff00                                            */
 613 /*     0xffff0000ffff0000                                            */
 614 /*     0xffffffff00000000                                            */
 615 /*                                                                   */
 616 /*   The number test patterns will always be given by:               */
 617 /*                                                                   */
 618 /*   log(base 2)(number data bits) = log2 (64) = 6                   */
 619 /*                                                                   */
 620 /*   To test for short and opens to other signals on our boards. we  */
 621 /*   simply                                                          */
 622 /*   test with the 1's complemnt of the paterns as well.             */
 623 /*                                                                   */
 624 /* OUTPUTS:                                                          */
 625 /*   Displays failing test pattern                                   */
 626 /*                                                                   */
 627 /* RETURNS:                                                          */
 628 /*   0 -  Passed test                                                */
 629 /*   1 -  Failed test                                                */
 630 /*                                                                   */
 631 /* RESTRICTIONS/LIMITATIONS:                                         */
 632 /*  Assumes only one one SDRAM bank                                  */
 633 /*                                                                   */
 634 /*********************************************************************/
 635 int mem_test_data (void)
 636 {
 637         unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 638         unsigned long long temp64 = 0;
 639         int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 640         int i;
 641         unsigned int hi, lo;
 642
 643         for (i = 0; i < num_patterns; i++) {
 644                 move64 (&(pattern[i]), pmem);
 645                 move64 (pmem, &temp64);
 646
 647                 /* hi = (temp64>>32) & 0xffffffff;              */
 648                 /* lo = temp64 & 0xffffffff;                    */
 649                 /* printf("\ntemp64 = 0x%08x%08x", hi, lo);     */
 650
 651                 hi = (pattern[i] >> 32) & 0xffffffff;
 652                 lo = pattern[i] & 0xffffffff;
 653                 /* printf("\npattern[%d] = 0x%08x%08x", i, hi, lo);  */
 654
 655                 if (temp64 != pattern[i]) {
 656                         printf ("\n   Data Test Failed, pattern 0x%08x%08x",
 657                                 hi, lo);
 658                         return 1;
 659                 }
 660         }
 661
 662         return 0;
 663 }
 664 #endif /* CONFIG_SYS_DRAM_TEST_DATA */
 665
 666 #if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 667 /*********************************************************************/
 668 /* NAME:  mem_test_address() -  test address lines                   */
 669 /*                                                                   */
 670 /* DESCRIPTION:                                                      */
 671 /*   This function performs a test to verify that each word im       */
 672 /*   memory is uniquly addressable. The test sequence is as follows: */
 673 /*                                                                   */
 674 /*   1) write the address of each word to each word.                 */
 675 /*   2) verify that each location equals its address                 */
 676 /*                                                                   */
 677 /* OUTPUTS:                                                          */
 678 /*   Displays failing test pattern and address                       */
 679 /*                                                                   */
 680 /* RETURNS:                                                          */
 681 /*   0 -  Passed test                                                */
 682 /*   1 -  Failed test                                                */
 683 /*                                                                   */
 684 /* RESTRICTIONS/LIMITATIONS:                                         */
 685 /*                                                                   */
 686 /*                                                                   */
 687 /*********************************************************************/
 688 int mem_test_address (void)
 689 {
 690         volatile unsigned int *pmem =
 691                 (volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
 692         const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 693         unsigned int i;
 694
 695         /* write address to each location */
 696         for (i = 0; i < size; i++) {
 697                 pmem[i] = i;
 698         }
 699
 700         /* verify each loaction */
 701         for (i = 0; i < size; i++) {
 702                 if (pmem[i] != i) {
 703                         printf ("\n   Address Test Failed at 0x%x", i);
 704                         return 1;
 705                 }
 706         }
 707         return 0;
 708 }
 709 #endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 710
 711 #if defined (CONFIG_SYS_DRAM_TEST_WALK)
 712 /*********************************************************************/
 713 /* NAME:   mem_march() -  memory march                               */
 714 /*                                                                   */
 715 /* DESCRIPTION:                                                      */
 716 /*   Marches up through memory. At each location verifies rmask if   */
 717 /*   read = 1. At each location write wmask if  write = 1. Displays  */
 718 /*   failing address and pattern.                                    */
 719 /*                                                                   */
 720 /* INPUTS:                                                           */
 721 /*   volatile unsigned long long * base - start address of test      */
 722 /*   unsigned int size - number of dwords(64-bit) to test            */
 723 /*   unsigned long long rmask - read verify mask                     */
 724 /*   unsigned long long wmask - wrtie verify mask                    */
 725 /*   short read - verifies rmask if read = 1                         */
 726 /*   short write  - writes wmask if write = 1                        */
 727 /*                                                                   */
 728 /* OUTPUTS:                                                          */
 729 /*   Displays failing test pattern and address                       */
 730 /*                                                                   */
 731 /* RETURNS:                                                          */
 732 /*   0 -  Passed test                                                */
 733 /*   1 -  Failed test                                                */
 734 /*                                                                   */
 735 /* RESTRICTIONS/LIMITATIONS:                                         */
 736 /*                                                                   */
 737 /*                                                                   */
 738 /*********************************************************************/
 739 int mem_march (volatile unsigned long long *base,
 740                unsigned int size,
 741                unsigned long long rmask,
 742                unsigned long long wmask, short read, short write)
 743 {
 744         unsigned int i;
 745         unsigned long long temp = 0;
 746         unsigned int hitemp, lotemp, himask, lomask;
 747
 748         for (i = 0; i < size; i++) {
 749                 if (read != 0) {
 750                         /* temp = base[i]; */
 751                         move64 ((unsigned long long *) &(base[i]), &temp);
 752                         if (rmask != temp) {
 753                                 hitemp = (temp >> 32) & 0xffffffff;
 754                                 lotemp = temp & 0xffffffff;
 755                                 himask = (rmask >> 32) & 0xffffffff;
 756                                 lomask = rmask & 0xffffffff;
 757
 758                                 printf ("\n Walking one's test failed: address = 0x%08x," "\n\texpected 0x%08x%08x, found 0x%08x%08x", i << 3, himask, lomask, hitemp, lotemp);
 759                                 return 1;
 760                         }
 761                 }
 762                 if (write != 0) {
 763                         /*  base[i] = wmask; */
 764                         move64 (&wmask, (unsigned long long *) &(base[i]));
 765                 }
 766         }
 767         return 0;
 768 }
 769 #endif /* CONFIG_SYS_DRAM_TEST_WALK */
 770
 771 /*********************************************************************/
 772 /* NAME:   mem_test_walk() -  a simple walking ones test             */
 773 /*                                                                   */
 774 /* DESCRIPTION:                                                      */
 775 /*   Performs a walking ones through entire physical memory. The     */
 776 /*   test uses as series of memory marches, mem_march(), to verify   */
 777 /*   and write the test patterns to memory. The test sequence is as  */
 778 /*   follows:                                                        */
 779 /*     1) march writing 0000...0001                                  */
 780 /*     2) march verifying 0000...0001  , writing  0000...0010        */
 781 /*     3) repeat step 2 shifting masks left 1 bit each time unitl    */
 782 /*         the write mask equals 1000...0000                         */
 783 /*     4) march verifying 1000...0000                                */
 784 /*   The test fails if any of the memory marches return a failure.   */
 785 /*                                                                   */
 786 /* OUTPUTS:                                                          */
 787 /*   Displays which pass on the memory test is executing             */
 788 /*                                                                   */
 789 /* RETURNS:                                                          */
 790 /*   0 -  Passed test                                                */
 791 /*   1 -  Failed test                                                */
 792 /*                                                                   */
 793 /* RESTRICTIONS/LIMITATIONS:                                         */
 794 /*                                                                   */
 795 /*                                                                   */
 796 /*********************************************************************/
 797 int mem_test_walk (void)
 798 {
 799         unsigned long long mask;
 800         volatile unsigned long long *pmem =
 801                 (volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
 802         const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 803
 804         unsigned int i;
 805
 806         mask = 0x01;
 807
 808         printf ("Initial Pass");
 809         mem_march (pmem, size, 0x0, 0x1, 0, 1);
 810
 811         printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
 812         printf ("               ");
 813         printf ("         ");
 814         printf ("\b\b\b\b\b\b\b\b\b\b\b\b");
 815
 816         for (i = 0; i < 63; i++) {
 817                 printf ("Pass %2d", i + 2);
 818                 if (mem_march (pmem, size, mask, mask << 1, 1, 1) != 0) {
 819                         /*printf("mask: 0x%x, pass: %d, ", mask, i); */
 820                         return 1;
 821                 }
 822                 mask = mask << 1;
 823                 printf ("\b\b\b\b\b\b\b");
 824         }
 825
 826         printf ("Last Pass");
 827         if (mem_march (pmem, size, 0, mask, 0, 1) != 0) {
 828                 /* printf("mask: 0x%x", mask); */
 829                 return 1;
 830         }
 831         printf ("\b\b\b\b\b\b\b\b\b");
 832         printf ("            ");
 833         printf ("\b\b\b\b\b\b\b\b\b");
 834
 835         return 0;
 836 }
 837
 838 /*********************************************************************/
 839 /* NAME:    testdram() -  calls any enabled memory tests             */
 840 /*                                                                   */
 841 /* DESCRIPTION:                                                      */
 842 /*   Runs memory tests if the environment test variables are set to  */
 843 /*   'y'.                                                            */
 844 /*                                                                   */
 845 /* INPUTS:                                                           */
 846 /*   testdramdata    - If set to 'y', data test is run.              */
 847 /*   testdramaddress - If set to 'y', address test is run.           */
 848 /*   testdramwalk    - If set to 'y', walking ones test is run       */
 849 /*                                                                   */
 850 /* OUTPUTS:                                                          */
 851 /*   None                                                            */
 852 /*                                                                   */
 853 /* RETURNS:                                                          */
 854 /*   0 -  Passed test                                                */
 855 /*   1 -  Failed test                                                */
 856 /*                                                                   */
 857 /* RESTRICTIONS/LIMITATIONS:                                         */
 858 /*                                                                   */
 859 /*                                                                   */
 860 /*********************************************************************/
 861 int testdram (void)
 862 {
 863         char *s;
 864         int rundata    = 0;
 865         int runaddress = 0;
 866         int runwalk    = 0;
 867
 868 #ifdef CONFIG_SYS_DRAM_TEST_DATA
 869         s = getenv ("testdramdata");
 870         rundata = (s && (*s == 'y')) ? 1 : 0;
 871 #endif
 872 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 873         s = getenv ("testdramaddress");
 874         runaddress = (s && (*s == 'y')) ? 1 : 0;
 875 #endif
 876 #ifdef CONFIG_SYS_DRAM_TEST_WALK
 877         s = getenv ("testdramwalk");
 878         runwalk = (s && (*s == 'y')) ? 1 : 0;
 879 #endif
 880
 881         if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
 882                 printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
 883         }
 884 #ifdef CONFIG_SYS_DRAM_TEST_DATA
 885         if (rundata == 1) {
 886                 printf ("Test DATA ...  ");
 887                 if (mem_test_data () == 1) {
 888                         printf ("failed \n");
 889                         return 1;
 890                 } else
 891                         printf ("ok \n");
 892         }
 893 #endif
 894 #ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 895         if (runaddress == 1) {
 896                 printf ("Test ADDRESS ...  ");
 897                 if (mem_test_address () == 1) {
 898                         printf ("failed \n");
 899                         return 1;
 900                 } else
 901                         printf ("ok \n");
 902         }
 903 #endif
 904 #ifdef CONFIG_SYS_DRAM_TEST_WALK
 905         if (runwalk == 1) {
 906                 printf ("Test WALKING ONEs ...  ");
 907                 if (mem_test_walk () == 1) {
 908                         printf ("failed \n");
 909                         return 1;
 910                 } else
 911                         printf ("ok \n");
 912         }
 913 #endif
 914         if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
 915                 printf ("passed\n");
 916         }
 917         return 0;
 918
 919 }
 920 #endif /* CONFIG_SYS_DRAM_TEST */
 921
 922 /* ronen - the below functions are used by the bootm function           */
 923 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
 924 /*  - we turn off the RX gig dmas - to prevent the dma from overunning  */
 925 /*    the kernel data areas.                                            */
 926 /*  - we diable and invalidate the icache and dcache.                   */
 927 void my_remap_gt_regs_bootm (u32 cur_loc, u32 new_loc)
 928 {
 929         u32 temp;
 930
 931         temp = in_le32 ((u32 *) (new_loc + INTERNAL_SPACE_DECODE));
 932         if ((temp & 0xffff) == new_loc >> 16)
 933                 return;
 934
 935         temp = (in_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE)) &
 936                 0xffff0000) | (new_loc >> 16);
 937
 938         out_le32 ((u32 *) (cur_loc + INTERNAL_SPACE_DECODE), temp);
 939
 940         while ((WORD_SWAP (*((volatile unsigned int *) (NONE_CACHEABLE |
 941                                                         new_loc |
 942                                                         (INTERNAL_SPACE_DECODE)))))
 943                != temp);
 944
 945 }
 946
 947 void board_prebootm_init ()
 948 {
 949
 950 /* change window size of PCI1 IO in order tp prevent overlaping with REG BASE. */
 951                 GT_REG_WRITE (PCI_1_IO_SIZE, (_64K - 1) >> 16);
 952
 953 /* Stop GigE Rx DMA engines */
 954         GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (0), 0x0000ff00);
 955 /*      GT_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (1), 0x0000ff00); */
 956 /*      GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
 957
 958 /* Relocate MV64360 internal regs */
 959         my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
 960
 961         icache_disable ();
 962         dcache_disable ();
 963 }
 964
 965 int do_show_config(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 966 {
 967         unsigned int reset_sample_low;
 968         unsigned int reset_sample_high;
 969         unsigned int l, l1, l2;
 970
 971         GT_REG_READ(0x3c4, &reset_sample_low);
 972         GT_REG_READ(0x3d4, &reset_sample_high);
 973         printf("Reset configuration 0x%08x 0x%08x\n", reset_sample_low, reset_sample_high);
 974
 975         l2 = 0;
 976         for (l=0; l<63; l++) {
 977                 if (show_config_tab[l][0] != 0) {
 978                         printf("%14s:%1x ", show_config_tab[l],
 979                                ((reset_sample_low >> (31 - (l & 0x1f)))) & 0x01);
 980                         l2++;
 981                         if ((l2 % 4) == 0)
 982                                 printf("\n");
 983                 } else {
 984                         l1++;
 985                 }
 986                 if (l == 32)
 987                         reset_sample_low = reset_sample_high;
 988         }
 989         printf("\n");
 990
 991         return(0);
 992 }
 993
 994 U_BOOT_CMD(
 995         show_config,    1,      1,      do_show_config,
 996         "show_config - Show Marvell strapping register\n",
 997         "Show Marvell strapping register (ResetSampleLow ResetSampleHigh)\n"
 998         );