3 * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
5 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/processor.h>
11 #include <asm/bitops.h>
14 #include <asm/ppc440.h>
17 DECLARE_GLOBAL_DATA_PTR;
19 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
20 extern ulong flash_get_size (ulong base, int banknum);
22 int usbhub_init(void);
24 int eeprom_write_enable (unsigned dev_addr, int state);
25 int board_revision(void);
27 static int du440_post_errors;
29 int board_early_init_f(void)
32 u32 sdr0_pfc1, sdr0_pfc2;
35 mtdcr(EBC0_CFGADDR, EBC0_CFG);
36 mtdcr(EBC0_CFGDATA, 0xb8400000);
41 out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
42 out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
43 out_be32((void*)GPIO0_OSRL, 0x50055400);
44 out_be32((void*)GPIO0_OSRH, 0x55005000);
45 out_be32((void*)GPIO0_TSRL, 0x50055400);
46 out_be32((void*)GPIO0_TSRH, 0x55005000);
47 out_be32((void*)GPIO0_ISR1L, 0x50000000);
48 out_be32((void*)GPIO0_ISR1H, 0x00000000);
49 out_be32((void*)GPIO0_ISR2L, 0x00000000);
50 out_be32((void*)GPIO0_ISR2H, 0x00000000);
51 out_be32((void*)GPIO0_ISR3L, 0x00000000);
52 out_be32((void*)GPIO0_ISR3H, 0x00000000);
54 out_be32((void*)GPIO1_OR, 0x00000000);
55 out_be32((void*)GPIO1_TCR, 0xc2000000 |
56 CONFIG_SYS_GPIO1_IORSTN |
57 CONFIG_SYS_GPIO1_IORST2N |
58 CONFIG_SYS_GPIO1_LEDUSR1 |
59 CONFIG_SYS_GPIO1_LEDUSR2 |
60 CONFIG_SYS_GPIO1_LEDPOST |
61 CONFIG_SYS_GPIO1_LEDDU);
62 out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
63 out_be32((void*)GPIO1_OSRL, 0x0c280000);
64 out_be32((void*)GPIO1_OSRH, 0x00000000);
65 out_be32((void*)GPIO1_TSRL, 0xcc000000);
66 out_be32((void*)GPIO1_TSRH, 0x00000000);
67 out_be32((void*)GPIO1_ISR1L, 0x00005550);
68 out_be32((void*)GPIO1_ISR1H, 0x00000000);
69 out_be32((void*)GPIO1_ISR2L, 0x00050000);
70 out_be32((void*)GPIO1_ISR2H, 0x00000000);
71 out_be32((void*)GPIO1_ISR3L, 0x01400000);
72 out_be32((void*)GPIO1_ISR3H, 0x00000000);
75 * Setup the interrupt controller polarities, triggers, etc.
77 mtdcr(UIC0SR, 0xffffffff); /* clear all */
78 mtdcr(UIC0ER, 0x00000000); /* disable all */
79 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
80 mtdcr(UIC0PR, 0xfffff7ff); /* per ref-board manual */
81 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
82 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
83 mtdcr(UIC0SR, 0xffffffff); /* clear all */
87 * bit30: ext. Irq 1: PLD : int 32+30
89 mtdcr(UIC1SR, 0xffffffff); /* clear all */
90 mtdcr(UIC1ER, 0x00000000); /* disable all */
91 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
92 mtdcr(UIC1PR, 0xfffffffd);
93 mtdcr(UIC1TR, 0x00000000);
94 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
95 mtdcr(UIC1SR, 0xffffffff); /* clear all */
99 * bit3: ext. Irq 2: DCF77 : int 64+3
101 mtdcr(UIC2SR, 0xffffffff); /* clear all */
102 mtdcr(UIC2ER, 0x00000000); /* disable all */
103 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
104 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
105 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
106 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
107 mtdcr(UIC2SR, 0xffffffff); /* clear all */
109 /* select Ethernet pins */
110 mfsdr(SDR0_PFC1, sdr0_pfc1);
111 mfsdr(SDR0_PFC2, sdr0_pfc2);
113 /* setup EMAC bridge interface */
114 if (board_revision() == 0) {
116 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
117 SDR0_PFC1_SELECT_CONFIG_1_2;
118 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
119 SDR0_PFC2_SELECT_CONFIG_1_2;
122 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
123 SDR0_PFC1_SELECT_CONFIG_6;
124 sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
125 SDR0_PFC2_SELECT_CONFIG_6;
129 sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL;
131 mtsdr(SDR0_PFC2, sdr0_pfc2);
132 mtsdr(SDR0_PFC1, sdr0_pfc1);
134 /* PCI arbiter enabled */
135 mfsdr(SDR0_PCI0, reg);
136 mtsdr(SDR0_PCI0, 0x80000000 | reg);
138 /* setup NAND FLASH */
139 mfsdr(SDR0_CUST0, sdr0_cust0);
140 sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
141 SDR0_CUST0_NDFC_ENABLE |
142 SDR0_CUST0_NDFC_BW_8_BIT |
143 SDR0_CUST0_NDFC_ARE_MASK |
144 (0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
145 (0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
146 mtsdr(SDR0_CUST0, sdr0_cust0);
151 int misc_init_r(void)
156 unsigned long usb2d0cr = 0;
157 unsigned long usb2phy0cr, usb2h0cr = 0;
158 unsigned long sdr0_pfc1;
159 unsigned long sdr0_srst0, sdr0_srst1;
162 /* adjust flash start and offset */
163 gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
164 gd->bd->bi_flashoffset = 0;
166 mtdcr(EBC0_CFGADDR, PB0CR);
167 pbcr = mfdcr(EBC0_CFGDATA);
168 size_val = ffs(gd->bd->bi_flashsize) - 21;
169 pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
170 mtdcr(EBC0_CFGADDR, PB0CR);
171 mtdcr(EBC0_CFGDATA, pbcr);
174 * Re-check to get correct base address
176 flash_get_size(gd->bd->bi_flashstart, 0);
182 mfsdr(SDR0_PFC1, sdr0_pfc1);
183 mfsdr(SDR0_USB0, usb2d0cr);
184 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
185 mfsdr(SDR0_USB2H0CR, usb2h0cr);
187 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
188 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
189 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
190 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
191 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
192 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
193 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
194 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
195 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
196 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
198 /* An 8-bit/60MHz interface is the only possible alternative
199 when connecting the Device to the PHY */
200 usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
201 usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
203 /* To enable the USB 2.0 Device function through the UTMI interface */
204 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
206 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
207 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
209 mtsdr(SDR0_PFC1, sdr0_pfc1);
210 mtsdr(SDR0_USB0, usb2d0cr);
211 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
212 mtsdr(SDR0_USB2H0CR, usb2h0cr);
215 * Take USB out of reset:
216 * -Initial status = all cores are in reset
217 * -deassert reset to OPB1, P4OPB0, OPB2, PLB42OPB1 OPB2PLB40 cores
219 * -deassert reset to PHY
221 * -deassert reset to HOST
223 * -deassert all other resets
225 mfsdr(SDR0_SRST1, sdr0_srst1);
226 sdr0_srst1 &= ~(SDR0_SRST1_OPBA1 | \
227 SDR0_SRST1_P4OPB0 | \
229 SDR0_SRST1_PLB42OPB1 | \
230 SDR0_SRST1_OPB2PLB40);
231 mtsdr(SDR0_SRST1, sdr0_srst1);
234 mfsdr(SDR0_SRST1, sdr0_srst1);
235 sdr0_srst1 &= ~SDR0_SRST1_USB20PHY;
236 mtsdr(SDR0_SRST1, sdr0_srst1);
239 mfsdr(SDR0_SRST0, sdr0_srst0);
240 sdr0_srst0 &= ~SDR0_SRST0_USB2H;
241 mtsdr(SDR0_SRST0, sdr0_srst0);
244 /* finally all the other resets */
245 mtsdr(SDR0_SRST1, 0x00000000);
246 mtsdr(SDR0_SRST0, 0x00000000);
248 printf("USB: Host(int phy)\n");
251 * Clear PLB4A0_ACR[WRP]
252 * This fix will make the MAL burst disabling patch for the Linux
253 * EMAC driver obsolete.
255 reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
256 mtdcr(PLB4A0_ACR, reg);
260 * We have to wait at least 560ms until we may call usbhub_init
262 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
263 CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
266 * flash USR1/2 LEDs (600ms)
267 * This results in the necessary delay from IORST# until
268 * calling usbhub_init will succeed
270 for (j = 0; j < 3; j++) {
271 out_be32((void*)GPIO1_OR,
272 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
273 CONFIG_SYS_GPIO1_LEDUSR1);
275 for (i = 0; i < 100; i++)
278 out_be32((void*)GPIO1_OR,
279 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
280 CONFIG_SYS_GPIO1_LEDUSR2);
282 for (i = 0; i < 100; i++)
286 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
287 ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
298 int pld_revision(void)
300 out_8((void *)CONFIG_SYS_CPLD_BASE, 0x00);
301 return (int)(in_8((void *)CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
304 int board_revision(void)
306 int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
307 >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
309 return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
310 ((rpins & 4) >> 1) | ((rpins & 8) >> 3);
313 #if defined(CONFIG_SHOW_ACTIVITY)
314 void board_show_activity (ulong timestamp)
316 if ((timestamp % 100) == 0)
317 out_be32((void*)GPIO1_OR,
318 in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
321 void show_activity(int arg)
324 #endif /* CONFIG_SHOW_ACTIVITY */
326 int du440_phy_addr(int devnum)
328 if (board_revision() == 0)
338 puts("Board: DU440");
340 if (getenv_f("serial#", serno, sizeof(serno)) > 0) {
345 printf(", HW-Rev. 1.%d, CPLD-Rev. 1.%d\n",
346 board_revision(), pld_revision());
350 int last_stage_init(void)
354 /* everyting is ok: turn on POST-LED */
355 out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
357 /* slowly blink on errors and finally keep LED off */
358 for (e = 0; e < du440_post_errors; e++) {
359 out_be32((void*)GPIO1_OR,
360 in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
362 for (i = 0; i < 500; i++)
365 out_be32((void*)GPIO1_OR,
366 in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
368 for (i = 0; i < 500; i++)
375 #if defined(CONFIG_I2C_MULTI_BUS)
377 * read field strength from I2C ADC
379 int dcf77_status(void)
385 oldbus = I2C_GET_BUS();
388 if (i2c_read (IIC1_MCP3021_ADDR, 0, 0, u, 2)) {
393 mv = (int)(((u[0] << 8) | u[1]) >> 2) * 3300 / 1024;
399 int do_dcf77(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
403 unsigned long long t1, t2;
409 printf("signal=%d mV\n", mv);
411 printf("ERROR - no signal\n");
414 pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
416 pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
417 if (pin && !pinold) { /* bit start */
419 if (t2 && ((unsigned int)(t1 - t2) /
420 (bd->bi_procfreq / 1000) >= 1800))
421 printf("Start of minute\n");
425 if (t1 && !pin && pinold) { /* bit end */
426 printf("%5d\n", (unsigned int)(get_ticks() - t1) /
427 (bd->bi_procfreq / 1000));
436 dcf77, 1, 1, do_dcf77,
437 "Check DCF77 receiver",
442 * initialize USB hub via I2C1
444 int usbhub_init(void)
449 uchar u[] = {0x04, 0x24, 0x04, 0x07, 0x25, 0x00, 0x00, 0xd3,
450 0x18, 0xe0, 0x00, 0x00, 0x01, 0x64, 0x01, 0x64,
456 oldbus = I2C_GET_BUS();
459 for (reg = 0; reg < sizeof(u); reg++)
460 if (i2c_write (IIC1_USB2507_ADDR, reg, 1, &u[reg], 1)) {
467 if (i2c_write (IIC1_USB2507_ADDR, 0, 1, &stcd, 1))
472 printf("initialized\n");
474 printf("failed - cannot initialize USB hub\n");
480 int do_hubinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
486 hubinit, 1, 1, do_hubinit,
487 "Initialize USB hub",
490 #endif /* CONFIG_I2C_MULTI_BUS */
492 #define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
493 int boot_eeprom_write (unsigned dev_addr,
498 unsigned end = offset + cnt;
502 #if defined(CONFIG_SYS_EEPROM_WREN)
503 eeprom_write_enable(dev_addr, 1);
506 * Write data until done or would cross a write page boundary.
507 * We must write the address again when changing pages
508 * because the address counter only increments within a page.
511 while (offset < end) {
517 blk_off = offset & 0xFF; /* block offset */
519 addr[0] = offset >> 8; /* block number */
520 addr[1] = blk_off; /* block offset */
522 addr[0] |= dev_addr; /* insert device address */
527 * For a FRAM device there is no limit on the number of the
528 * bytes that can be ccessed with the single read or write
531 #if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
533 #define BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
534 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
536 maxlen = BOOT_EEPROM_PAGE_SIZE -
537 BOOT_EEPROM_PAGE_OFFSET(blk_off);
539 maxlen = 0x100 - blk_off;
541 if (maxlen > I2C_RXTX_LEN)
542 maxlen = I2C_RXTX_LEN;
547 if (i2c_write (addr[0], offset, alen - 1, buffer, len) != 0)
553 #if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
554 udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
557 #if defined(CONFIG_SYS_EEPROM_WREN)
558 eeprom_write_enable(dev_addr, 0);
563 int do_setup_boot_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
568 if (!strcmp(argv[1], "533")) {
569 printf("Bootstrapping for 533MHz\n");
570 sdsdp[0] = 0x87788252;
571 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
572 sdsdp[1] = 0x095fa030;
573 sdsdp[2] = 0x40082350;
574 sdsdp[3] = 0x0d050000;
575 } else if (!strcmp(argv[1], "533-66")) {
576 printf("Bootstrapping for 533MHz (66MHz PCI)\n");
577 sdsdp[0] = 0x87788252;
578 /* PLB-PCI-divider = 2 : sync PCI clock=66MHz */
579 sdsdp[1] = 0x0957a030;
580 sdsdp[2] = 0x40082350;
581 sdsdp[3] = 0x0d050000;
582 } else if (!strcmp(argv[1], "667")) {
583 printf("Bootstrapping for 667MHz\n");
584 sdsdp[0] = 0x8778a256;
585 /* PLB-PCI-divider = 4 : sync PCI clock=33MHz */
586 sdsdp[1] = 0x0947a030;
587 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz
588 * -> not working when overclocking 533MHz chips
589 * -> untested on 667MHz chips */
590 /* sdsdp[1]=0x095fa030; */
591 sdsdp[2] = 0x40082350;
592 sdsdp[3] = 0x0d050000;
593 } else if (!strcmp(argv[1], "667-166")) {
594 printf("Bootstrapping for 667-166MHz\n");
595 sdsdp[0] = 0x8778a252;
596 sdsdp[1] = 0x09d7a030;
597 sdsdp[2] = 0x40082350;
598 sdsdp[3] = 0x0d050000;
601 printf("Bootstrapping for 533MHz (default)\n");
602 sdsdp[0] = 0x87788252;
603 /* PLB-PCI-divider = 3 : sync PCI clock=44MHz */
604 sdsdp[1] = 0x095fa030;
605 sdsdp[2] = 0x40082350;
606 sdsdp[3] = 0x0d050000;
609 printf("Writing boot EEPROM ...\n");
610 if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
611 0, (uchar*)sdsdp, 16) != 0)
612 printf("boot_eeprom_write failed\n");
614 printf("done (dump via 'i2c md 52 0.1 10')\n");
619 sbe, 2, 0, do_setup_boot_eeprom,
624 #if defined(CONFIG_SYS_EEPROM_WREN)
626 * Input: <dev_addr> I2C address of EEPROM device to enable.
627 * <state> -1: deliver current state
630 * Returns: -1: wrong device address
631 * 0: dis-/en- able done
632 * 0/1: current state if <state> was -1.
634 int eeprom_write_enable (unsigned dev_addr, int state)
636 if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
637 (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
642 /* Enable write access, clear bit GPIO_SINT2. */
643 out_be32((void*)GPIO0_OR,
644 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
648 /* Disable write access, set bit GPIO_SINT2. */
649 out_be32((void*)GPIO0_OR,
650 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
654 /* Read current status back. */
655 state = (0 == (in_be32((void*)GPIO0_OR) &
656 CONFIG_SYS_GPIO0_EP_EEP));
663 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
665 int query = argc == 1;
669 /* Query write access state. */
670 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
672 puts ("Query of write access state failed.\n");
674 printf ("Write access for device 0x%0x is %sabled.\n",
675 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
679 if ('0' == argv[1][0]) {
680 /* Disable write access. */
681 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
683 /* Enable write access. */
684 state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
687 puts ("Setup of write access state failed.\n");
693 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
694 "Enable / disable / query EEPROM write access",
697 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
699 static int got_pldirq;
701 static int pld_interrupt(u32 arg)
703 int rc = -1; /* not for us */
704 u8 status = in_8((void *)CONFIG_SYS_CPLD_BASE);
706 /* check for PLD interrupt */
707 if (status & PWR_INT_FLAG) {
709 out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
711 got_pldirq = 1; /* trigger backend */
717 int do_waitpwrirq(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
721 /* clear any pending interrupt */
722 out_8((void *)CONFIG_SYS_CPLD_BASE, 0);
724 irq_install_handler(CPLD_IRQ,
725 (interrupt_handler_t *)pld_interrupt, 0);
727 printf("Waiting ...\n");
729 /* Abort if ctrl-c was pressed */
736 printf("Got interrupt!\n");
737 printf("Power %sready!\n",
738 in_8((void *)CONFIG_SYS_CPLD_BASE) &
739 PWR_RDY ? "":"NOT ");
742 irq_free_handler(CPLD_IRQ);
746 wpi, 1, 1, do_waitpwrirq,
747 "Wait for power change interrupt",
752 * initialize DVI panellink transmitter
759 uchar u[] = {0x08, 0x34,
767 oldbus = I2C_GET_BUS();
770 for (i = 0; i < sizeof(u); i += 2)
771 if (i2c_write (0x38, u[i], 1, &u[i + 1], 1)) {
777 printf("initialized\n");
779 printf("failed - cannot initialize DVI transmitter\n");
785 int do_dviinit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
791 dviinit, 1, 1, do_dviinit,
792 "Initialize DVI Panellink transmitter",
797 * TODO: 'time' command might be useful for others as well.
798 * Move to 'common' directory.
800 int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
802 unsigned long long start, end;
803 char c, cmd[CONFIG_SYS_CBSIZE];
808 for (i = 1; i < argc; i++) {
814 while ((c = *p++) != '\0') {
821 ret = run_command(cmd, 0);
824 printf("ticks=%ld\n", (ulong)(end - start));
825 us = (ulong)((1000L * (end - start)) / (get_tbclk() / 1000));
826 printf("usec=%ld\n", us);
831 time, CONFIG_SYS_MAXARGS, 1, do_time,
832 "run command and output execution time",
836 extern void video_hw_rectfill (
837 unsigned int bpp, /* bytes per pixel */
838 unsigned int dst_x, /* dest pos x */
839 unsigned int dst_y, /* dest pos y */
840 unsigned int dim_x, /* frame width */
841 unsigned int dim_y, /* frame height */
842 unsigned int color /* fill color */
847 * draw rectangles using pseudorandom number generator
848 * (see http://www.embedded.com/columns/technicalinsights/20900500)
850 unsigned int rprime = 9972;
851 static unsigned int r;
852 static unsigned int Y;
854 unsigned int prng(unsigned int max)
856 if (r == 0 || r == 1 || r == -1)
857 r = rprime; /* keep from getting stuck */
859 r = (9973 * ~r) + ((Y) % 701); /* the actual algorithm */
860 Y = (r >> 16) % max; /* choose upper bits and reduce */
864 int do_gfxdemo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
867 unsigned int x, y, dx, dy;
872 dx = prng(1280- x - 1);
873 dy = prng(1024 - y - 1);
874 color = prng(0x10000);
875 video_hw_rectfill(2, x, y, dx, dy, color);
881 gfxdemo, CONFIG_SYS_MAXARGS, 1, do_gfxdemo,