board/esd/hh405/hh405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * (C) Copyright 2005
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * (C) Copyright 2006-2007
   9  * Matthias Fuchs, esd GmbH, matthias.fuchs@esd-electronics.com
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #include <common.h>
  31 #include <asm/processor.h>
  32 #include <asm/io.h>
  33 #include <command.h>
  34 #include <malloc.h>
  35 #include <pci.h>
  36 #include <sm501.h>
  37
  38 DECLARE_GLOBAL_DATA_PTR;
  39
  40 /* FPGA internal regs */
  41 #define FPGA_CTRL       ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x000))
  42 #define FPGA_STATUS     ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x002))
  43 #define FPGA_CTR        ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x004))
  44 #define FPGA_BL         ((u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + 0x006))
  45
  46 /* FPGA Control Reg */
  47 #define FPGA_CTRL_REV0      0x0001
  48 #define FPGA_CTRL_REV1      0x0002
  49 #define FPGA_CTRL_VGA0_BL   0x0004
  50 #define FPGA_CTRL_VGA0_BL_MODE 0x0008
  51 #define FPGA_CTRL_CF_RESET  0x0040
  52 #define FPGA_CTRL_PS2_PWR   0x0080
  53 #define FPGA_CTRL_CF_PWRN   0x0100      /* low active */
  54 #define FPGA_CTRL_CF_BUS_EN 0x0200
  55 #define FPGA_CTRL_LCD_CLK   0x7000      /* mask for lcd clock */
  56 #define FPGA_CTRL_OW_ENABLE 0x8000
  57
  58 #define FPGA_STATUS_CF_DETECT 0x8000
  59
  60 #ifdef CONFIG_VIDEO_SM501
  61
  62 #define SWAP32(x)        ((((x) & 0x000000ff) << 24) | (((x) & 0x0000ff00) << 8)|\
  63                           (((x) & 0x00ff0000) >>  8) | (((x) & 0xff000000) >> 24) )
  64
  65 #ifdef CONFIG_VIDEO_SM501_8BPP
  66 #error CONFIG_VIDEO_SM501_8BPP not supported.
  67 #endif /* CONFIG_VIDEO_SM501_8BPP */
  68
  69 #ifdef CONFIG_VIDEO_SM501_16BPP
  70 #define BPP     16
  71
  72 /*
  73  * 800x600 display B084SN03: PCLK = 40MHz
  74  * => 2*PCLK = 80MHz
  75  * 336/4 = 84MHz
  76  * => PCLK = 84MHz
  77  */
  78 static const SMI_REGS init_regs_800x600 [] =
  79 {
  80 #if 1 /* test-only */
  81         {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
  82 #else
  83         {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
  84 #endif
  85         {0x00004, SWAP32(0x00000000)},
  86         /* clocks for pm1... */
  87         {0x00048, SWAP32(0x00021807)},
  88         {0x0004C, SWAP32(0x221a0a01)},
  89         {0x00054, SWAP32(0x00000001)},
  90         /* clocks for pm0... */
  91         {0x00040, SWAP32(0x00021807)},
  92         {0x00044, SWAP32(0x221a0a01)},
  93         {0x00054, SWAP32(0x00000000)},
  94         /* GPIO */
  95         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
  96         /* panel control regs... */
  97         {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
  98         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
  99         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
 100         {0x80010, SWAP32(0x06400640)}, /* panel fb offset/window width */
 101         {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
 102         {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
 103         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 104         {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
 105         {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
 106         {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
 107         {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
 108         {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
 109         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 110         {0, 0}
 111 };
 112
 113 /*
 114  * 1024x768 display G150XG02: PCLK = 65MHz
 115  * => 2*PCLK = 130MHz
 116  * 288/2 = 144MHz
 117  * => PCLK = 72MHz
 118  */
 119 static const SMI_REGS init_regs_1024x768 [] =
 120 {
 121         {0x00004, SWAP32(0x00000000)},
 122         /* clocks for pm1... */
 123         {0x00048, SWAP32(0x00021807)},
 124         {0x0004C, SWAP32(0x011a0a01)},
 125         {0x00054, SWAP32(0x00000001)},
 126         /* clocks for pm0... */
 127         {0x00040, SWAP32(0x00021807)},
 128         {0x00044, SWAP32(0x011a0a01)},
 129         {0x00054, SWAP32(0x00000000)},
 130         /* GPIO */
 131         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
 132         /* panel control regs... */
 133         {0x80000, SWAP32(0x0f013105)}, /* panel display control: 16-bit RGB 5:6:5 mode */
 134         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 135         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
 136         {0x80010, SWAP32(0x08000800)}, /* panel fb offset/window width */
 137         {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
 138         {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
 139         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 140         {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
 141         {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
 142         {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
 143         {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
 144         {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
 145         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 146         {0, 0}
 147 };
 148
 149 #endif /* CONFIG_VIDEO_SM501_16BPP */
 150
 151 #ifdef CONFIG_VIDEO_SM501_32BPP
 152 #define BPP     32
 153
 154 /*
 155  * 800x600 display B084SN03: PCLK = 40MHz
 156  * => 2*PCLK = 80MHz
 157  * 336/4 = 84MHz
 158  * => PCLK = 84MHz
 159  */
 160 static const SMI_REGS init_regs_800x600 [] =
 161 {
 162 #if 0 /* test-only */
 163         {0x0005c, SWAP32(0xffffffff)}, /* set endianess to big endian */
 164 #else
 165         {0x0005c, SWAP32(0x00000000)}, /* set endianess to little endian */
 166 #endif
 167         {0x00004, SWAP32(0x00000000)},
 168         /* clocks for pm1... */
 169         {0x00048, SWAP32(0x00021807)},
 170         {0x0004C, SWAP32(0x221a0a01)},
 171         {0x00054, SWAP32(0x00000001)},
 172         /* clocks for pm0... */
 173         {0x00040, SWAP32(0x00021807)},
 174         {0x00044, SWAP32(0x221a0a01)},
 175         {0x00054, SWAP32(0x00000000)},
 176         /* GPIO */
 177         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
 178         /* panel control regs... */
 179         {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
 180         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 181         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
 182         {0x80010, SWAP32(0x0c800c80)}, /* panel fb offset/window width */
 183         {0x80014, SWAP32(0x03200000)}, /* panel fb width (0x320=800) */
 184         {0x80018, SWAP32(0x02580000)}, /* panel fb height (0x258=600) */
 185         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 186         {0x80020, SWAP32(0x02580320)}, /* panel plane br location */
 187         {0x80024, SWAP32(0x041f031f)}, /* panel horizontal total */
 188         {0x80028, SWAP32(0x00800347)}, /* panel horizontal sync */
 189         {0x8002C, SWAP32(0x02730257)}, /* panel vertical total */
 190         {0x80030, SWAP32(0x00040258)}, /* panel vertical sync */
 191         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 192         {0, 0}
 193 };
 194
 195 /*
 196  * 1024x768 display G150XG02: PCLK = 65MHz
 197  * => 2*PCLK = 130MHz
 198  * 288/2 = 144MHz
 199  * => PCLK = 72MHz
 200  */
 201 static const SMI_REGS init_regs_1024x768 [] =
 202 {
 203         {0x00004, SWAP32(0x00000000)},
 204         /* clocks for pm1... */
 205         {0x00048, SWAP32(0x00021807)},
 206         {0x0004C, SWAP32(0x011a0a01)},
 207         {0x00054, SWAP32(0x00000001)},
 208         /* clocks for pm0... */
 209         {0x00040, SWAP32(0x00021807)},
 210         {0x00044, SWAP32(0x011a0a01)},
 211         {0x00054, SWAP32(0x00000000)},
 212         /* GPIO */
 213         {0x1000c, SWAP32(0xfffffff0)}, /* GPIO32..63 direction */
 214         /* panel control regs... */
 215         {0x80000, SWAP32(0x0f013106)}, /* panel display control: 32-bit RGB 8:8:8 mode */
 216         {0x80004, SWAP32(0xc428bb17)}, /* panel panning control ??? */
 217         {0x8000C, SWAP32(0x00010000)}, /* panel fb address */
 218         {0x80010, SWAP32(0x10001000)}, /* panel fb offset/window width */
 219         {0x80014, SWAP32(0x04000000)}, /* panel fb width (0x400=1024) */
 220         {0x80018, SWAP32(0x03000000)}, /* panel fb height (0x300=768) */
 221         {0x8001C, SWAP32(0x00000000)}, /* panel plane tl location */
 222         {0x80020, SWAP32(0x03000400)}, /* panel plane br location */
 223         {0x80024, SWAP32(0x053f03ff)}, /* panel horizontal total */
 224         {0x80028, SWAP32(0x0140040f)}, /* panel horizontal sync */
 225         {0x8002C, SWAP32(0x032502ff)}, /* panel vertical total */
 226         {0x80030, SWAP32(0x00260301)}, /* panel vertical sync */
 227         {0x80200, SWAP32(0x00010000)}, /* crt display control */
 228         {0, 0}
 229 };
 230
 231 #endif /* CONFIG_VIDEO_SM501_32BPP */
 232
 233 #endif /* CONFIG_VIDEO_SM501 */
 234
 235 #if 0
 236 #define FPGA_DEBUG
 237 #endif
 238
 239 extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
 240 extern void lxt971_no_sleep(void);
 241
 242 /* fpga configuration data - gzip compressed and generated by bin2c */
 243 const unsigned char fpgadata[] =
 244 {
 245 #include "fpgadata.c"
 246 };
 247
 248 /*
 249  * include common fpga code (for esd boards)
 250  */
 251 #include "../common/fpga.c"
 252
 253
 254 /* logo bitmap data - gzip compressed and generated by bin2c */
 255 unsigned char logo_bmp_320[] =
 256 {
 257 #include "logo_320_240_4bpp.c"
 258 };
 259
 260 unsigned char logo_bmp_320_8bpp[] =
 261 {
 262 #include "logo_320_240_8bpp.c"
 263 };
 264
 265 unsigned char logo_bmp_640[] =
 266 {
 267 #include "logo_640_480_24bpp.c"
 268 };
 269
 270 unsigned char logo_bmp_1024[] =
 271 {
 272 #include "logo_1024_768_8bpp.c"
 273 };
 274
 275
 276 /*
 277  * include common lcd code (for esd boards)
 278  */
 279 #include "../common/lcd.c"
 280
 281 #include "../common/s1d13704_320_240_4bpp.h"
 282 #include "../common/s1d13705_320_240_8bpp.h"
 283 #include "../common/s1d13806_640_480_16bpp.h"
 284 #include "../common/s1d13806_1024_768_8bpp.h"
 285
 286
 287 /*
 288  * include common auto-update code (for esd boards)
 289  */
 290 #include "../common/auto_update.h"
 291
 292 au_image_t au_image[] = {
 293         {"hh405/preinst.img", 0, -1, AU_SCRIPT},
 294         {"hh405/u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE},
 295         {"hh405/pImage_${bd_type}", 0x00000000, 0x00100000, AU_NAND},
 296         {"hh405/pImage.initrd", 0x00100000, 0x00200000, AU_NAND},
 297         {"hh405/yaffsmt2.img", 0x00300000, 0x01c00000, AU_NAND},
 298         {"hh405/postinst.img", 0, 0, AU_SCRIPT},
 299 };
 300
 301 int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
 302
 303
 304 /*
 305  * Get version of HH405 board from GPIO's
 306  */
 307 int board_revision(void)
 308 {
 309         unsigned long osrh_reg;
 310         unsigned long isr1h_reg;
 311         unsigned long tcr_reg;
 312         unsigned long value;
 313
 314         /*
 315          * Setup GPIO pins (BLAST/GPIO0 and GPIO9 as GPIO)
 316          */
 317         osrh_reg = in_be32((void *)GPIO0_OSRH);
 318         isr1h_reg = in_be32((void *)GPIO0_ISR1H);
 319         tcr_reg = in_be32((void *)GPIO0_TCR);
 320         out_be32((void *)GPIO0_OSRH, osrh_reg & ~0xC0003000);     /* output select */
 321         out_be32((void *)GPIO0_ISR1H, isr1h_reg | 0xC0003000);    /* input select  */
 322         out_be32((void *)GPIO0_TCR, tcr_reg & ~0x80400000);       /* select input  */
 323
 324         udelay(1000);            /* wait some time before reading input */
 325         value = in_be32((void *)GPIO0_IR) & 0x80400000;         /* get config bits */
 326
 327         /*
 328          * Restore GPIO settings
 329          */
 330         out_be32((void *)GPIO0_OSRH, osrh_reg);                   /* output select */
 331         out_be32((void *)GPIO0_ISR1H, isr1h_reg);                 /* input select  */
 332         out_be32((void *)GPIO0_TCR, tcr_reg);  /* enable output driver for outputs */
 333
 334         if (value & 0x80000000) {
 335                 /* Revision 1.0 or 1.1 detected */
 336                 return 1;
 337         } else {
 338                 if (value & 0x00400000) {
 339                         /* unused */
 340                         return 3;
 341                 } else {
 342                         return 2;
 343                 }
 344         }
 345 }
 346
 347
 348 int board_early_init_f (void)
 349 {
 350         /*
 351          * IRQ 0-15  405GP internally generated; active high; level sensitive
 352          * IRQ 16    405GP internally generated; active low; level sensitive
 353          * IRQ 17-24 RESERVED
 354          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
 355          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
 356          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
 357          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
 358          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
 359          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
 360          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
 361          */
 362         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 363         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
 364         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
 365         mtdcr(UIC0PR, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
 366         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
 367         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 368         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
 369
 370         /*
 371          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
 372          */
 373         mtebc(EBC0_CFG, 0xa8400000); /* ebc always driven */
 374
 375         return 0;
 376 }
 377
 378 int cf_enable(void)
 379 {
 380         int i;
 381
 382         if (gd->board_type >= 2) {
 383                 if (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT) {
 384                         if (!(in_be16(FPGA_CTRL) & FPGA_CTRL_CF_BUS_EN)) {
 385                                 out_be16(FPGA_CTRL,
 386                                          in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_PWRN);
 387
 388                                 for (i=0; i<300; i++)
 389                                         udelay(1000);
 390
 391                                 out_be16(FPGA_CTRL,
 392                                          in_be16(FPGA_CTRL) | FPGA_CTRL_CF_BUS_EN);
 393
 394                                 for (i=0; i<20; i++)
 395                                         udelay(1000);
 396                         }
 397                 } else {
 398                         out_be16(FPGA_CTRL,
 399                                  in_be16(FPGA_CTRL) & ~FPGA_CTRL_CF_BUS_EN);
 400                         out_be16(FPGA_CTRL,
 401                                  in_be16(FPGA_CTRL) | FPGA_CTRL_CF_PWRN);
 402                 }
 403         }
 404
 405         return 0;
 406 }
 407
 408 int misc_init_r (void)
 409 {
 410         unsigned char *dst;
 411         ulong len = sizeof(fpgadata);
 412         int status;
 413         int index;
 414         int i;
 415         char *str;
 416         unsigned long contrast0 = 0xffffffff;
 417
 418         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 419         if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 420                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 421                 do_reset (NULL, 0, 0, NULL);
 422         }
 423
 424         status = fpga_boot(dst, len);
 425         if (status != 0) {
 426                 printf("\nFPGA: Booting failed ");
 427                 switch (status) {
 428                 case ERROR_FPGA_PRG_INIT_LOW:
 429                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 430                         break;
 431                 case ERROR_FPGA_PRG_INIT_HIGH:
 432                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 433                         break;
 434                 case ERROR_FPGA_PRG_DONE:
 435                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 436                         break;
 437                 }
 438
 439                 /* display infos on fpgaimage */
 440                 index = 15;
 441                 for (i=0; i<4; i++) {
 442                         len = dst[index];
 443                         printf("FPGA: %s\n", &(dst[index+1]));
 444                         index += len+3;
 445                 }
 446                 putc ('\n');
 447                 /* delayed reboot */
 448                 for (i=20; i>0; i--) {
 449                         printf("Rebooting in %2d seconds \r",i);
 450                         for (index=0;index<1000;index++)
 451                                 udelay(1000);
 452                 }
 453                 putc ('\n');
 454                 do_reset(NULL, 0, 0, NULL);
 455         }
 456
 457         puts("FPGA:  ");
 458
 459         /* display infos on fpgaimage */
 460         index = 15;
 461         for (i=0; i<4; i++) {
 462                 len = dst[index];
 463                 printf("%s ", &(dst[index+1]));
 464                 index += len+3;
 465         }
 466         putc ('\n');
 467
 468         free(dst);
 469
 470         /*
 471          * Reset FPGA via FPGA_INIT pin
 472          */
 473         /* setup FPGA_INIT as output */
 474         out_be32((void *)GPIO0_TCR,
 475                  in_be32((void *)GPIO0_TCR) | FPGA_INIT);
 476         out_be32((void *)GPIO0_OR,
 477                  in_be32((void *)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
 478         udelay(1000); /* wait 1ms */
 479         out_be32((void *)GPIO0_OR,
 480                  in_be32((void *)GPIO0_OR) | FPGA_INIT);   /* reset high */
 481         udelay(1000); /* wait 1ms */
 482
 483         /*
 484          * Write Board revision into FPGA
 485          */
 486         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | (gd->board_type & 0x0003));
 487
 488         /*
 489          * Setup and enable EEPROM write protection
 490          */
 491         out_be32((void *)GPIO0_OR,
 492                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 493
 494         /*
 495          * Reset touch-screen controller
 496          */
 497         out_be32((void *)GPIO0_OR,
 498                  in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
 499         udelay(1000);
 500         out_be32((void *)GPIO0_OR,
 501                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
 502
 503         /*
 504          * Enable power on PS/2 interface (with reset)
 505          */
 506         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) & ~FPGA_CTRL_PS2_PWR);
 507         for (i=0;i<500;i++)
 508                 udelay(1000);
 509         out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | FPGA_CTRL_PS2_PWR);
 510
 511         /*
 512          * Get contrast value from environment variable
 513          */
 514         str = getenv("contrast0");
 515         if (str) {
 516                 contrast0 = simple_strtol(str, NULL, 16);
 517                 if (contrast0 > 255) {
 518                         printf("ERROR: contrast0 value too high (0x%lx)!\n",
 519                                contrast0);
 520                         contrast0 = 0xffffffff;
 521                 }
 522         }
 523
 524         /*
 525          * Init lcd interface and display logo
 526          */
 527
 528         str = getenv("bd_type");
 529         if (strcmp(str, "ppc230") == 0) {
 530                 /*
 531                  * Switch backlight on
 532                  */
 533                 out_be16(FPGA_CTRL,
 534                          in_be16(FPGA_CTRL) | FPGA_CTRL_VGA0_BL);
 535                 out_be16(FPGA_BL, 0x0000);
 536
 537                 lcd_setup(1, 0);
 538                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 539                          regs_13806_1024_768_8bpp,
 540                          sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
 541                          logo_bmp_1024, sizeof(logo_bmp_1024));
 542         } else if (strcmp(str, "ppc220") == 0) {
 543                 /*
 544                  * Switch backlight on
 545                  */
 546                 out_be16(FPGA_CTRL,
 547                          in_be16(FPGA_CTRL) & ~FPGA_CTRL_VGA0_BL);
 548                 out_be16(FPGA_BL, 0x0000);
 549
 550                 lcd_setup(1, 0);
 551                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 552                          regs_13806_640_480_16bpp,
 553                          sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 554                          logo_bmp_640, sizeof(logo_bmp_640));
 555         } else if (strcmp(str, "ppc215") == 0) {
 556                 /*
 557                  * Set default display contrast voltage
 558                  */
 559                 if (contrast0 == 0xffffffff) {
 560                         out_be16(FPGA_CTR, 0x0082);
 561                 } else {
 562                         out_be16(FPGA_CTR, contrast0);
 563                 }
 564                 out_be16(FPGA_BL, 0xffff);
 565                 /*
 566                  * Switch backlight on
 567                  */
 568                 out_be16(FPGA_CTRL,
 569                          in_be16(FPGA_CTRL) |
 570                          FPGA_CTRL_VGA0_BL |
 571                          FPGA_CTRL_VGA0_BL_MODE);
 572                 /*
 573                  * Set lcd clock (small epson)
 574                  */
 575                 out_be16(FPGA_CTRL, in_be16(FPGA_CTRL) | LCD_CLK_06250);
 576                 udelay(100);               /* wait for 100 us */
 577
 578                 lcd_setup(0, 1);
 579                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 580                          regs_13705_320_240_8bpp,
 581                          sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
 582                          logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
 583         } else if (strcmp(str, "ppc210") == 0) {
 584                 /*
 585                  * Set default display contrast voltage
 586                  */
 587                 if (contrast0 == 0xffffffff) {
 588                         out_be16(FPGA_CTR, 0x0060);
 589                 } else {
 590                         out_be16(FPGA_CTR, contrast0);
 591                 }
 592                 out_be16(FPGA_BL, 0xffff);
 593                 /*
 594                  * Switch backlight on
 595                  */
 596                 out_be16(FPGA_CTRL,
 597                          in_be16(FPGA_CTRL) |
 598                          FPGA_CTRL_VGA0_BL |
 599                          FPGA_CTRL_VGA0_BL_MODE);
 600                 /*
 601                  * Set lcd clock (small epson), enable 1-wire interface
 602                  */
 603                 out_be16(FPGA_CTRL,
 604                          in_be16(FPGA_CTRL) |
 605                          LCD_CLK_08330 |
 606                          FPGA_CTRL_OW_ENABLE);
 607
 608                 lcd_setup(0, 1);
 609                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 610                          regs_13704_320_240_4bpp,
 611                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 612                          logo_bmp_320, sizeof(logo_bmp_320));
 613 #ifdef CONFIG_VIDEO_SM501
 614         } else {
 615                 pci_dev_t devbusfn;
 616
 617                 /*
 618                  * Is SM501 connected (ppc221/ppc231)?
 619                  */
 620                 devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 621                 if (devbusfn != -1) {
 622                         puts("VGA:   SM501 with 8 MB ");
 623                         if (strcmp(str, "ppc221") == 0) {
 624                                 printf("(800*600, %dbpp)\n", BPP);
 625                                 out_be16(FPGA_BL, 0x002d); /* max. allowed brightness */
 626                         } else if (strcmp(str, "ppc231") == 0) {
 627                                 printf("(1024*768, %dbpp)\n", BPP);
 628                                 out_be16(FPGA_BL, 0x0000);
 629                         } else {
 630                                 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 631                                 return 0;
 632                         }
 633                 } else {
 634                         printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 635                         return 0;
 636                 }
 637 #endif /* CONFIG_VIDEO_SM501 */
 638         }
 639
 640         cf_enable();
 641
 642         return (0);
 643 }
 644
 645
 646 /*
 647  * Check Board Identity:
 648  */
 649
 650 int checkboard (void)
 651 {
 652         char str[64];
 653         int i = getenv_f("serial#", str, sizeof(str));
 654
 655         puts ("Board: ");
 656
 657         if (i == -1) {
 658                 puts ("### No HW ID - assuming HH405");
 659         } else {
 660                 puts(str);
 661         }
 662
 663         if (getenv_f("bd_type", str, sizeof(str)) != -1) {
 664                 printf(" (%s", str);
 665         } else {
 666                 puts(" (Missing bd_type!");
 667         }
 668
 669         gd->board_type = board_revision();
 670         printf(", Rev %ld.x)\n", gd->board_type);
 671
 672         return 0;
 673 }
 674
 675 #ifdef CONFIG_IDE_RESET
 676 void ide_set_reset(int on)
 677 {
 678         if (((gd->board_type >= 2) &&
 679              (in_be16(FPGA_STATUS) & FPGA_STATUS_CF_DETECT)) ||
 680             (gd->board_type < 2)) {
 681                 /*
 682                  * Assert or deassert CompactFlash Reset Pin
 683                  */
 684                 if (on) {               /* assert RESET */
 685                         cf_enable();
 686                         out_be16(FPGA_CTRL,
 687                                  in_be16(FPGA_CTRL) &
 688                                  ~FPGA_CTRL_CF_RESET);
 689                 } else {                /* release RESET */
 690                         out_be16(FPGA_CTRL,
 691                                  in_be16(FPGA_CTRL) |
 692                                  FPGA_CTRL_CF_RESET);
 693                 }
 694         }
 695 }
 696 #endif /* CONFIG_IDE_RESET */
 697
 698
 699 #if defined(CONFIG_SYS_EEPROM_WREN)
 700 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 701  *         <state>     -1: deliver current state
 702  *                     0: disable write
 703  *                     1: enable write
 704  *  Returns:           -1: wrong device address
 705  *                      0: dis-/en- able done
 706  *                   0/1: current state if <state> was -1.
 707  */
 708 int eeprom_write_enable (unsigned dev_addr, int state)
 709 {
 710         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 711                 return -1;
 712         } else {
 713                 switch (state) {
 714                 case 1:
 715                         /* Enable write access, clear bit GPIO_SINT2. */
 716                         out_be32((void *)GPIO0_OR,
 717                                  in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 718                         state = 0;
 719                         break;
 720                 case 0:
 721                         /* Disable write access, set bit GPIO_SINT2. */
 722                         out_be32((void *)GPIO0_OR,
 723                                  in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 724                         state = 0;
 725                         break;
 726                 default:
 727                         /* Read current status back. */
 728                         state = (0 == (in_be32((void *)GPIO0_OR) &
 729                                        CONFIG_SYS_EEPROM_WP));
 730                         break;
 731                 }
 732         }
 733         return state;
 734 }
 735
 736 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 737 {
 738         int query = argc == 1;
 739         int state = 0;
 740
 741         if (query) {
 742                 /* Query write access state. */
 743                 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 744                 if (state < 0) {
 745                         puts ("Query of write access state failed.\n");
 746                 } else {
 747                         printf ("Write access for device 0x%0x is %sabled.\n",
 748                                 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 749                         state = 0;
 750                 }
 751         } else {
 752                 if ('0' == argv[1][0]) {
 753                         /* Disable write access. */
 754                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 755                 } else {
 756                         /* Enable write access. */
 757                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 758                 }
 759                 if (state < 0) {
 760                         puts ("Setup of write access state failed.\n");
 761                 }
 762         }
 763
 764         return state;
 765 }
 766
 767 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 768         "Enable / disable / query EEPROM write access",
 769         ""
 770 );
 771 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 772
 773
 774 #ifdef CONFIG_VIDEO_SM501
 775 #ifdef CONFIG_CONSOLE_EXTRA_INFO
 776 /*
 777  * Return text to be printed besides the logo.
 778  */
 779 void video_get_info_str (int line_number, char *info)
 780 {
 781         char str[64];
 782         char str2[64];
 783         int i = getenv_f("serial#", str2, sizeof(str));
 784
 785         if (line_number == 1) {
 786                 sprintf(str, " Board: ");
 787
 788                 if (i == -1) {
 789                         strcat(str, "### No HW ID - assuming HH405");
 790                 } else {
 791                         strcat(str, str2);
 792                 }
 793
 794                 if (getenv_f("bd_type", str2, sizeof(str2)) != -1) {
 795                         strcat(str, " (");
 796                         strcat(str, str2);
 797                 } else {
 798                         strcat(str, " (Missing bd_type!");
 799                 }
 800
 801                 sprintf(str2, ", Rev %ld.x)", gd->board_type);
 802                 strcat(str, str2);
 803                 strcpy(info, str);
 804         } else {
 805                 info [0] = '\0';
 806         }
 807 }
 808 #endif /* CONFIG_CONSOLE_EXTRA_INFO */
 809
 810 /*
 811  * Returns SM501 register base address. First thing called in the driver.
 812  */
 813 unsigned int board_video_init (void)
 814 {
 815         pci_dev_t devbusfn;
 816         u32 addr;
 817
 818         /*
 819          * Is SM501 connected (ppc221/ppc231)?
 820          */
 821         devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 822         if (devbusfn != -1) {
 823                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, (u32 *)&addr);
 824                 return (addr & 0xfffffffe);
 825         }
 826
 827         return 0;
 828 }
 829
 830 /*
 831  * Returns SM501 framebuffer address
 832  */
 833 unsigned int board_video_get_fb (void)
 834 {
 835         pci_dev_t devbusfn;
 836         u32 addr;
 837
 838         /*
 839          * Is SM501 connected (ppc221/ppc231)?
 840          */
 841         devbusfn = pci_find_device(PCI_VENDOR_SM, PCI_DEVICE_SM501, 0);
 842         if (devbusfn != -1) {
 843                 pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_0, (u32 *)&addr);
 844                 addr &= 0xfffffffe;
 845 #ifdef CONFIG_VIDEO_SM501_FBMEM_OFFSET
 846                 addr += CONFIG_VIDEO_SM501_FBMEM_OFFSET;
 847 #endif
 848                 return addr;
 849         }
 850
 851         return 0;
 852 }
 853
 854 /*
 855  * Called after initializing the SM501 and before clearing the screen.
 856  */
 857 void board_validate_screen (unsigned int base)
 858 {
 859 }
 860
 861 /*
 862  * Return a pointer to the initialization sequence.
 863  */
 864 const SMI_REGS *board_get_regs (void)
 865 {
 866         char *str;
 867
 868         str = getenv("bd_type");
 869         if (strcmp(str, "ppc221") == 0) {
 870                 return init_regs_800x600;
 871         } else {
 872                 return init_regs_1024x768;
 873         }
 874 }
 875
 876 int board_get_width (void)
 877 {
 878         char *str;
 879
 880         str = getenv("bd_type");
 881         if (strcmp(str, "ppc221") == 0) {
 882                 return 800;
 883         } else {
 884                 return 1024;
 885         }
 886 }
 887
 888 int board_get_height (void)
 889 {
 890         char *str;
 891
 892         str = getenv("bd_type");
 893         if (strcmp(str, "ppc221") == 0) {
 894                 return 600;
 895         } else {
 896                 return 768;
 897         }
 898 }
 899
 900 #endif /* CONFIG_VIDEO_SM501 */
 901
 902
 903 void reset_phy(void)
 904 {
 905 #ifdef CONFIG_LXT971_NO_SLEEP
 906
 907         /*
 908          * Disable sleep mode in LXT971
 909          */
 910         lxt971_no_sleep();
 911 #endif
 912 }