2 * (C) Copyright 2009 Wolfgang Denk <wd@denx.de>
3 * (C) Copyright 2009 Dave Srl www.dave.eu
4 * (C) Copyright 2009 Stefan Roese <sr@denx.de>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 #include <asm/bitops.h>
30 #include <asm/processor.h>
31 #include <asm/mpc512x.h>
32 #include <fdt_support.h>
34 DECLARE_GLOBAL_DATA_PTR;
37 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
38 CLOCK_SCCR1_LPC_EN | \
39 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
40 CLOCK_SCCR1_PSCFIFO_EN | \
41 CLOCK_SCCR1_DDR_EN | \
42 CLOCK_SCCR1_FEC_EN | \
43 CLOCK_SCCR1_NFC_EN | \
44 CLOCK_SCCR1_PCI_EN | \
47 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
50 int eeprom_write_enable(unsigned dev_addr, int state)
52 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
54 if (dev_addr != CONFIG_SYS_I2C_EEPROM_ADDR)
58 setbits_be32(&im->gpio.gpdat, 0x00100000);
60 clrbits_be32(&im->gpio.gpdat, 0x00100000);
65 int board_early_init_f(void)
67 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
71 * Initialize Local Window for boot access
73 out_be32(&im->sysconf.lpbaw,
74 CSAW_START(0xffb00000) | CSAW_STOP(0xffb00000, 0x00010000));
75 sync_law(&im->sysconf.lpbaw);
80 out_be32(&im->clk.sccr[0], SCCR1_CLOCKS_EN);
81 out_be32(&im->clk.sccr[1], SCCR2_CLOCKS_EN);
82 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
83 setbits_be32(&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
87 * Configure MSCAN clocks
90 out_be32(&im->clk.msccr[i], 0x00300000);
91 out_be32(&im->clk.msccr[i], 0x00310000);
97 clrbits_be32(&im->gpio.gpodr, 0x000000e0);
98 clrbits_be32(&im->gpio.gpdir, 0x00ef0000);
99 setbits_be32(&im->gpio.gpdir, 0x001000e0);
100 setbits_be32(&im->gpio.gpdat, 0x00100000);
105 phys_size_t initdram(int board_type)
107 return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
110 int misc_init_r(void)
112 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
116 * Optimize access to profibus chip (VPC3) on the local bus
120 * Select 1:1 for LPC_DIV
122 val = in_be32(&im->clk.scfr[0]) & ~SCFR1_LPC_DIV_MASK;
123 out_be32(&im->clk.scfr[0], val | (0x1 << SCFR1_LPC_DIV_SHIFT));
126 * Configure LPC Chips Select Deadcycle Control Register
127 * CS0 - device can drive data 2 clock cycle(s) after CS deassertion
128 * CS1 - device can drive data 1 clock cycle(s) after CS deassertion
130 clrbits_be32(&im->lpc.cs_dccr, 0x000000ff);
131 setbits_be32(&im->lpc.cs_dccr, (0x00 << 4) | (0x01 << 0));
134 * Configure LPC Chips Select Holdcycle Control Register
135 * CS0 - data is valid 2 clock cycle(s) after CS deassertion
136 * CS1 - data is valid 1 clock cycle(s) after CS deassertion
138 clrbits_be32(&im->lpc.cs_hccr, 0x000000ff);
139 setbits_be32(&im->lpc.cs_hccr, (0x00 << 4) | (0x01 << 0));
144 static iopin_t ioregs_init[] = {
145 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
147 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
148 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
149 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
151 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
153 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
154 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
155 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
157 /* FUNC1=SELECT LPC_CS1 */
159 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
160 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
161 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
163 /* FUNC3=SELECT PSC5_2 */
165 offsetof(struct ioctrl512x, io_control_psc5_2), 1, 0,
166 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
167 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
169 /* FUNC3=SELECT PSC5_3 */
171 offsetof(struct ioctrl512x, io_control_psc5_3), 1, 0,
172 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
173 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
175 /* FUNC3=SELECT PSC7_3 */
177 offsetof(struct ioctrl512x, io_control_psc7_3), 1, 0,
178 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
179 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
181 /* FUNC3=SELECT PSC9_0 */
183 offsetof(struct ioctrl512x, io_control_psc9_0), 3, 0,
184 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
185 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
187 /* FUNC3=SELECT PSC10_0 */
189 offsetof(struct ioctrl512x, io_control_psc10_0), 3, 0,
190 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
191 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
193 /* FUNC3=SELECT PSC10_3 */
195 offsetof(struct ioctrl512x, io_control_psc10_3), 1, 0,
196 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
197 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
199 /* FUNC3=SELECT PSC11_0 */
201 offsetof(struct ioctrl512x, io_control_psc11_0), 4, 0,
202 IO_PIN_FMUX(3) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
203 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
205 /* FUNC0=SELECT IRQ0 */
207 offsetof(struct ioctrl512x, io_control_irq0), 4, 0,
208 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
209 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
213 static iopin_t rev2_silicon_pci_ioregs_init[] = {
214 /* FUNC0=PCI Sets next 54 to PCI pads */
216 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
217 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
223 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
226 puts("Board: MECP_5123\n");
229 * Initialize function mux & slew rate IO inter alia on IO
232 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
234 spridr = in_be32(&im->sysconf.spridr);
235 if (SVR_MJREV(spridr) >= 2)
236 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
241 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
242 void ft_board_setup(void *blob, bd_t *bd)
244 ft_cpu_setup(blob, bd);
246 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */