board/esd/otc570/otc570.c

   1 /*
   2  * (C) Copyright 2010
   3  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   4  * esd electronic system design gmbh <www.esd.eu>
   5  *
   6  * (C) Copyright 2007-2008
   7  * Stelian Pop <stelian.pop@leadtechdesign.com>
   8  * Lead Tech Design <www.leadtechdesign.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <asm/arch/at91sam9263.h>
  31 #include <asm/arch/at91sam9_matrix.h>
  32 #include <asm/arch/at91sam9_smc.h>
  33 #include <asm/arch/at91_common.h>
  34 #include <asm/arch/at91_pmc.h>
  35 #include <asm/arch/at91_rstc.h>
  36 #include <asm/arch/clk.h>
  37 #include <asm/arch/gpio.h>
  38 #include <asm/arch/hardware.h>
  39 #include <asm/arch/io.h>
  40 #include <atmel_lcdc.h>
  41 #include <lcd.h>
  42 #include <netdev.h>
  43 #ifdef CONFIG_LCD_INFO
  44 #include <nand.h>
  45 #include <version.h>
  46 #endif
  47
  48 DECLARE_GLOBAL_DATA_PTR;
  49
  50 /*
  51  * Miscelaneous platform dependent initialisations
  52  */
  53
  54 static int hw_rev = -1; /* hardware revision */
  55
  56 int get_hw_rev(void)
  57 {
  58         if (hw_rev >= 0)
  59                 return hw_rev;
  60
  61         hw_rev = at91_get_gpio_value(AT91_PIN_PB19);
  62         hw_rev |= at91_get_gpio_value(AT91_PIN_PB20) << 1;
  63         hw_rev |= at91_get_gpio_value(AT91_PIN_PB21) << 2;
  64         hw_rev |= at91_get_gpio_value(AT91_PIN_PB22) << 3;
  65
  66         if (hw_rev == 15)
  67                 hw_rev = 0;
  68
  69         return hw_rev;
  70 }
  71
  72 #ifdef CONFIG_CMD_NAND
  73 static void otc570_nand_hw_init(void)
  74 {
  75         unsigned long csa;
  76
  77         /* Enable CS3 */
  78         csa = at91_sys_read(AT91_MATRIX_EBI0CSA);
  79         at91_sys_write(AT91_MATRIX_EBI0CSA,
  80                 csa | AT91_MATRIX_EBI0_CS3A_SMC_SMARTMEDIA);
  81
  82         /* Configure SMC CS3 for NAND/SmartMedia */
  83         at91_sys_write(AT91_SMC_SETUP(3),
  84                 AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  85                 AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  86         at91_sys_write(AT91_SMC_PULSE(3),
  87                 AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  88                 AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  89         at91_sys_write(AT91_SMC_CYCLE(3),
  90                 AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  91         at91_sys_write(AT91_SMC_MODE(3),
  92                 AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  93                 AT91_SMC_EXNWMODE_DISABLE |
  94                 AT91_SMC_DBW_8 |
  95                 AT91_SMC_TDF_(2));
  96
  97         /* Configure RDY/BSY */
  98         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  99
 100         /* Enable NandFlash */
 101         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 102 }
 103 #endif /* CONFIG_CMD_NAND */
 104
 105 #ifdef CONFIG_MACB
 106 static void otc570_macb_hw_init(void)
 107 {
 108         /* Enable clock */
 109         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_EMAC);
 110         at91_macb_hw_init();
 111 }
 112 #endif
 113
 114 /*
 115  * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
 116  * controller debugging
 117  * The ET1100 is located at physical address 0x70000000
 118  * Its process memory is located at physical address 0x70001000
 119  */
 120 static void otc570_ethercat_hw_init(void)
 121 {
 122         /* Configure SMC EBI1_CS0 for EtherCAT */
 123         at91_sys_write(AT91_SMC1_SETUP(0),
 124                 AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) |
 125                 AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
 126         at91_sys_write(AT91_SMC1_PULSE(0),
 127                 AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) |
 128                 AT91_SMC_NRDPULSE_(5) | AT91_SMC_NCS_RDPULSE_(9));
 129         at91_sys_write(AT91_SMC1_CYCLE(0),
 130                 AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(6));
 131         /*
 132          * Configure behavior at external wait signal, byte-select mode, 16 bit
 133          * data bus width, none data float wait states and TDF optimization
 134          */
 135         at91_sys_write(AT91_SMC1_MODE(0),
 136                 AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY |
 137                 AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) |
 138                 AT91_SMC_TDFMODE);
 139
 140         /* Configure RDY/BSY */
 141         at91_set_B_periph(AT91_PIN_PE20, 0);    /* EBI1_NWAIT */
 142 }
 143
 144 #ifdef CONFIG_LCD
 145 /* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
 146 vidinfo_t panel_info = {
 147         .vl_col =               640,
 148         .vl_row =               480,
 149         .vl_clk =               25175000,
 150         .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
 151                                 ATMEL_LCDC_INVFRAME_INVERTED,
 152
 153         .vl_bpix =              3,      /* Bits per pixel, 0 = 1bit, 3 = 8bit */
 154         .vl_tft =               1,      /* 0 = passive, 1 = TFT */
 155         .vl_vsync_len =         1,      /* Length of vertical sync in NOL */
 156         .vl_upper_margin =      35,     /* Idle lines at the frame start */
 157         .vl_lower_margin =      5,      /* Idle lines at the end of the frame */
 158         .vl_hsync_len =         5,      /* Width of the LCDHSYNC pulse */
 159         .vl_left_margin =       112,    /* Idle cycles at the line beginning */
 160         .vl_right_margin =      1,      /* Idle cycles at the end of the line */
 161
 162         .mmio =                 AT91SAM9263_LCDC_BASE,
 163 };
 164
 165 void lcd_enable(void)
 166 {
 167         at91_set_gpio_value(AT91_PIN_PA30, 0);  /* power up */
 168 }
 169
 170 void lcd_disable(void)
 171 {
 172         at91_set_gpio_value(AT91_PIN_PA30, 1);  /* power down */
 173 }
 174
 175 static void otc570_lcd_hw_init(void)
 176 {
 177         at91_set_A_periph(AT91_PIN_PC0, 0);     /* LCDVSYNC */
 178         at91_set_A_periph(AT91_PIN_PC1, 0);     /* LCDHSYNC */
 179         at91_set_A_periph(AT91_PIN_PC2, 0);     /* LCDDOTCK */
 180         at91_set_A_periph(AT91_PIN_PC3, 0);     /* LCDDEN */
 181         at91_set_B_periph(AT91_PIN_PB9, 0);     /* LCDCC */
 182         at91_set_A_periph(AT91_PIN_PC6, 0);     /* LCDD2 */
 183         at91_set_A_periph(AT91_PIN_PC7, 0);     /* LCDD3 */
 184         at91_set_A_periph(AT91_PIN_PC8, 0);     /* LCDD4 */
 185         at91_set_A_periph(AT91_PIN_PC9, 0);     /* LCDD5 */
 186         at91_set_A_periph(AT91_PIN_PC10, 0);    /* LCDD6 */
 187         at91_set_A_periph(AT91_PIN_PC11, 0);    /* LCDD7 */
 188         at91_set_A_periph(AT91_PIN_PC14, 0);    /* LCDD10 */
 189         at91_set_A_periph(AT91_PIN_PC15, 0);    /* LCDD11 */
 190         at91_set_A_periph(AT91_PIN_PC16, 0);    /* LCDD12 */
 191         at91_set_B_periph(AT91_PIN_PC12, 0);    /* LCDD13 */
 192         at91_set_A_periph(AT91_PIN_PC18, 0);    /* LCDD14 */
 193         at91_set_A_periph(AT91_PIN_PC19, 0);    /* LCDD15 */
 194         at91_set_A_periph(AT91_PIN_PC22, 0);    /* LCDD18 */
 195         at91_set_A_periph(AT91_PIN_PC23, 0);    /* LCDD19 */
 196         at91_set_A_periph(AT91_PIN_PC24, 0);    /* LCDD20 */
 197         at91_set_B_periph(AT91_PIN_PC17, 0);    /* LCDD21 */
 198         at91_set_A_periph(AT91_PIN_PC26, 0);    /* LCDD22 */
 199         at91_set_A_periph(AT91_PIN_PC27, 0);    /* LCDD23 */
 200         at91_set_gpio_output(AT91_PIN_PA30, 1); /* PCI */
 201
 202         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_LCDC);
 203
 204         gd->fb_base = CONFIG_OTC570_LCD_BASE;
 205 }
 206
 207 #ifdef CONFIG_LCD_INFO
 208 void lcd_show_board_info(void)
 209 {
 210         ulong dram_size, nand_size;
 211         int i;
 212         char temp[32];
 213
 214         dram_size = 0;
 215         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 216                 dram_size += gd->bd->bi_dram[i].size;
 217         nand_size = 0;
 218         for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 219                 nand_size += nand_info[i].size;
 220
 221         lcd_printf("\n%s\n", U_BOOT_VERSION);
 222         lcd_printf("%s CPU at %s MHz\n", AT91_CPU_NAME,
 223                                         strmhz(temp, get_cpu_clk_rate()));
 224         lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 225                 dram_size >> 20,
 226                 nand_size >> 20 );
 227         lcd_printf("  Board            : esd ARM9 HMI Panel - OTC570\n");
 228         lcd_printf("  Hardware-revision: 1.%d\n", get_hw_rev());
 229         lcd_printf("  Mach-type        : %lu\n", gd->bd->bi_arch_number);
 230 }
 231 #endif /* CONFIG_LCD_INFO */
 232 #endif /* CONFIG_LCD */
 233
 234 int dram_init(void)
 235 {
 236         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 237         gd->bd->bi_dram[0].size = get_ram_size((long *) PHYS_SDRAM, (1 << 27));
 238         return 0;
 239 }
 240
 241 int board_eth_init(bd_t *bis)
 242 {
 243         int rc = 0;
 244 #ifdef CONFIG_MACB
 245         rc = macb_eth_initialize(0, (void *)AT91SAM9263_BASE_EMAC, 0x00);
 246 #endif
 247         return rc;
 248 }
 249
 250 int checkboard(void)
 251 {
 252         char str[32];
 253
 254         puts("Board: esd ARM9 HMI Panel - OTC570");
 255         if (getenv_r("serial#", str, sizeof(str)) > 0) {
 256                 puts(", serial# ");
 257                 puts(str);
 258         }
 259         printf("\nHardware-revision: 1.%d\n", get_hw_rev());
 260         printf("Mach-type: %lu\n", gd->bd->bi_arch_number);
 261         return 0;
 262 }
 263
 264 #ifdef CONFIG_SERIAL_TAG
 265 void get_board_serial(struct tag_serialnr *serialnr)
 266 {
 267         char *str;
 268
 269         char *serial = getenv("serial#");
 270         if (serial) {
 271                 str = strchr(serial, '_');
 272                 if (str && (strlen(str) >= 4)) {
 273                         serialnr->high = (*(str + 1) << 8) | *(str + 2);
 274                         serialnr->low = simple_strtoul(str + 3, NULL, 16);
 275                 }
 276         } else {
 277                 serialnr->high = 0;
 278                 serialnr->low = 0;
 279         }
 280 }
 281 #endif
 282
 283 #ifdef CONFIG_REVISION_TAG
 284 u32 get_board_rev(void)
 285 {
 286         return hw_rev | 0x100;
 287 }
 288 #endif
 289
 290 #ifdef CONFIG_MISC_INIT_R
 291 int misc_init_r(void)
 292 {
 293         char str[64];
 294
 295         at91_set_gpio_output(AT91_PIN_PA29, 1);
 296         at91_set_A_periph(AT91_PIN_PA26, 1);                    /* TXD0 */
 297         at91_set_A_periph(AT91_PIN_PA27, 0);                    /* RXD0 */
 298         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9263_ID_US0);
 299         /* Set USART_MODE = 1 (RS485) */
 300         at91_sys_write((0xFFF8C004 - AT91_BASE_SYS), 1);
 301
 302         printf("USART0: ");
 303
 304         if (getenv_r("usart0", str, sizeof(str)) == -1) {
 305                 printf("No entry - assuming 1-wire\n");
 306                 /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
 307                 at91_set_gpio_output(AT91_PIN_PA29, 0);
 308         } else {
 309                 if (strcmp(str, "1-wire") == 0) {
 310                         printf("%s\n", str);
 311                         at91_set_gpio_output(AT91_PIN_PA29, 0);
 312                 } else if (strcmp(str, "rs485") == 0) {
 313                         printf("%s\n", str);
 314                         at91_set_gpio_output(AT91_PIN_PA29, 1);
 315                 } else {
 316                         printf("Wrong entry - assuming 1-wire ");
 317                         printf("(valid values are '1-wire' or 'rs485')\n");
 318                         at91_set_gpio_output(AT91_PIN_PA29, 0);
 319                 }
 320         }
 321         printf("Display memory address: 0x%08lX\n", gd->fb_base);
 322
 323         return 0;
 324 }
 325 #endif /* CONFIG_MISC_INIT_R */
 326
 327 int board_init(void)
 328 {
 329         /* Peripheral Clock Enable Register */
 330         at91_sys_write(AT91_PMC_PCER,   1 << AT91SAM9263_ID_PIOA |
 331                                         1 << AT91SAM9263_ID_PIOB |
 332                                         1 << AT91SAM9263_ID_PIOCDE |
 333                                         1 << AT91SAM9263_ID_TWI |
 334                                         1 << AT91SAM9263_ID_SPI0 |
 335                                         1 << AT91SAM9263_ID_LCDC |
 336                                         1 << AT91SAM9263_ID_UHP);
 337
 338         /* arch number of OTC570-Board */
 339         gd->bd->bi_arch_number = MACH_TYPE_OTC570;
 340
 341         /* adress of boot parameters */
 342         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 343
 344         at91_serial_hw_init();
 345 #ifdef CONFIG_CMD_NAND
 346         otc570_nand_hw_init();
 347 #endif
 348         otc570_ethercat_hw_init();
 349 #ifdef CONFIG_HAS_DATAFLASH
 350         at91_spi0_hw_init(1 << 0);
 351 #endif
 352 #ifdef CONFIG_MACB
 353         otc570_macb_hw_init();
 354 #endif
 355 #ifdef CONFIG_AT91_CAN
 356         at91_can_hw_init();
 357 #endif
 358 #ifdef CONFIG_USB_OHCI_NEW
 359         at91_uhp_hw_init();
 360 #endif
 361 #ifdef CONFIG_LCD
 362         otc570_lcd_hw_init();
 363 #endif
 364         return 0;
 365 }