board/esd/voh405/voh405.c

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <asm/io.h>
  10 #include <asm/processor.h>
  11 #include <command.h>
  12 #include <malloc.h>
  13
  14 /* ------------------------------------------------------------------------- */
  15
  16 #if 0
  17 #define FPGA_DEBUG
  18 #endif
  19
  20 extern void lxt971_no_sleep(void);
  21
  22 /* fpga configuration data - gzip compressed and generated by bin2c */
  23 const unsigned char fpgadata[] =
  24 {
  25 #include "fpgadata.c"
  26 };
  27
  28 /*
  29  * include common fpga code (for esd boards)
  30  */
  31 #include "../common/fpga.c"
  32
  33
  34 /* logo bitmap data - gzip compressed and generated by bin2c */
  35 unsigned char logo_bmp_320[] =
  36 {
  37 #include "logo_320_240_4bpp.c"
  38 };
  39
  40 unsigned char logo_bmp_640[] =
  41 {
  42 #include "logo_640_480_24bpp.c"
  43 };
  44
  45
  46 /*
  47  * include common lcd code (for esd boards)
  48  */
  49 #include "../common/lcd.c"
  50
  51 #include "../common/s1d13704_320_240_4bpp.h"
  52 #include "../common/s1d13806_320_240_4bpp.h"
  53 #include "../common/s1d13806_640_480_16bpp.h"
  54
  55
  56 int board_early_init_f (void)
  57 {
  58         /*
  59          * IRQ 0-15  405GP internally generated; active high; level sensitive
  60          * IRQ 16    405GP internally generated; active low; level sensitive
  61          * IRQ 17-24 RESERVED
  62          * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
  63          * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
  64          * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
  65          * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
  66          * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
  67          * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
  68          * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
  69          */
  70         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  71         mtdcr(UIC0ER, 0x00000000);       /* disable all ints */
  72         mtdcr(UIC0CR, 0x00000000);       /* set all to be non-critical*/
  73         mtdcr(UIC0PR, 0xFFFFFFB5);       /* set int polarities */
  74         mtdcr(UIC0TR, 0x10000000);       /* set int trigger levels */
  75         mtdcr(UIC0VCR, 0x00000001);      /* set vect base=0,INT0 highest priority*/
  76         mtdcr(UIC0SR, 0xFFFFFFFF);       /* clear all ints */
  77
  78         /*
  79          * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
  80          */
  81         mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
  82
  83         return 0;
  84 }
  85
  86 int misc_init_r (void)
  87 {
  88         unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
  89         unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
  90         unsigned short *lcd_contrast =
  91                 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
  92         unsigned short *lcd_backlight =
  93                 (unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
  94         unsigned char *dst;
  95         ulong len = sizeof(fpgadata);
  96         int status;
  97         int index;
  98         int i;
  99         char *str;
 100
 101         dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
 102         if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 103                 printf ("GUNZIP ERROR - must RESET board to recover\n");
 104                 do_reset (NULL, 0, 0, NULL);
 105         }
 106
 107         status = fpga_boot(dst, len);
 108         if (status != 0) {
 109                 printf("\nFPGA: Booting failed ");
 110                 switch (status) {
 111                 case ERROR_FPGA_PRG_INIT_LOW:
 112                         printf("(Timeout: INIT not low after asserting PROGRAM*)\n ");
 113                         break;
 114                 case ERROR_FPGA_PRG_INIT_HIGH:
 115                         printf("(Timeout: INIT not high after deasserting PROGRAM*)\n ");
 116                         break;
 117                 case ERROR_FPGA_PRG_DONE:
 118                         printf("(Timeout: DONE not high after programming FPGA)\n ");
 119                         break;
 120                 }
 121
 122                 /* display infos on fpgaimage */
 123                 index = 15;
 124                 for (i=0; i<4; i++) {
 125                         len = dst[index];
 126                         printf("FPGA: %s\n", &(dst[index+1]));
 127                         index += len+3;
 128                 }
 129                 putc ('\n');
 130                 /* delayed reboot */
 131                 for (i=20; i>0; i--) {
 132                         printf("Rebooting in %2d seconds \r",i);
 133                         for (index=0;index<1000;index++)
 134                                 udelay(1000);
 135                 }
 136                 putc ('\n');
 137                 do_reset(NULL, 0, 0, NULL);
 138         }
 139
 140         puts("FPGA:  ");
 141
 142         /* display infos on fpgaimage */
 143         index = 15;
 144         for (i=0; i<4; i++) {
 145                 len = dst[index];
 146                 printf("%s ", &(dst[index+1]));
 147                 index += len+3;
 148         }
 149         putc ('\n');
 150
 151         free(dst);
 152
 153         /*
 154          * Reset FPGA via FPGA_INIT pin
 155          */
 156         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | FPGA_INIT); /* setup FPGA_INIT as output */
 157         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~FPGA_INIT);  /* reset low */
 158         udelay(1000); /* wait 1ms */
 159         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | FPGA_INIT);   /* reset high */
 160         udelay(1000); /* wait 1ms */
 161
 162         /*
 163          * Reset external DUARTs
 164          */
 165         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
 166         udelay(10); /* wait 10us */
 167         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
 168         udelay(1000); /* wait 1ms */
 169
 170         /*
 171          * Set NAND-FLASH GPIO signals to default
 172          */
 173         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
 174         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 175
 176         /*
 177          * Setup EEPROM write protection
 178          */
 179         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 180         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 181
 182         /*
 183          * Enable interrupts in exar duart mcr[3]
 184          */
 185         out_8(duart0_mcr, 0x08);
 186         out_8(duart1_mcr, 0x08);
 187
 188         /*
 189          * Init lcd interface and display logo
 190          */
 191         str = getenv("bd_type");
 192         if (strcmp(str, "voh405_bw") == 0) {
 193                 lcd_setup(0, 1);
 194                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 195                          regs_13704_320_240_4bpp,
 196                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 197                          logo_bmp_320, sizeof(logo_bmp_320));
 198         } else if (strcmp(str, "voh405_bwbw") == 0) {
 199                 lcd_setup(0, 1);
 200                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 201                          regs_13704_320_240_4bpp,
 202                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 203                          logo_bmp_320, sizeof(logo_bmp_320));
 204                 lcd_setup(1, 1);
 205                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 206                          regs_13806_320_240_4bpp,
 207                          sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
 208                          logo_bmp_320, sizeof(logo_bmp_320));
 209         } else if (strcmp(str, "voh405_bwc") == 0) {
 210                 lcd_setup(0, 1);
 211                 lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 212                          regs_13704_320_240_4bpp,
 213                          sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 214                          logo_bmp_320, sizeof(logo_bmp_320));
 215                 lcd_setup(1, 0);
 216                 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 217                          regs_13806_640_480_16bpp,
 218                          sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 219                          logo_bmp_640, sizeof(logo_bmp_640));
 220         } else {
 221                 printf("Unsupported bd_type defined (%s) -> No display configured!\n", str);
 222                 return 0;
 223         }
 224
 225         /*
 226          * Set invert bit in small lcd controller
 227          */
 228         out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
 229               in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
 230
 231         /*
 232          * Set default contrast voltage on epson vga controller
 233          */
 234         out_be16(lcd_contrast, 0x4646);
 235
 236         /*
 237          * Enable backlight
 238          */
 239         out_be16(lcd_backlight, 0xffff);
 240
 241         /*
 242          * Enable external I2C bus
 243          */
 244         out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
 245
 246         return (0);
 247 }
 248
 249
 250 /*
 251  * Check Board Identity:
 252  */
 253
 254 int checkboard (void)
 255 {
 256         char str[64];
 257         int i = getenv_f("serial#", str, sizeof(str));
 258
 259         puts ("Board: ");
 260
 261         if (i == -1) {
 262                 puts ("### No HW ID - assuming VOH405");
 263         } else {
 264                 puts(str);
 265         }
 266
 267         if (getenv_f("bd_type", str, sizeof(str)) != -1) {
 268                 printf(" (%s)", str);
 269         } else {
 270                 puts(" (Missing bd_type!)");
 271         }
 272
 273         putc ('\n');
 274
 275         return 0;
 276 }
 277
 278 #ifdef CONFIG_IDE_RESET
 279 #define FPGA_MODE (CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL)
 280 void ide_set_reset(int on)
 281 {
 282         /*
 283          * Assert or deassert CompactFlash Reset Pin
 284          */
 285         if (on) {               /* assert RESET */
 286                 out_be16((void *)FPGA_MODE,
 287                          in_be16((void *)FPGA_MODE) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 288         } else {                /* release RESET */
 289                 out_be16((void *)FPGA_MODE,
 290                          in_be16((void *)FPGA_MODE) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
 291         }
 292 }
 293 #endif /* CONFIG_IDE_RESET */
 294
 295 #if defined(CONFIG_RESET_PHY_R)
 296 void reset_phy(void)
 297 {
 298 #ifdef CONFIG_LXT971_NO_SLEEP
 299
 300         /*
 301          * Disable sleep mode in LXT971
 302          */
 303         lxt971_no_sleep();
 304 #endif
 305 }
 306 #endif
 307
 308 #if defined(CONFIG_SYS_EEPROM_WREN)
 309 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
 310  *         <state>     -1: deliver current state
 311  *                     0: disable write
 312  *                     1: enable write
 313  *  Returns:           -1: wrong device address
 314  *                      0: dis-/en- able done
 315  *                   0/1: current state if <state> was -1.
 316  */
 317 int eeprom_write_enable (unsigned dev_addr, int state)
 318 {
 319         if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 320                 return -1;
 321         } else {
 322                 switch (state) {
 323                 case 1:
 324                         /* Enable write access, clear bit GPIO0. */
 325                         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 326                         state = 0;
 327                         break;
 328                 case 0:
 329                         /* Disable write access, set bit GPIO0. */
 330                         out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 331                         state = 0;
 332                         break;
 333                 default:
 334                         /* Read current status back. */
 335                         state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 336                         break;
 337                 }
 338         }
 339         return state;
 340 }
 341
 342 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 343 {
 344         int query = argc == 1;
 345         int state = 0;
 346
 347         if (query) {
 348                 /* Query write access state. */
 349                 state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 350                 if (state < 0) {
 351                         puts ("Query of write access state failed.\n");
 352                 } else {
 353                         printf ("Write access for device 0x%0x is %sabled.\n",
 354                                 CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 355                         state = 0;
 356                 }
 357         } else {
 358                 if ('0' == argv[1][0]) {
 359                         /* Disable write access. */
 360                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 361                 } else {
 362                         /* Enable write access. */
 363                         state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 364                 }
 365                 if (state < 0) {
 366                         puts ("Setup of write access state failed.\n");
 367                 }
 368         }
 369
 370         return state;
 371 }
 372
 373 U_BOOT_CMD(eepwren,     2,      0,      do_eep_wren,
 374         "Enable / disable / query EEPROM write access",
 375         ""
 376 );
 377 #endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */