board/etin/kvme080/multiverse.h

   1 /*
   2  * multiverse.h
   3  *
   4  * VME driver for Multiverse
   5  *
   6  * Author : Sangmoon Kim
   7  *          dogoil@etinsys.com
   8  *
   9  * Copyright 2005 ETIN SYSTEMS Co.,Ltd.
  10  *
  11  * This program is free software; you can redistribute  it and/or modify it
  12  * under  the terms of  the GNU General Public License as published by the
  13  * Free Software Foundation;  either version 2 of the  License, or (at your
  14  * option) any later version.
  15  */
  16
  17 #ifndef __MULTIVERSE_H__
  18 #define __MULTIVERSE_H__
  19
  20 #define VME_A32_MSTR_BUS        0x90000000
  21 #define VME_A32_MSTR_SIZE       0x01000000
  22
  23 #define VME_A32_SLV_SIZE        0x01000000
  24
  25 #define VME_A32_SLV_BUS         0x90000000
  26 #define VME_A24_SLV_BUS         0x00000000
  27 #define VME_A16_SLV_BUS         0x00000000
  28
  29 #define VME_A32_SLV_LOCAL       0x00000000
  30 #define VME_A24_SLV_LOCAL       0x00000000
  31 #define VME_A16_SLV_LOCAL       0x00000000
  32
  33 #define A32_SLV_WINDOW
  34 #undef  A24_SLV_WINDOW
  35 #undef  A16_SLV_WINDOW
  36 #undef  REG_SLV_WINDOW
  37
  38 /* PCI Registers */
  39
  40 #define P_IMG_CTRL0             0x100
  41 #define P_BA0                   0x104
  42 #define P_AM0                   0x108
  43 #define P_TA0                   0x10C
  44 #define P_IMG_CTRL1             0x110
  45 #define P_BA1                   0x114
  46 #define P_AM1                   0x118
  47 #define P_TA1                   0x11C
  48 #define P_IMG_CTRL2             0x120
  49 #define P_BA2                   0x124
  50 #define P_AM2                   0x128
  51 #define P_TA2                   0x12C
  52 #define P_IMG_CTRL3             0x130
  53 #define P_BA3                   0x134
  54 #define P_AM3                   0x138
  55 #define P_TA3                   0x13C
  56 #define P_IMG_CTRL4             0x140
  57 #define P_BA4                   0x144
  58 #define P_AM4                   0x148
  59 #define P_TA4                   0x14C
  60 #define P_IMG_CTRL5             0x150
  61 #define P_BA5                   0x154
  62 #define P_AM5                   0x158
  63 #define P_TA5                   0x15C
  64 #define P_ERR_CS                0x160
  65 #define P_ERR_ADDR              0x164
  66 #define P_ERR_DATA              0x168
  67
  68 #define WB_CONF_SPC_BAR         0x180
  69 #define W_IMG_CTRL1             0x184
  70 #define W_BA1                   0x188
  71 #define W_AM1                   0x18C
  72 #define W_TA1                   0x190
  73 #define W_IMG_CTRL2             0x194
  74 #define W_BA2                   0x198
  75 #define W_AM2                   0x19C
  76 #define W_TA2                   0x1A0
  77 #define W_IMG_CTRL3             0x1A4
  78 #define W_BA3                   0x1A8
  79 #define W_AM3                   0x1AC
  80 #define W_TA3                   0x1B0
  81 #define W_IMG_CTRL4             0x1B4
  82 #define W_BA4                   0x1B8
  83 #define W_AM4                   0x1BC
  84 #define W_TA4                   0x1C0
  85 #define W_IMG_CTRL5             0x1C4
  86 #define W_BA5                   0x1C8
  87 #define W_AM5                   0x1CC
  88 #define W_TA5                   0x1D0
  89 #define W_ERR_CS                0x1D4
  90 #define W_ERR_ADDR              0x1D8
  91 #define W_ERR_DATA              0x1DC
  92 #define CNF_ADDR                0x1E0
  93 #define CNF_DATA                0x1E4
  94 #define INT_ACK                 0x1E8
  95 #define ICR                     0x1EC
  96 #define ISR                     0x1F0
  97
  98 /* VME registers */
  99
 100 #define VME_SLAVE32_AM          0x03
 101 #define VME_SLAVE24_AM          0x02
 102 #define VME_SLAVE16_AM          0x01
 103 #define VME_SLAVE_REG_AM        0x00
 104 #define VME_SLAVE32_A           0x07
 105 #define VME_SLAVE24_A           0x06
 106 #define VME_SLAVE16_A           0x05
 107 #define VME_SLAVE_REG_A         0x04
 108 #define VME_SLAVE32_MASK        0x0B
 109 #define VME_SLAVE24_MASK        0x0A
 110 #define VME_SLAVE16_MASK        0x09
 111 #define VME_SLAVE_REG_MASK      0x08
 112 #define VME_SLAVE32_EN          0x0F
 113 #define VME_SLAVE24_EN          0x0E
 114 #define VME_SLAVE16_EN          0x0D
 115 #define VME_SLAVE_REG_EN        0x0C
 116 #define VME_MASTER32_AM         0x13
 117 #define VME_MASTER24_AM         0x12
 118 #define VME_MASTER16_AM         0x11
 119 #define VME_MASTER_REG_AM       0x10
 120 #define VME_RMW_ADRS            0x14
 121 #define VME_MBOX                0x18
 122 #define VME_STATUS              0x1E
 123 #define VME_CTRL                0x1C
 124 #define VME_IRQ                 0x20
 125 #define VME_INT_EN              0x21
 126 #define VME_INT                 0x22
 127 #define VME_IRQ1_REG            0x24
 128 #define VME_IRQ2_REG            0x28
 129 #define VME_IRQ3_REG            0x2C
 130 #define VME_IRQ4_REG            0x30
 131 #define VME_IRQ5_REG            0x34
 132 #define VME_IRQ6_REG            0x38
 133 #define VME_IRQ7_REG            0x3C
 134
 135 /* VME control register */
 136
 137 #define VME_CTRL_BRDRST         0x01
 138 #define VME_CTRL_SYSRST         0x02
 139 #define VME_CTRL_RMW            0x04
 140 #define VME_CTRL_SHORT_D        0x08
 141 #define VME_CTRL_SYSFAIL        0x10
 142 #define VME_CTRL_VOWN           0x20
 143 #define VME_CTRL_A16_REG_MODE   0x40
 144
 145 /* VME status register */
 146
 147 #define VME_STATUS_SYSCON       0x01
 148 #define VME_STATUS_SYSFAIL      0x02
 149 #define VME_STATUS_ACFAIL       0x04
 150 #define VME_STATUS_SYSRST       0x08
 151 #define VME_STATUS_VOWN         0x10
 152
 153 /* Interrupt types */
 154
 155 #define LVL1                    0x0002
 156 #define LVL2                    0x0004
 157 #define LVL3                    0x0008
 158 #define LVL4                    0x0010
 159 #define LVL5                    0x0020
 160 #define LVL6                    0x0040
 161 #define LVL7                    0x0080
 162 #define MULTIVERSE_INTI_INT     0x0100
 163 #define MULTIVERSE_WB_INT       0x0200
 164 #define MULTIVERSE_PCI_INT      0x0400
 165
 166 /* interrupt acknowledge */
 167
 168 #define VME_IACK1               0x04
 169 #define VME_IACK2               0x08
 170 #define VME_IACK3               0x0c
 171 #define VME_IACK4               0x10
 172 #define VME_IACK5               0x14
 173 #define VME_IACK6               0x18
 174 #define VME_IACK7               0x1c
 175
 176 #endif /* __MULTIVERSE_H__ */