board/eukrea/cpu9260/cpu9260.c

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Stelian Pop <stelian.pop@leadtechdesign.com>
   4  * Lead Tech Design <www.leadtechdesign.com>
   5  * Ilko Iliev <www.ronetix.at>
   6  *
   7  * (C) Copyright 2009
   8  * Eric Benard <eric@eukrea.com>
   9  *
  10  * See file CREDITS for list of people who contributed to this
  11  * project.
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License as
  15  * published by the Free Software Foundation; either version 2 of
  16  * the License, or (at your option) any later version.
  17  *
  18  * This program is distributed in the hope that it will be useful,
  19  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21  * GNU General Public License for more details.
  22  *
  23  * You should have received a copy of the GNU General Public License
  24  * along with this program; if not, write to the Free Software
  25  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26  * MA 02111-1307 USA
  27  */
  28
  29 #include <common.h>
  30 #include <asm/sizes.h>
  31 #include <asm/arch/at91sam9260.h>
  32 #include <asm/arch/at91sam9_matrix.h>
  33 #include <asm/arch/at91sam9_smc.h>
  34 #include <asm/arch/at91_common.h>
  35 #include <asm/arch/at91_pmc.h>
  36 #include <asm/arch/at91_rstc.h>
  37 #include <asm/arch/gpio.h>
  38 #include <asm/arch/io.h>
  39 #include <asm/arch/hardware.h>
  40 #if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  41 #include <net.h>
  42 #endif
  43 #include <netdev.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 /* ------------------------------------------------------------------------- */
  48 /*
  49  * Miscelaneous platform dependent initialisations
  50  */
  51
  52 #ifdef CONFIG_CMD_NAND
  53 static void cpu9260_nand_hw_init(void)
  54 {
  55         unsigned long csa;
  56
  57         /* Enable CS3 */
  58         csa = at91_sys_read(AT91_MATRIX_EBICSA);
  59         at91_sys_write(AT91_MATRIX_EBICSA,
  60                        csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  61
  62         /* Configure SMC CS3 for NAND/SmartMedia */
  63 #if defined(CONFIG_CPU9G20)
  64         at91_sys_write(AT91_SMC_SETUP(3),
  65                        AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
  66                        AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
  67         at91_sys_write(AT91_SMC_PULSE(3),
  68                        AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(4) |
  69                        AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(4));
  70         at91_sys_write(AT91_SMC_CYCLE(3),
  71                        AT91_SMC_NWECYCLE_(7) | AT91_SMC_NRDCYCLE_(7));
  72         at91_sys_write(AT91_SMC_MODE(3),
  73                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  74                        AT91_SMC_EXNWMODE_DISABLE |
  75                        AT91_SMC_DBW_8 |
  76                        AT91_SMC_TDF_(3));
  77 #elif defined(CONFIG_CPU9260)
  78         at91_sys_write(AT91_SMC_SETUP(3),
  79                        AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  80                        AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  81         at91_sys_write(AT91_SMC_PULSE(3),
  82                        AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  83                        AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  84         at91_sys_write(AT91_SMC_CYCLE(3),
  85                        AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  86         at91_sys_write(AT91_SMC_MODE(3),
  87                        AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  88                        AT91_SMC_EXNWMODE_DISABLE |
  89                        AT91_SMC_DBW_8 |
  90                        AT91_SMC_TDF_(2));
  91 #endif
  92
  93         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_PIOC);
  94
  95         /* Configure RDY/BSY */
  96         at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  97
  98         /* Enable NandFlash */
  99         at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
 100 }
 101 #endif
 102
 103 #ifdef CONFIG_MACB
 104 static void cpu9260_macb_hw_init(void)
 105 {
 106         unsigned long rstc;
 107
 108         /* Enable clock */
 109         at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_EMAC);
 110
 111         /*
 112          * Disable pull-up on:
 113          *      RXDV (PA17) => PHY normal mode (not Test mode)
 114          *      ERX0 (PA14) => PHY ADDR0
 115          *      ERX1 (PA15) => PHY ADDR1
 116          *      ERX2 (PA25) => PHY ADDR2
 117          *      ERX3 (PA26) => PHY ADDR3
 118          *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
 119          *
 120          * PHY has internal pull-down
 121          */
 122         writel(pin_to_mask(AT91_PIN_PA14) |
 123                pin_to_mask(AT91_PIN_PA15) |
 124                pin_to_mask(AT91_PIN_PA17) |
 125                pin_to_mask(AT91_PIN_PA25) |
 126                pin_to_mask(AT91_PIN_PA26) |
 127                pin_to_mask(AT91_PIN_PA28),
 128                pin_to_controller(AT91_PIN_PA0) + PIO_PUDR);
 129
 130         rstc = at91_sys_read(AT91_RSTC_MR) & AT91_RSTC_ERSTL;
 131
 132         /* Need to reset PHY -> 500ms reset */
 133         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 134                        (AT91_RSTC_ERSTL & (0x0D << 8)) |
 135                        AT91_RSTC_URSTEN);
 136
 137         at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST);
 138
 139         /* Wait for end hardware reset */
 140         while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL))
 141                 ;
 142
 143         /* Restore NRST value */
 144         at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY |
 145                        (rstc) |
 146                        AT91_RSTC_URSTEN);
 147
 148         /* Re-enable pull-up */
 149         writel(pin_to_mask(AT91_PIN_PA14) |
 150                pin_to_mask(AT91_PIN_PA15) |
 151                pin_to_mask(AT91_PIN_PA17) |
 152                pin_to_mask(AT91_PIN_PA25) |
 153                pin_to_mask(AT91_PIN_PA26) |
 154                pin_to_mask(AT91_PIN_PA28),
 155                pin_to_controller(AT91_PIN_PA0) + PIO_PUER);
 156
 157         at91_macb_hw_init();
 158 }
 159 #endif
 160
 161 int board_init(void)
 162 {
 163         /* Enable Ctrlc */
 164         console_init_f();
 165
 166         /* arch number of the board */
 167 #if defined(CONFIG_CPU9G20)
 168         gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
 169 #elif defined(CONFIG_CPU9260)
 170         gd->bd->bi_arch_number = MACH_TYPE_CPUAT9260;
 171 #endif
 172
 173         /* adress of boot parameters */
 174         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 175
 176         at91_serial_hw_init();
 177 #ifdef CONFIG_CMD_NAND
 178         cpu9260_nand_hw_init();
 179 #endif
 180 #ifdef CONFIG_MACB
 181         cpu9260_macb_hw_init();
 182 #endif
 183 #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
 184         status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
 185 #endif
 186         return 0;
 187 }
 188
 189 int dram_init(void)
 190 {
 191         gd->bd->bi_dram[0].start = PHYS_SDRAM;
 192         if (get_ram_size((long *) PHYS_SDRAM, PHYS_SDRAM_SIZE) !=
 193             PHYS_SDRAM_SIZE)
 194                 return -1;
 195
 196         gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 197         return 0;
 198 }
 199
 200 #ifdef CONFIG_RESET_PHY_R
 201 void reset_phy(void)
 202 {
 203 #ifdef CONFIG_MACB
 204         /*
 205          * Initialize ethernet HW addr prior to starting Linux,
 206          * needed for nfsroot
 207          */
 208         eth_init(gd->bd);
 209 #endif
 210 }
 211 #endif
 212
 213 int board_eth_init(bd_t *bis)
 214 {
 215         int rc = 0;
 216 #ifdef CONFIG_MACB
 217         rc = macb_eth_initialize(0, (void *)AT91SAM9260_BASE_EMAC, 0x00);
 218 #endif
 219         return rc;
 220 }