board/evb64260/eth.c

   1 /**************************************************************************
   2 Etherboot -  BOOTP/TFTP Bootstrap Program
   3 Skeleton NIC driver for Etherboot
   4 ***************************************************************************/
   5
   6 /*
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * This file is a modified version from the Galileo polled mode
  12  * network driver for the ethernet contained within the GT64260
  13  * chip. It has been modified to fit into the U-Boot framework, from
  14  * the original (etherboot) setup.  Also, additional cleanup and features
  15  * were added.
  16  *
  17  * - Josh Huber <huber@mclx.com>
  18  */
  19
  20 #include <common.h>
  21 #include <malloc.h>
  22 #include <galileo/gt64260R.h>
  23 #include <galileo/core.h>
  24 #include <asm/cache.h>
  25 #include <miiphy.h>
  26 #include <net.h>
  27 #include <netdev.h>
  28
  29 #include "eth.h"
  30 #include "eth_addrtbl.h"
  31
  32 #if defined(CONFIG_CMD_NET)
  33
  34 #define GT6426x_ETH_BUF_SIZE    1536
  35
  36 /* if you like verbose output, turn this on! */
  37 #undef DEBUG
  38
  39 /* Restart autoneg if we detect link is up on phy init. */
  40
  41 /*
  42  * The GT doc's say that after Rst is deasserted, and the PHY
  43  * reports autoneg complete, it runs through its autoneg
  44  * procedures. This doesn't seem to be the case for MII
  45  * PHY's. To work around this check for link up && autoneg
  46  * complete when initilizing the port. If they are both set,
  47  * then restart PHY autoneg. Of course, it may be something
  48  * completly different.
  49  */
  50 #ifdef CONFIG_ETHER_PORT_MII
  51 # define RESTART_AUTONEG
  52 #endif
  53
  54 /* do this if you dont want to use snooping */
  55 #define USE_SOFTWARE_CACHE_MANAGEMENT
  56
  57 #ifdef USE_SOFTWARE_CACHE_MANAGEMENT
  58 #define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
  59 #define FLUSH_AND_INVALIDATE_DCACHE(a,b) if(dcache_status()){flush_dcache_range((u32)(a),(u32)(b));}
  60 #define INVALIDATE_DCACHE(a,b)           if(dcache_status()){invalidate_dcache_range((u32)(a),(u32)(b));}
  61 #else
  62 /* bummer - w/o flush, nothing works, even with snooping - FIXME */
  63 /* #define FLUSH_DCACHE(a,b) */
  64 #define FLUSH_DCACHE(a,b)                if(dcache_status()){clean_dcache_range((u32)(a),(u32)(b));}
  65 #define FLUSH_AND_INVALIDATE_DCACHE(a,b)
  66 #define INVALIDATE_DCACHE(a,b)
  67 #endif
  68 struct eth_dev_s {
  69         eth0_tx_desc_single *eth_tx_desc;
  70         eth0_rx_desc_single *eth_rx_desc;
  71         char *eth_tx_buffer;
  72         char *eth_rx_buffer[NR];
  73         int tdn, rdn;
  74         int dev;
  75         unsigned int reg_base;
  76 };
  77
  78
  79 #ifdef CONFIG_INTEL_LXT97X
  80 /* for intel LXT972 */
  81 static const char ether_port_phy_addr[3]={0,1,2};
  82 #else
  83 static const char ether_port_phy_addr[3]={4,5,6};
  84 #endif
  85
  86 /* MII PHY access routines are common for all i/f, use gal_ent0 */
  87 #define GT6426x_MII_DEVNAME     "gal_enet0"
  88
  89 int gt6426x_miiphy_read(const char *devname, unsigned char phy,
  90                 unsigned char reg, unsigned short *val);
  91
  92 static inline unsigned short
  93 miiphy_read_ret(unsigned short phy, unsigned short reg)
  94 {
  95     unsigned short val;
  96     gt6426x_miiphy_read(GT6426x_MII_DEVNAME,phy,reg,&val);
  97     return val;
  98 }
  99
 100
 101 /**************************************************************************
 102 RESET - Reset adapter
 103 ***************************************************************************/
 104 void
 105 gt6426x_eth_reset(void *v)
 106 {
 107         /*  we should do something here...
 108         struct eth_device *wp = (struct eth_device *)v;
 109         struct eth_dev_s *p = wp->priv;
 110         */
 111
 112         printf ("RESET\n");
 113         /* put the card in its initial state */
 114 }
 115
 116 static void gt6426x_handle_SMI(struct eth_dev_s *p, unsigned int icr)
 117 {
 118 #ifdef DEBUG
 119     printf("SMI interrupt: ");
 120
 121     if(icr&0x20000000) {
 122         printf("SMI done\n");
 123     }
 124 #endif
 125
 126     if(icr&0x10000000) {
 127 #ifdef DEBUG
 128         unsigned int psr;
 129
 130         psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
 131         printf("PHY state change:\n"
 132                "  GT:%s:%s:%s:%s\n",
 133                 psr & 1 ? "100" : " 10",
 134                 psr & 8 ? " Link" : "nLink",
 135                 psr & 2 ? "FD" : "HD",
 136                 psr & 4 ? " FC" : "nFC");
 137
 138 #ifdef CONFIG_INTEL_LXT97X /* non-standard mii reg (intel lxt972a) */
 139         {
 140                 unsigned short mii_11;
 141                 mii_11 = miiphy_read_ret(ether_port_phy_addr[p->dev], 0x11);
 142
 143                 printf(" mii:%s:%s:%s:%s %s:%s %s\n",
 144                         mii_11 & (1 << 14) ? "100" : " 10",
 145                         mii_11 & (1 << 10) ? " Link" : "nLink",
 146                         mii_11 & (1 << 9) ? "FD" : "HD",
 147                         mii_11 & (1 << 4) ? " FC" : "nFC",
 148
 149                         mii_11 & (1 << 7) ? "ANc" : "ANnc",
 150                         mii_11 & (1 << 8) ? "AN" : "Manual",
 151                         ""
 152                         );
 153         }
 154 #endif /* CONFIG_INTEL_LXT97X */
 155 #endif /* DEBUG */
 156     }
 157 }
 158
 159 static int
 160 gt6426x_eth_receive(struct eth_dev_s *p,unsigned int icr)
 161 {
 162         int eth_len=0;
 163         char *eth_data;
 164
 165         eth0_rx_desc_single *rx = &p->eth_rx_desc[(p->rdn)];
 166
 167         INVALIDATE_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
 168
 169         if (rx->command_status & 0x80000000) {
 170                 return 0; /* No packet received */
 171         }
 172
 173         eth_len = (unsigned int)
 174                 (rx->buff_size_byte_count) & 0x0000ffff;
 175         eth_data = (char *) p->eth_rx_buffer[p->rdn];
 176
 177 #ifdef DEBUG
 178         if (eth_len) {
 179                 printf ("%s: Recived %d byte Packet @ 0x%p\n",
 180                         __FUNCTION__, eth_len, eth_data);
 181         }
 182 #endif
 183         /*
 184          * packet is now in:
 185          * eth0_rx_buffer[RDN_ETH0];
 186          */
 187
 188         /* let the upper layer handle the packet */
 189         NetReceive ((uchar *)eth_data, eth_len);
 190
 191         rx->buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
 192
 193
 194         /* GT96100 Owner */
 195         rx->command_status = 0x80000000;
 196
 197         FLUSH_DCACHE((unsigned int)rx,(unsigned int)(rx+1));
 198
 199         p->rdn ++;
 200         if (p->rdn == NR) {p->rdn = 0;}
 201
 202         sync();
 203
 204         /* Start Rx*/
 205         GT_REG_WRITE (ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x00000080);
 206
 207 #ifdef DEBUG
 208         {
 209             int i;
 210             for (i=0;i<12;i++) {
 211                 printf(" %02x", eth_data[i]);
 212             }
 213         }
 214         printf(": %d bytes\n", eth_len);
 215 #endif
 216         INVALIDATE_DCACHE((unsigned int)eth_data,
 217                 (unsigned int)eth_data+eth_len);
 218         return eth_len;
 219 }
 220
 221 /**************************************************************************
 222 POLL - look for an rx frame, handle other conditions
 223 ***************************************************************************/
 224 int
 225 gt6426x_eth_poll(void *v)
 226 {
 227         struct eth_device *wp = (struct eth_device *)v;
 228         struct eth_dev_s *p = wp->priv;
 229         unsigned int icr=GTREGREAD(ETHERNET0_INTERRUPT_CAUSE_REGISTER + p->reg_base);
 230
 231         if(icr) {
 232             GT_REG_WRITE(ETHERNET0_INTERRUPT_CAUSE_REGISTER +p->reg_base, 0);
 233 #ifdef DEBUG
 234             printf("poll got ICR %08x\n", icr);
 235 #endif
 236             /* SMI done or PHY state change*/
 237             if(icr&0x30000000) gt6426x_handle_SMI(p, icr);
 238         }
 239         /* always process. We aren't using RX interrupts */
 240         return gt6426x_eth_receive(p, icr);
 241 }
 242
 243 /**************************************************************************
 244 TRANSMIT - Transmit a frame
 245 ***************************************************************************/
 246 int gt6426x_eth_transmit(void *v, char *p, unsigned int s)
 247 {
 248         struct eth_device *wp = (struct eth_device *)v;
 249         struct eth_dev_s *dev = (struct eth_dev_s *)wp->priv;
 250 #ifdef DEBUG
 251         unsigned int old_command_stat,old_psr;
 252 #endif
 253         eth0_tx_desc_single *tx = &dev->eth_tx_desc[dev->tdn];
 254
 255         /* wait for tx to be ready */
 256         INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
 257         while (tx->command_status & 0x80000000) {
 258             int i;
 259             for(i=0;i<1000;i++);
 260                         INVALIDATE_DCACHE((unsigned int)tx,(unsigned int)(tx+1));
 261         }
 262
 263         GT_REG_WRITE (ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + dev->reg_base,
 264                       (unsigned int)tx);
 265
 266 #ifdef DEBUG
 267         printf("copying to tx_buffer [%p], length %x, desc = %p\n",
 268                dev->eth_tx_buffer, s, dev->eth_tx_desc);
 269 #endif
 270         memcpy(dev->eth_tx_buffer, (char *) p, s);
 271
 272         tx->buff_pointer = (uchar *)dev->eth_tx_buffer;
 273         tx->bytecount_reserved = ((__u16)s) << 16;
 274
 275         /*    31 - own
 276          *    22 - gencrc
 277          * 18:16 - pad, last, first */
 278         tx->command_status = (1<<31) | (1<<22) | (7<<16);
 279 #if 0
 280         /* FEr #18 */
 281         tx->next_desc = NULL;
 282 #else
 283         tx->next_desc =
 284                 (struct eth0_tx_desc_struct *)
 285                 &dev->eth_tx_desc[(dev->tdn+1)%NT].bytecount_reserved;
 286
 287         /* cpu owned */
 288         dev->eth_tx_desc[(dev->tdn+1)%NT].command_status = (7<<16);     /* pad, last, first */
 289 #endif
 290
 291 #ifdef DEBUG
 292         old_command_stat=tx->command_status,
 293         old_psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
 294 #endif
 295
 296         FLUSH_DCACHE((unsigned int)tx,
 297                 (unsigned int)&dev->eth_tx_desc[(dev->tdn+2)%NT]);
 298
 299         FLUSH_DCACHE((unsigned int)dev->eth_tx_buffer,(unsigned int)dev->eth_tx_buffer+s);
 300
 301         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + dev->reg_base, 0x01000000);
 302
 303 #ifdef DEBUG
 304         {
 305             unsigned int command_stat=0;
 306             printf("cmd_stat: %08x PSR: %08x\n", old_command_stat, old_psr);
 307             /* wait for tx to be ready */
 308             do {
 309                 unsigned int psr=GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + dev->reg_base);
 310                 command_stat=tx->command_status;
 311                 if(command_stat!=old_command_stat || psr !=old_psr) {
 312                     printf("cmd_stat: %08x PSR: %08x\n", command_stat, psr);
 313                     old_command_stat = command_stat;
 314                     old_psr = psr;
 315                 }
 316                 /* gt6426x_eth0_poll(); */
 317             } while (command_stat & 0x80000000);
 318
 319             printf("sent %d byte frame\n", s);
 320
 321             if((command_stat & (3<<15)) == 3) {
 322                 printf("frame had error (stat=%08x)\n", command_stat);
 323             }
 324         }
 325 #endif
 326         return 0;
 327 }
 328
 329 /**************************************************************************
 330 DISABLE - Turn off ethernet interface
 331 ***************************************************************************/
 332 void
 333 gt6426x_eth_disable(void *v)
 334 {
 335         struct eth_device *wp = (struct eth_device *)v;
 336         struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
 337
 338         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + p->reg_base, 0x80008000);
 339 }
 340
 341 /**************************************************************************
 342 MII utilities - write: write to an MII register via SMI
 343 ***************************************************************************/
 344 int
 345 gt6426x_miiphy_write(const char *devname, unsigned char phy,
 346                 unsigned char reg, unsigned short data)
 347 {
 348     unsigned int temp= (reg<<21) | (phy<<16) | data;
 349
 350     while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));  /* wait for !Busy */
 351
 352     GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
 353     return 0;
 354 }
 355
 356 /**************************************************************************
 357 MII utilities - read: read from an MII register via SMI
 358 ***************************************************************************/
 359 int
 360 gt6426x_miiphy_read(const char *devname, unsigned char phy,
 361                 unsigned char reg, unsigned short *val)
 362 {
 363     unsigned int temp= (reg<<21) | (phy<<16) | 1<<26;
 364
 365     while(GTREGREAD(ETHERNET_SMI_REGISTER) & (1<<28));  /* wait for !Busy */
 366
 367     GT_REG_WRITE(ETHERNET_SMI_REGISTER, temp);
 368
 369     while(1) {
 370         temp=GTREGREAD(ETHERNET_SMI_REGISTER);
 371         if(temp & (1<<27)) break;               /* wait for ReadValid */
 372     }
 373     *val = temp & 0xffff;
 374
 375     return 0;
 376 }
 377
 378 #ifdef DEBUG
 379 /**************************************************************************
 380 MII utilities - dump mii registers
 381 ***************************************************************************/
 382 static void
 383 gt6426x_dump_mii(bd_t *bis, unsigned short phy)
 384 {
 385         printf("mii reg 0 - 3:   %04x %04x %04x %04x\n",
 386                 miiphy_read_ret(phy, 0x0),
 387                 miiphy_read_ret(phy, 0x1),
 388                 miiphy_read_ret(phy, 0x2),
 389                 miiphy_read_ret(phy, 0x3)
 390                 );
 391         printf("        4 - 7:   %04x %04x %04x %04x\n",
 392                 miiphy_read_ret(phy, 0x4),
 393                 miiphy_read_ret(phy, 0x5),
 394                 miiphy_read_ret(phy, 0x6),
 395                 miiphy_read_ret(phy, 0x7)
 396                 );
 397         printf("        8:       %04x\n",
 398                 miiphy_read_ret(phy, 0x8)
 399                 );
 400         printf("        16-19:   %04x %04x %04x %04x\n",
 401                 miiphy_read_ret(phy, 0x10),
 402                 miiphy_read_ret(phy, 0x11),
 403                 miiphy_read_ret(phy, 0x12),
 404                 miiphy_read_ret(phy, 0x13)
 405                 );
 406         printf("        20,30:   %04x %04x\n",
 407                 miiphy_read_ret(phy, 20),
 408                 miiphy_read_ret(phy, 30)
 409                 );
 410 }
 411 #endif
 412
 413 #ifdef RESTART_AUTONEG
 414
 415 /* If link is up && autoneg compleate, and if
 416  * GT and PHY disagree about link capabilitys,
 417  * restart autoneg - something screwy with FD/HD
 418  * unless we do this. */
 419 static void
 420 check_phy_state(struct eth_dev_s *p)
 421 {
 422         int bmsr = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_BMSR);
 423         int psr = GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + p->reg_base);
 424
 425         if ((psr & 1<<3) && (bmsr & BMSR_LSTATUS)) {
 426                 int nego = miiphy_read_ret(ether_port_phy_addr[p->dev], MII_ADVERTISE) &
 427                                 miiphy_read_ret(ether_port_phy_addr[p->dev], MII_LPA);
 428                 int want;
 429
 430                 if (nego & LPA_100FULL) {
 431                         want = 0x3;
 432                         printf("MII: 100Base-TX, Full Duplex\n");
 433                 } else if (nego & LPA_100HALF) {
 434                         want = 0x1;
 435                         printf("MII: 100Base-TX, Half Duplex\n");
 436                 } else if (nego & LPA_10FULL) {
 437                         want = 0x2;
 438                         printf("MII: 10Base-T, Full Duplex\n");
 439                 } else if (nego & LPA_10HALF) {
 440                         want = 0x0;
 441                         printf("MII: 10Base-T, Half Duplex\n");
 442                 } else {
 443                         printf("MII: Unknown link-foo! %x\n", nego);
 444                         return;
 445                 }
 446
 447                 if ((psr & 0x3) != want) {
 448                         printf("MII: GT thinks %x, PHY thinks %x, restarting autoneg..\n",
 449                                         psr & 0x3, want);
 450                         miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev],0,
 451                                         miiphy_read_ret(ether_port_phy_addr[p->dev],0) | (1<<9));
 452                         udelay(10000);  /* the EVB's GT takes a while to notice phy
 453                                            went down and up */
 454                 }
 455         }
 456 }
 457 #endif
 458
 459 /**************************************************************************
 460 PROBE - Look for an adapter, this routine's visible to the outside
 461 ***************************************************************************/
 462 int
 463 gt6426x_eth_probe(void *v, bd_t *bis)
 464 {
 465         struct eth_device *wp = (struct eth_device *)v;
 466         struct eth_dev_s *p = (struct eth_dev_s *)wp->priv;
 467         int dev = p->dev;
 468         unsigned int reg_base = p->reg_base;
 469         unsigned long temp;
 470         int i;
 471
 472         if (( dev < 0 ) || ( dev >= GAL_ETH_DEVS ))
 473         {       /* This should never happen */
 474                 printf("%s: Invalid device %d\n", __FUNCTION__, dev );
 475                 return 0;
 476         }
 477
 478 #ifdef DEBUG
 479         printf ("%s: initializing %s\n", __FUNCTION__, wp->name );
 480         printf ("\nCOMM_CONTROL = %08x , COMM_CONF = %08x\n",
 481                 GTREGREAD(COMM_UNIT_ARBITER_CONTROL),
 482                 GTREGREAD(COMM_UNIT_ARBITER_CONFIGURATION_REGISTER));
 483 #endif
 484
 485         /* clear MIB counters */
 486         for(i=0;i<255; i++)
 487             temp=GTREGREAD(ETHERNET0_MIB_COUNTER_BASE + reg_base +i);
 488
 489 #ifdef CONFIG_INTEL_LXT97X
 490         /* for intel LXT972 */
 491
 492         /* led 1: 0x1=txact
 493            led 2: 0xc=link/rxact
 494            led 3: 0x2=rxact (N/C)
 495            strch: 0,2=30 ms, enable */
 496         miiphy_write(GT6426x_MII_DEVNAME,ether_port_phy_addr[p->dev], 20, 0x1c22);
 497
 498         /* 2.7ns port rise time */
 499         /*miiphy_write(ether_port_phy_addr[p->dev], 30, 0x0<<10); */
 500 #else
 501         /* already set up in mpsc.c */
 502         /*GT_REG_WRITE(MAIN_ROUTING_REGISTER, 0x7ffe38);        /  b400 */
 503
 504         /* already set up in sdram_init.S... */
 505         /* MPSC0, MPSC1, RMII */
 506         /*GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, 0x1102);          /  f010 */
 507 #endif
 508         GT_REG_WRITE(ETHERNET_PHY_ADDRESS_REGISTER,
 509              ether_port_phy_addr[0]     |
 510             (ether_port_phy_addr[1]<<5) |
 511             (ether_port_phy_addr[2]<<10));                      /* 2000 */
 512
 513         /* 13:12 -   10: 4x64bit burst  (cache line size = 32 bytes)
 514          *    9  -    1: RIFB - interrupt on frame boundaries only
 515          *  6:7  -   00: big endian rx and tx
 516          *  5:2  - 1111: 15 retries */
 517         GT_REG_WRITE(ETHERNET0_SDMA_CONFIGURATION_REGISTER + reg_base,
 518                 (2<<12) | (1<<9) | (0xf<<2) );                  /* 2440 */
 519
 520 #ifndef USE_SOFTWARE_CACHE_MANAGEMENT
 521         /* enable rx/tx desc/buffer cache snoop */
 522         GT_REG_READ(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
 523                 &temp);                                         /* f200 */
 524         temp|= (1<<6)| (1<<14)| (1<<22)| (1<<30);
 525         GT_REG_WRITE(ETHERNET_0_ADDRESS_CONTROL_LOW + dev*0x20,
 526                 temp);
 527 #endif
 528
 529         /* 31  28 27  24 23  20 19  16
 530          *  0000   0000   0000   0000   [0004]
 531          * 15  12 11  8   7  4   3  0
 532          *  1000   1101   0000   0000   [4d00]
 533          *    20 - 0=MII 1=RMII
 534          *    19 - 0=speed autoneg
 535          * 15:14 - framesize 1536 (GT6426x_ETH_BUF_SIZE)
 536          *    11 - no force link pass
 537          *    10 - 1=disable fctl autoneg
 538          *     8 - override prio ?? */
 539         temp = 0x00004d00;
 540 #ifndef CONFIG_ETHER_PORT_MII
 541         temp |= (1<<20);        /* RMII */
 542 #endif
 543         /* set En */
 544         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + reg_base,
 545                      temp);                             /* 2408 */
 546
 547         /* hardcode E1 also? */
 548         /* -- according to dox, this is safer due to extra pulldowns? */
 549         if (dev<2) {
 550         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER + (dev+1) * 0x400,
 551                      temp);                             /* 2408 */
 552         }
 553
 554         /* wake up MAC */                                /* 2400 */
 555         GT_REG_READ(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, &temp);
 556         temp |= (1<<7);         /* enable port */
 557 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
 558         temp |= (1<<12);        /* hash size 1/2k */
 559 #else
 560         temp |= 1;              /* promisc */
 561 #endif
 562         GT_REG_WRITE(ETHERNET0_PORT_CONFIGURATION_REGISTER + reg_base, temp);
 563                                                         /* 2400 */
 564
 565 #ifdef RESTART_AUTONEG
 566         check_phy_state(p);
 567 #endif
 568
 569         printf("%s: Waiting for link up..\n", wp->name);
 570         temp = 10 * 1000;
 571         /* wait for link back up */
 572         while(!(GTREGREAD(ETHERNET0_PORT_STATUS_REGISTER + reg_base) & 8)
 573                         && (--temp > 0)){
 574             udelay(1000);       /* wait 1 ms */
 575         }
 576         if ( temp == 0) {
 577                 printf("%s: Failed!\n", wp->name);
 578                 return (0);
 579         }
 580
 581         printf("%s: OK!\n", wp->name);
 582
 583         p->tdn = 0;
 584         p->rdn = 0;
 585         p->eth_tx_desc[p->tdn].command_status = 0;
 586
 587         /* Initialize Rx Side */
 588         for (temp = 0; temp < NR; temp++) {
 589                 p->eth_rx_desc[temp].buff_pointer = (uchar *)p->eth_rx_buffer[temp];
 590                 p->eth_rx_desc[temp].buff_size_byte_count = GT6426x_ETH_BUF_SIZE<<16;
 591
 592                 /* GT96100 Owner */
 593                 p->eth_rx_desc[temp].command_status = 0x80000000;
 594                 p->eth_rx_desc[temp].next_desc =
 595                         (struct eth0_rx_desc_struct *)
 596                         &p->eth_rx_desc[(temp+1)%NR].buff_size_byte_count;
 597         }
 598
 599         FLUSH_DCACHE((unsigned int)&p->eth_tx_desc[0],
 600                      (unsigned int)&p->eth_tx_desc[NR]);
 601         FLUSH_DCACHE((unsigned int)&p->eth_rx_desc[0],
 602                      (unsigned int)&p->eth_rx_desc[NR]);
 603
 604         GT_REG_WRITE(ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 + reg_base,
 605                       (unsigned int) p->eth_tx_desc);
 606         GT_REG_WRITE(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base,
 607                       (unsigned int) p->eth_rx_desc);
 608         GT_REG_WRITE(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base,
 609                       (unsigned int) p->eth_rx_desc);
 610
 611 #ifdef DEBUG
 612         printf ("\nRx descriptor pointer is %08x %08x\n",
 613                 GTREGREAD(ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 + reg_base),
 614                 GTREGREAD(ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 + reg_base));
 615         printf ("\n\n%08x %08x\n",
 616                 (unsigned int)p->eth_rx_desc,p->eth_rx_desc[0].command_status);
 617
 618         printf ("Descriptor dump:\n");
 619         printf ("cmd status: %08x\n",p->eth_rx_desc[0].command_status);
 620         printf ("byte_count: %08x\n",p->eth_rx_desc[0].buff_size_byte_count);
 621         printf ("buff_ptr: %08x\n",(unsigned int)p->eth_rx_desc[0].buff_pointer);
 622         printf ("next_desc: %08x\n\n",(unsigned int)p->eth_rx_desc[0].next_desc);
 623         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x0));
 624         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x4));
 625         printf ("%08x\n",*(unsigned int *) ((unsigned int)p->eth_rx_desc + 0x8));
 626         printf ("%08x\n\n",
 627                 *(unsigned int *) ((unsigned int)p->eth_rx_desc + 0xc));
 628 #endif
 629
 630 #ifdef DEBUG
 631         gt6426x_dump_mii(bis,ether_port_phy_addr[p->dev]);
 632 #endif
 633
 634 #ifdef CONFIG_GT_USE_MAC_HASH_TABLE
 635         {
 636                 unsigned int hashtable_base;
 637             u8 *b = (u8 *)(wp->enetaddr);
 638                 u32 macH, macL;
 639
 640                 /* twist the MAC up into the way the discovery wants it */
 641                 macH= (b[0]<<8) | b[1];
 642             macL= (b[2]<<24) | (b[3]<<16) | (b[4]<<8) | b[5];
 643
 644             /* mode 0, size 0x800 */
 645             hashtable_base =initAddressTable(dev,0,1);
 646
 647             if(!hashtable_base) {
 648                         printf("initAddressTable failed\n");
 649                         return 0;
 650             }
 651
 652             addAddressTableEntry(dev, macH, macL, 1, 0);
 653             GT_REG_WRITE(ETHERNET0_HASH_TABLE_POINTER_REGISTER + reg_base,
 654                     hashtable_base);
 655         }
 656 #endif
 657
 658         /* Start Rx*/
 659         GT_REG_WRITE(ETHERNET0_SDMA_COMMAND_REGISTER + reg_base, 0x00000080);
 660         printf("%s: gt6426x eth device %d init success \n", wp->name, dev );
 661         return 1;
 662 }
 663
 664 /* enter all the galileo ethernet devs into MULTI-BOOT */
 665 void
 666 gt6426x_eth_initialize(bd_t *bis)
 667 {
 668         struct eth_device *dev;
 669         struct eth_dev_s *p;
 670         int devnum, x, temp;
 671         char *s, *e, buf[64];
 672
 673 #ifdef DEBUG
 674         printf( "\n%s\n", __FUNCTION );
 675 #endif
 676
 677         for (devnum = 0; devnum < GAL_ETH_DEVS; devnum++) {
 678                 dev = calloc(sizeof(*dev), 1);
 679                 if (!dev) {
 680                         printf( "%s: gal_enet%d allocation failure, %s\n",
 681                                         __FUNCTION__, devnum, "eth_device structure");
 682                         return;
 683                 }
 684
 685                 /* must be less than sizeof(dev->name) */
 686                 sprintf(dev->name, "gal_enet%d", devnum);
 687
 688 #ifdef DEBUG
 689                 printf( "Initializing %s\n", dev->name );
 690 #endif
 691
 692                 /* Extract the MAC address from the environment */
 693                 switch (devnum)
 694                 {
 695                         case 0: s = "ethaddr"; break;
 696 #if (GAL_ETH_DEVS > 1)
 697                         case 1: s = "eth1addr"; break;
 698 #endif
 699 #if (GAL_ETH_DEVS > 2)
 700                         case 2: s = "eth2addr"; break;
 701 #endif
 702                         default: /* this should never happen */
 703                                 printf( "%s: Invalid device number %d\n",
 704                                                 __FUNCTION__, devnum );
 705                                 return;
 706                 }
 707
 708                 temp = getenv_f(s, buf, sizeof(buf));
 709                 s = (temp > 0) ? buf : NULL;
 710
 711 #ifdef DEBUG
 712                 printf ("Setting MAC %d to %s\n", devnum, s );
 713 #endif
 714                 for (x = 0; x < 6; ++x) {
 715                         dev->enetaddr[x] = s ? simple_strtoul(s, &e, 16) : 0;
 716                         if (s)
 717                                 s = (*e) ? e+1 : e;
 718                 }
 719
 720                 dev->init = (void*)gt6426x_eth_probe;
 721                 dev->halt = (void*)gt6426x_eth_reset;
 722                 dev->send = (void*)gt6426x_eth_transmit;
 723                 dev->recv = (void*)gt6426x_eth_poll;
 724
 725                 p = calloc( sizeof(*p), 1 );
 726                 dev->priv = (void*)p;
 727                 if (!p)
 728                 {
 729                         printf( "%s: %s allocation failure, %s\n",
 730                                         __FUNCTION__, dev->name, "Private Device Structure");
 731                         free(dev);
 732                         return;
 733                 }
 734
 735                 p->dev = devnum;
 736                 p->tdn=0;
 737                 p->rdn=0;
 738                 p->reg_base = devnum * ETHERNET_PORTS_DIFFERENCE_OFFSETS;
 739
 740                 p->eth_tx_desc =
 741                         (eth0_tx_desc_single *)
 742                         (((unsigned int) malloc(sizeof (eth0_tx_desc_single) *
 743                                                 (NT+1)) & 0xfffffff0) + 0x10);
 744                 if (!p)
 745                 {
 746                         printf( "%s: %s allocation failure, %s\n",
 747                                         __FUNCTION__, dev->name, "Tx Descriptor");
 748                         free(dev);
 749                         return;
 750                 }
 751
 752                 p->eth_rx_desc =
 753                         (eth0_rx_desc_single *)
 754                         (((unsigned int) malloc(sizeof (eth0_rx_desc_single) *
 755                                                 (NR+1)) & 0xfffffff0) + 0x10);
 756                 if (!p->eth_rx_desc)
 757                 {
 758                         printf( "%s: %s allocation failure, %s\n",
 759                                         __FUNCTION__, dev->name, "Rx Descriptor");
 760                         free(dev);
 761                         free(p);
 762                         return;
 763                 }
 764
 765                 p->eth_tx_buffer =
 766                         (char *) (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
 767                 if (!p->eth_tx_buffer)
 768                 {
 769                         printf( "%s: %s allocation failure, %s\n",
 770                                         __FUNCTION__, dev->name, "Tx Bufffer");
 771                         free(dev);
 772                         free(p);
 773                         free(p->eth_rx_desc);
 774                         return;
 775                 }
 776
 777                 for (temp = 0 ; temp < NR ; temp ++) {
 778                         p->eth_rx_buffer[temp] =
 779                                 (char *)
 780                                 (((unsigned int) malloc(GT6426x_ETH_BUF_SIZE) & 0xfffffff0) + 0x10);
 781                         if (!p->eth_rx_buffer[temp])
 782                         {
 783                                 printf( "%s: %s allocation failure, %s\n",
 784                                                 __FUNCTION__, dev->name, "Rx Buffers");
 785                                 free(dev);
 786                                 free(p);
 787                                 free(p->eth_tx_buffer);
 788                                 free(p->eth_rx_desc);
 789                                 free(p->eth_tx_desc);
 790                                 while (temp >= 0)
 791                                         free(p->eth_rx_buffer[--temp]);
 792                                 return;
 793                         }
 794                 }
 795
 796
 797                 eth_register(dev);
 798 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
 799                 miiphy_register(dev->name,
 800                                 gt6426x_miiphy_read, gt6426x_miiphy_write);
 801 #endif
 802         }
 803
 804 }
 805 #endif