board/freescale/mpc8540ads/mpc8540ads.c

   1 /*
   2  * Copyright 2004 Freescale Semiconductor.
   3  * (C) Copyright 2002,2003, Motorola Inc.
   4  * Xianghua Xiao, (X.Xiao@motorola.com)
   5  *
   6  * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27
  28 #include <common.h>
  29 #include <pci.h>
  30 #include <asm/processor.h>
  31 #include <asm/mmu.h>
  32 #include <asm/immap_85xx.h>
  33 #include <asm/fsl_ddr_sdram.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36
  37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  38 extern void ddr_enable_ecc(unsigned int dram_size);
  39 #endif
  40
  41 void local_bus_init(void);
  42 void sdram_init(void);
  43 long int fixed_sdram(void);
  44
  45 int checkboard (void)
  46 {
  47         puts("Board: ADS\n");
  48
  49 #ifdef CONFIG_PCI
  50         printf("    PCI1: 32 bit, %d MHz (compiled)\n",
  51                CONFIG_SYS_CLK_FREQ / 1000000);
  52 #else
  53         printf("    PCI1: disabled\n");
  54 #endif
  55
  56         /*
  57          * Initialize local bus.
  58          */
  59         local_bus_init();
  60
  61         return 0;
  62 }
  63
  64
  65 phys_size_t
  66 initdram(int board_type)
  67 {
  68         long dram_size = 0;
  69
  70         puts("Initializing\n");
  71
  72 #if defined(CONFIG_DDR_DLL)
  73         {
  74             volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  75             uint temp_ddrdll = 0;
  76
  77             /*
  78              * Work around to stabilize DDR DLL
  79              */
  80             temp_ddrdll = gur->ddrdllcr;
  81             gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
  82             asm("sync;isync;msync");
  83         }
  84 #endif
  85
  86 #ifdef CONFIG_SPD_EEPROM
  87         dram_size = fsl_ddr_sdram();
  88         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  89
  90         dram_size *= 0x100000;
  91 #else
  92         dram_size = fixed_sdram();
  93 #endif
  94
  95 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  96         /*
  97          * Initialize and enable DDR ECC.
  98          */
  99         ddr_enable_ecc(dram_size);
 100 #endif
 101
 102         /*
 103          * Initialize SDRAM.
 104          */
 105         sdram_init();
 106
 107         puts("    DDR: ");
 108         return dram_size;
 109 }
 110
 111
 112 /*
 113  * Initialize Local Bus
 114  */
 115
 116 void
 117 local_bus_init(void)
 118 {
 119         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 120         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 121
 122         uint clkdiv;
 123         uint lbc_hz;
 124         sys_info_t sysinfo;
 125
 126         /*
 127          * Errata LBC11.
 128          * Fix Local Bus clock glitch when DLL is enabled.
 129          *
 130          * If localbus freq is < 66Mhz, DLL bypass mode must be used.
 131          * If localbus freq is > 133Mhz, DLL can be safely enabled.
 132          * Between 66 and 133, the DLL is enabled with an override workaround.
 133          */
 134
 135         get_sys_info(&sysinfo);
 136         clkdiv = lbc->lcrr & 0x0f;
 137         lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 138
 139         if (lbc_hz < 66) {
 140                 lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;   /* DLL Bypass */
 141
 142         } else if (lbc_hz >= 133) {
 143                 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 144
 145         } else {
 146                 /*
 147                  * On REV1 boards, need to change CLKDIV before enable DLL.
 148                  * Default CLKDIV is 8, change it to 4 temporarily.
 149                  */
 150                 uint pvr = get_pvr();
 151                 uint temp_lbcdll = 0;
 152
 153                 if (pvr == PVR_85xx_REV1) {
 154                         /* FIXME: Justify the high bit here. */
 155                         lbc->lcrr = 0x10000004;
 156                 }
 157
 158                 lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 159                 udelay(200);
 160
 161                 /*
 162                  * Sample LBC DLL ctrl reg, upshift it to set the
 163                  * override bits.
 164                  */
 165                 temp_lbcdll = gur->lbcdllcr;
 166                 gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 167                 asm("sync;isync;msync");
 168         }
 169 }
 170
 171
 172 /*
 173  * Initialize SDRAM memory on the Local Bus.
 174  */
 175
 176 void
 177 sdram_init(void)
 178 {
 179         volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 180         uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 181
 182         puts("    SDRAM: ");
 183         print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 184
 185         /*
 186          * Setup SDRAM Base and Option Registers
 187          */
 188         lbc->or2 = CONFIG_SYS_OR2_PRELIM;
 189         lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 190         lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 191         asm("msync");
 192
 193         lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 194         lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 195         asm("sync");
 196
 197         /*
 198          * Configure the SDRAM controller.
 199          */
 200         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 201         asm("sync");
 202         *sdram_addr = 0xff;
 203         ppcDcbf((unsigned long) sdram_addr);
 204         udelay(100);
 205
 206         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 207         asm("sync");
 208         *sdram_addr = 0xff;
 209         ppcDcbf((unsigned long) sdram_addr);
 210         udelay(100);
 211
 212         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 213         asm("sync");
 214         *sdram_addr = 0xff;
 215         ppcDcbf((unsigned long) sdram_addr);
 216         udelay(100);
 217
 218         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 219         asm("sync");
 220         *sdram_addr = 0xff;
 221         ppcDcbf((unsigned long) sdram_addr);
 222         udelay(100);
 223
 224         lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 225         asm("sync");
 226         *sdram_addr = 0xff;
 227         ppcDcbf((unsigned long) sdram_addr);
 228         udelay(100);
 229 }
 230
 231 #if !defined(CONFIG_SPD_EEPROM)
 232 /*************************************************************************
 233  *  fixed sdram init -- doesn't use serial presence detect.
 234  ************************************************************************/
 235 long int fixed_sdram (void)
 236 {
 237   #ifndef CONFIG_SYS_RAMBOOT
 238         volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 239
 240         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 241         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 242         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 243         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 244         ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
 245         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 246     #if defined (CONFIG_DDR_ECC)
 247         ddr->err_disable = 0x0000000D;
 248         ddr->err_sbe = 0x00ff0000;
 249     #endif
 250         asm("sync;isync;msync");
 251         udelay(500);
 252     #if defined (CONFIG_DDR_ECC)
 253         /* Enable ECC checking */
 254         ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 255     #else
 256         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 257     #endif
 258         asm("sync; isync; msync");
 259         udelay(500);
 260   #endif
 261         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 262 }
 263 #endif  /* !defined(CONFIG_SPD_EEPROM) */
 264
 265
 266 #if defined(CONFIG_PCI)
 267 /*
 268  * Initialize PCI Devices, report devices found.
 269  */
 270
 271
 272 static struct pci_controller hose;
 273
 274 #endif  /* CONFIG_PCI */
 275
 276
 277 void
 278 pci_init_board(void)
 279 {
 280 #ifdef CONFIG_PCI
 281         pci_mpc85xx_init(&hose);
 282 #endif /* CONFIG_PCI */
 283 }
 284
 285
 286 #if defined(CONFIG_OF_BOARD_SETUP)
 287 void
 288 ft_board_setup(void *blob, bd_t *bd)
 289 {
 290         int node, tmp[2];
 291         const char *path;
 292
 293         ft_cpu_setup(blob, bd);
 294
 295         node = fdt_path_offset(blob, "/aliases");
 296         tmp[0] = 0;
 297         if (node >= 0) {
 298 #ifdef CONFIG_PCI
 299                 path = fdt_getprop(blob, node, "pci0", NULL);
 300                 if (path) {
 301                         tmp[1] = hose.last_busno - hose.first_busno;
 302                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 303                 }
 304 #endif
 305         }
 306 }
 307 #endif