board/freescale/mpc8544ds/mpc8544ds.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/immap_85xx.h>
  29 #include <asm/immap_fsl_pci.h>
  30 #include <asm/fsl_ddr_sdram.h>
  31 #include <asm/io.h>
  32 #include <miiphy.h>
  33 #include <libfdt.h>
  34 #include <fdt_support.h>
  35
  36 #include "../common/pixis.h"
  37
  38 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  39 extern void ddr_enable_ecc(unsigned int dram_size);
  40 #endif
  41
  42 int checkboard (void)
  43 {
  44         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
  45         volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
  46         volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
  47
  48         if ((uint)&gur->porpllsr != 0xe00e0000) {
  49                 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
  50         }
  51         printf ("Board: MPC8544DS, System ID: 0x%02x, "
  52                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  53                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  54                 in8(PIXIS_BASE + PIXIS_PVER));
  55
  56         lbc->ltesr = 0xffffffff;        /* Clear LBC error interrupts */
  57         lbc->lteir = 0xffffffff;        /* Enable LBC error interrupts */
  58         ecm->eedr = 0xffffffff;         /* Clear ecm errors */
  59         ecm->eeer = 0xffffffff;         /* Enable ecm errors */
  60
  61         return 0;
  62 }
  63
  64 phys_size_t
  65 initdram(int board_type)
  66 {
  67         long dram_size = 0;
  68
  69         puts("Initializing\n");
  70
  71         dram_size = fsl_ddr_sdram();
  72
  73         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  74
  75         dram_size *= 0x100000;
  76
  77 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  78         /*
  79          * Initialize and enable DDR ECC.
  80          */
  81         ddr_enable_ecc(dram_size);
  82 #endif
  83         puts("    DDR: ");
  84         return dram_size;
  85 }
  86
  87 #ifdef CONFIG_PCI1
  88 static struct pci_controller pci1_hose;
  89 #endif
  90
  91 #ifdef CONFIG_PCIE1
  92 static struct pci_controller pcie1_hose;
  93 #endif
  94
  95 #ifdef CONFIG_PCIE2
  96 static struct pci_controller pcie2_hose;
  97 #endif
  98
  99 #ifdef CONFIG_PCIE3
 100 static struct pci_controller pcie3_hose;
 101 #endif
 102
 103 int first_free_busno=0;
 104
 105 void
 106 pci_init_board(void)
 107 {
 108         volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
 109         uint devdisr = gur->devdisr;
 110         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 111         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 112
 113         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 114                 devdisr, io_sel, host_agent);
 115
 116         if (io_sel & 1) {
 117                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 118                         printf ("    eTSEC1 is in sgmii mode.\n");
 119                 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 120                         printf ("    eTSEC3 is in sgmii mode.\n");
 121         }
 122
 123 #ifdef CONFIG_PCIE3
 124 {
 125         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
 126         extern void fsl_pci_init(struct pci_controller *hose);
 127         struct pci_controller *hose = &pcie3_hose;
 128         int pcie_ep = (host_agent == 1);
 129         int pcie_configured  = io_sel >= 1;
 130
 131         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 132                 printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 133                         pcie_ep ? "End Point" : "Root Complex",
 134                         (uint)pci);
 135                 if (pci->pme_msg_det) {
 136                         pci->pme_msg_det = 0xffffffff;
 137                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 138                 }
 139                 printf ("\n");
 140
 141                 /* inbound */
 142                 pci_set_region(hose->regions + 0,
 143                                CFG_PCI_MEMORY_BUS,
 144                                CFG_PCI_MEMORY_PHYS,
 145                                CFG_PCI_MEMORY_SIZE,
 146                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 147
 148                 /* outbound memory */
 149                 pci_set_region(hose->regions + 1,
 150                                CFG_PCIE3_MEM_BASE,
 151                                CFG_PCIE3_MEM_PHYS,
 152                                CFG_PCIE3_MEM_SIZE,
 153                                PCI_REGION_MEM);
 154
 155                 /* outbound io */
 156                 pci_set_region(hose->regions + 2,
 157                                CFG_PCIE3_IO_BASE,
 158                                CFG_PCIE3_IO_PHYS,
 159                                CFG_PCIE3_IO_SIZE,
 160                                PCI_REGION_IO);
 161
 162                 hose->region_count = 3;
 163 #ifdef CFG_PCIE3_MEM_BASE2
 164                 /* outbound memory */
 165                 pci_set_region(hose->regions + 3,
 166                                CFG_PCIE3_MEM_BASE2,
 167                                CFG_PCIE3_MEM_PHYS2,
 168                                CFG_PCIE3_MEM_SIZE2,
 169                                PCI_REGION_MEM);
 170                 hose->region_count++;
 171 #endif
 172                 hose->first_busno=first_free_busno;
 173                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 174
 175                 fsl_pci_init(hose);
 176
 177                 first_free_busno=hose->last_busno+1;
 178                 printf ("    PCIE3 on bus %02x - %02x\n",
 179                         hose->first_busno,hose->last_busno);
 180
 181                 /*
 182                  * Activate ULI1575 legacy chip by performing a fake
 183                  * memory access.  Needed to make ULI RTC work.
 184                  */
 185                 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
 186         } else {
 187                 printf ("    PCIE3: disabled\n");
 188         }
 189
 190  }
 191 #else
 192         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 193 #endif
 194
 195 #ifdef CONFIG_PCIE1
 196  {
 197         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
 198         extern void fsl_pci_init(struct pci_controller *hose);
 199         struct pci_controller *hose = &pcie1_hose;
 200         int pcie_ep = (host_agent == 5);
 201         int pcie_configured  = io_sel & 6;
 202
 203         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 204                 printf ("\n    PCIE1 connected to Slot2 as %s (base address %x)",
 205                         pcie_ep ? "End Point" : "Root Complex",
 206                         (uint)pci);
 207                 if (pci->pme_msg_det) {
 208                         pci->pme_msg_det = 0xffffffff;
 209                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 210                 }
 211                 printf ("\n");
 212
 213                 /* inbound */
 214                 pci_set_region(hose->regions + 0,
 215                                CFG_PCI_MEMORY_BUS,
 216                                CFG_PCI_MEMORY_PHYS,
 217                                CFG_PCI_MEMORY_SIZE,
 218                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 219
 220                 /* outbound memory */
 221                 pci_set_region(hose->regions + 1,
 222                                CFG_PCIE1_MEM_BASE,
 223                                CFG_PCIE1_MEM_PHYS,
 224                                CFG_PCIE1_MEM_SIZE,
 225                                PCI_REGION_MEM);
 226
 227                 /* outbound io */
 228                 pci_set_region(hose->regions + 2,
 229                                CFG_PCIE1_IO_BASE,
 230                                CFG_PCIE1_IO_PHYS,
 231                                CFG_PCIE1_IO_SIZE,
 232                                PCI_REGION_IO);
 233
 234                 hose->region_count = 3;
 235 #ifdef CFG_PCIE1_MEM_BASE2
 236                 /* outbound memory */
 237                 pci_set_region(hose->regions + 3,
 238                                CFG_PCIE1_MEM_BASE2,
 239                                CFG_PCIE1_MEM_PHYS2,
 240                                CFG_PCIE1_MEM_SIZE2,
 241                                PCI_REGION_MEM);
 242                 hose->region_count++;
 243 #endif
 244                 hose->first_busno=first_free_busno;
 245
 246                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 247
 248                 fsl_pci_init(hose);
 249
 250                 first_free_busno=hose->last_busno+1;
 251                 printf("    PCIE1 on bus %02x - %02x\n",
 252                        hose->first_busno,hose->last_busno);
 253
 254         } else {
 255                 printf ("    PCIE1: disabled\n");
 256         }
 257
 258  }
 259 #else
 260         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 261 #endif
 262
 263 #ifdef CONFIG_PCIE2
 264  {
 265         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
 266         extern void fsl_pci_init(struct pci_controller *hose);
 267         struct pci_controller *hose = &pcie2_hose;
 268         int pcie_ep = (host_agent == 3);
 269         int pcie_configured  = io_sel & 4;
 270
 271         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 272                 printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 273                         pcie_ep ? "End Point" : "Root Complex",
 274                         (uint)pci);
 275                 if (pci->pme_msg_det) {
 276                         pci->pme_msg_det = 0xffffffff;
 277                         debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 278                 }
 279                 printf ("\n");
 280
 281                 /* inbound */
 282                 pci_set_region(hose->regions + 0,
 283                                CFG_PCI_MEMORY_BUS,
 284                                CFG_PCI_MEMORY_PHYS,
 285                                CFG_PCI_MEMORY_SIZE,
 286                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 287
 288                 /* outbound memory */
 289                 pci_set_region(hose->regions + 1,
 290                                CFG_PCIE2_MEM_BASE,
 291                                CFG_PCIE2_MEM_PHYS,
 292                                CFG_PCIE2_MEM_SIZE,
 293                                PCI_REGION_MEM);
 294
 295                 /* outbound io */
 296                 pci_set_region(hose->regions + 2,
 297                                CFG_PCIE2_IO_BASE,
 298                                CFG_PCIE2_IO_PHYS,
 299                                CFG_PCIE2_IO_SIZE,
 300                                PCI_REGION_IO);
 301
 302                 hose->region_count = 3;
 303 #ifdef CFG_PCIE2_MEM_BASE2
 304                 /* outbound memory */
 305                 pci_set_region(hose->regions + 3,
 306                                CFG_PCIE2_MEM_BASE2,
 307                                CFG_PCIE2_MEM_PHYS2,
 308                                CFG_PCIE2_MEM_SIZE2,
 309                                PCI_REGION_MEM);
 310                 hose->region_count++;
 311 #endif
 312                 hose->first_busno=first_free_busno;
 313                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 314
 315                 fsl_pci_init(hose);
 316                 first_free_busno=hose->last_busno+1;
 317                 printf ("    PCIE2 on bus %02x - %02x\n",
 318                         hose->first_busno,hose->last_busno);
 319
 320         } else {
 321                 printf ("    PCIE2: disabled\n");
 322         }
 323
 324  }
 325 #else
 326         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 327 #endif
 328
 329
 330 #ifdef CONFIG_PCI1
 331 {
 332         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
 333         extern void fsl_pci_init(struct pci_controller *hose);
 334         struct pci_controller *hose = &pci1_hose;
 335
 336         uint pci_agent = (host_agent == 6);
 337         uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
 338         uint pci_32 = 1;
 339         uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;       /* PORDEVSR[14] */
 340         uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;   /* PORPLLSR[16] */
 341
 342
 343         if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
 344                 printf ("\n    PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
 345                         (pci_32) ? 32 : 64,
 346                         (pci_speed == 33333000) ? "33" :
 347                         (pci_speed == 66666000) ? "66" : "unknown",
 348                         pci_clk_sel ? "sync" : "async",
 349                         pci_agent ? "agent" : "host",
 350                         pci_arb ? "arbiter" : "external-arbiter",
 351                         (uint)pci
 352                         );
 353
 354                 /* inbound */
 355                 pci_set_region(hose->regions + 0,
 356                                CFG_PCI_MEMORY_BUS,
 357                                CFG_PCI_MEMORY_PHYS,
 358                                CFG_PCI_MEMORY_SIZE,
 359                                PCI_REGION_MEM | PCI_REGION_MEMORY);
 360
 361                 /* outbound memory */
 362                 pci_set_region(hose->regions + 1,
 363                                CFG_PCI1_MEM_BASE,
 364                                CFG_PCI1_MEM_PHYS,
 365                                CFG_PCI1_MEM_SIZE,
 366                                PCI_REGION_MEM);
 367
 368                 /* outbound io */
 369                 pci_set_region(hose->regions + 2,
 370                                CFG_PCI1_IO_BASE,
 371                                CFG_PCI1_IO_PHYS,
 372                                CFG_PCI1_IO_SIZE,
 373                                PCI_REGION_IO);
 374                 hose->region_count = 3;
 375 #ifdef CFG_PCIE3_MEM_BASE2
 376                 /* outbound memory */
 377                 pci_set_region(hose->regions + 3,
 378                                CFG_PCIE3_MEM_BASE2,
 379                                CFG_PCIE3_MEM_PHYS2,
 380                                CFG_PCIE3_MEM_SIZE2,
 381                                PCI_REGION_MEM);
 382                 hose->region_count++;
 383 #endif
 384                 hose->first_busno=first_free_busno;
 385                 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 386
 387                 fsl_pci_init(hose);
 388                 first_free_busno=hose->last_busno+1;
 389                 printf ("PCI on bus %02x - %02x\n",
 390                         hose->first_busno,hose->last_busno);
 391         } else {
 392                 printf ("    PCI: disabled\n");
 393         }
 394 }
 395 #else
 396         gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
 397 #endif
 398 }
 399
 400
 401 int last_stage_init(void)
 402 {
 403         return 0;
 404 }
 405
 406
 407 unsigned long
 408 get_board_sys_clk(ulong dummy)
 409 {
 410         u8 i, go_bit, rd_clks;
 411         ulong val = 0;
 412
 413         go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
 414         go_bit &= 0x01;
 415
 416         rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
 417         rd_clks &= 0x1C;
 418
 419         /*
 420          * Only if both go bit and the SCLK bit in VCFGEN0 are set
 421          * should we be using the AUX register. Remember, we also set the
 422          * GO bit to boot from the alternate bank on the on-board flash
 423          */
 424
 425         if (go_bit) {
 426                 if (rd_clks == 0x1c)
 427                         i = in8(PIXIS_BASE + PIXIS_AUX);
 428                 else
 429                         i = in8(PIXIS_BASE + PIXIS_SPD);
 430         } else {
 431                 i = in8(PIXIS_BASE + PIXIS_SPD);
 432         }
 433
 434         i &= 0x07;
 435
 436         switch (i) {
 437         case 0:
 438                 val = 33333333;
 439                 break;
 440         case 1:
 441                 val = 40000000;
 442                 break;
 443         case 2:
 444                 val = 50000000;
 445                 break;
 446         case 3:
 447                 val = 66666666;
 448                 break;
 449         case 4:
 450                 val = 83000000;
 451                 break;
 452         case 5:
 453                 val = 100000000;
 454                 break;
 455         case 6:
 456                 val = 133333333;
 457                 break;
 458         case 7:
 459                 val = 166666666;
 460                 break;
 461         }
 462
 463         return val;
 464 }
 465
 466 #if defined(CONFIG_OF_BOARD_SETUP)
 467
 468 void
 469 ft_board_setup(void *blob, bd_t *bd)
 470 {
 471         int node, tmp[2];
 472         const char *path;
 473
 474         ft_cpu_setup(blob, bd);
 475
 476         node = fdt_path_offset(blob, "/aliases");
 477         tmp[0] = 0;
 478         if (node >= 0) {
 479 #ifdef CONFIG_PCI1
 480                 path = fdt_getprop(blob, node, "pci0", NULL);
 481                 if (path) {
 482                         tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
 483                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 484                 }
 485 #endif
 486 #ifdef CONFIG_PCIE2
 487                 path = fdt_getprop(blob, node, "pci1", NULL);
 488                 if (path) {
 489                         tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 490                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 491                 }
 492 #endif
 493 #ifdef CONFIG_PCIE1
 494                 path = fdt_getprop(blob, node, "pci2", NULL);
 495                 if (path) {
 496                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 497                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 498                 }
 499 #endif
 500 #ifdef CONFIG_PCIE3
 501                 path = fdt_getprop(blob, node, "pci3", NULL);
 502                 if (path) {
 503                         tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
 504                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 505                 }
 506 #endif
 507         }
 508 }
 509 #endif