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mxc_ipuv3: fix memory alignment of framebuffer
[karo-tx-uboot.git] / board / freescale / mpc8544ds / tlb.c
1 /*
2  * Copyright 2008 Freescale Semiconductor, Inc.
3  *
4  * (C) Copyright 2000
5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
6  *
7  * See file CREDITS for list of people who contributed to this
8  * project.
9  *
10  * This program is free software; you can redistribute it and/or
11  * modify it under the terms of the GNU General Public License as
12  * published by the Free Software Foundation; either version 2 of
13  * the License, or (at your option) any later version.
14  *
15  * This program is distributed in the hope that it will be useful,
16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
18  * GNU General Public License for more details.
19  *
20  * You should have received a copy of the GNU General Public License
21  * along with this program; if not, write to the Free Software
22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23  * MA 02111-1307 USA
24  */
25
26 #include <common.h>
27 #include <asm/mmu.h>
28
29 struct fsl_e_tlb_entry tlb_table[] = {
30         /* TLB 0 - for temp stack in cache */
31         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
32                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
33                       0, 0, BOOKE_PAGESZ_4K, 0),
34         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
35                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
36                       0, 0, BOOKE_PAGESZ_4K, 0),
37         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
38                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
39                       0, 0, BOOKE_PAGESZ_4K, 0),
40         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
41                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
42                       0, 0, BOOKE_PAGESZ_4K, 0),
43         /*
44          * TLB 0:       64M     Non-cacheable, guarded
45          * 0xfc000000   64M     Covers FLASH at 0xFE800000 and 0xFF800000
46          * Out of reset this entry is only 4K.
47          */
48         SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
49                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
50                       0, 0, BOOKE_PAGESZ_64M, 1),
51         /*
52          * TLB 1:       1G      Non-cacheable, guarded
53          * 0x80000000   1G      PCIE  8,9,a,b
54          */
55         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
56                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57                       0, 1, BOOKE_PAGESZ_1G, 1),
58
59         /*
60          * TLB 2:       256M    Non-cacheable, guarded
61          */
62         SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
63                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
64                       0, 2, BOOKE_PAGESZ_256M, 1),
65
66         /*
67          * TLB 3:       256M    Non-cacheable, guarded
68          */
69         SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
70                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
71                       0, 3, BOOKE_PAGESZ_256M, 1),
72
73         /*
74          * TLB 4:       64M     Non-cacheable, guarded
75          * 0xe000_0000  1M      CCSRBAR
76          * 0xe100_0000  255M    PCI IO range
77          */
78         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
79                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
80                       0, 4, BOOKE_PAGESZ_64M, 1),
81
82         /*
83          * TLB 5:       64M     Non-cacheable, guarded
84          * 0xf8000000   64M     PIXIS 0xF8000000 - 0xFBFFFFFF
85          */
86         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
87                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
88                       0, 5, BOOKE_PAGESZ_64M, 1),
89 };
90
91 int num_tlb_entries = ARRAY_SIZE(tlb_table);