board/freescale/mpc8568mds/tlb.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/mmu.h>
  12
  13 struct fsl_e_tlb_entry tlb_table[] = {
  14         /* TLB 0 - for temp stack in cache */
  15         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  16                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  17                       0, 0, BOOKE_PAGESZ_4K, 0),
  18         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  19                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20                       0, 0, BOOKE_PAGESZ_4K, 0),
  21         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  22                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23                       0, 0, BOOKE_PAGESZ_4K, 0),
  24         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  25                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  26                       0, 0, BOOKE_PAGESZ_4K, 0),
  27
  28         /* TLB 1 Initializations */
  29         /*
  30          * TLBe 0:      16M     Non-cacheable, guarded
  31          * 0xff000000   16M     FLASH (upper half)
  32          * Out of reset this entry is only 4K.
  33          */
  34         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
  35                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  36                       0, 0, BOOKE_PAGESZ_16M, 1),
  37
  38         /*
  39          * TLBe 1:      16M     Non-cacheable, guarded
  40          * 0xfe000000   16M     FLASH (lower half)
  41          */
  42         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
  43                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  44                       0, 1, BOOKE_PAGESZ_16M, 1),
  45
  46         /*
  47          * TLBe 2:      1G      Non-cacheable, guarded
  48          * 0x80000000   512M    PCI1 MEM
  49          * 0xa0000000   512M    PCIe MEM
  50          */
  51         SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
  52                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  53                       0, 2, BOOKE_PAGESZ_1G, 1),
  54
  55         /*
  56          * TLBe 3:      64M     Non-cacheable, guarded
  57          * 0xe000_0000  1M      CCSRBAR
  58          * 0xe200_0000  8M      PCI1 IO
  59          * 0xe280_0000  8M      PCIe IO
  60          */
  61         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  62                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  63                       0, 3, BOOKE_PAGESZ_64M, 1),
  64
  65         /*
  66          * TLBe 4:      64M     Cacheable, non-guarded
  67          * 0xf000_0000  64M     LBC SDRAM
  68          */
  69         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
  70                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  71                       0, 4, BOOKE_PAGESZ_64M, 1),
  72
  73         /*
  74          * TLBe 5:      256K    Non-cacheable, guarded
  75          * 0xf8000000   32K BCSR
  76          * 0xf8008000   32K PIB (CS4)
  77          * 0xf8010000   32K PIB (CS5)
  78          */
  79         SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
  80                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  81                       0, 5, BOOKE_PAGESZ_256K, 1),
  82 };
  83
  84 int num_tlb_entries = ARRAY_SIZE(tlb_table);