board/freescale/mpc8610hpcd/mpc8610hpcd.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/immap_86xx.h>
  28 #include <asm/fsl_pci.h>
  29 #include <asm/fsl_ddr_sdram.h>
  30 #include <i2c.h>
  31 #include <asm/io.h>
  32 #include <libfdt.h>
  33 #include <fdt_support.h>
  34 #include <spd_sdram.h>
  35 #include <netdev.h>
  36
  37 #include "../common/pixis.h"
  38
  39 void sdram_init(void);
  40 phys_size_t fixed_sdram(void);
  41 void mpc8610hpcd_diu_init(void);
  42
  43
  44 /* called before any console output */
  45 int board_early_init_f(void)
  46 {
  47         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  48         volatile ccsr_gur_t *gur = &immap->im_gur;
  49
  50         gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
  51
  52         return 0;
  53 }
  54
  55 int misc_init_r(void)
  56 {
  57         u8 tmp_val, version;
  58         u8 *pixis_base = (u8 *)PIXIS_BASE;
  59
  60         /*Do not use 8259PIC*/
  61         tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  62         out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
  63
  64         /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
  65         version = in_8(pixis_base + PIXIS_PVER);
  66         if(version >= 0x07) {
  67                 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
  68                 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
  69         }
  70
  71         /* Using this for DIU init before the driver in linux takes over
  72          *  Enable the TFP410 Encoder (I2C address 0x38)
  73          */
  74
  75         tmp_val = 0xBF;
  76         i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  77         /* Verify if enabled */
  78         tmp_val = 0;
  79         i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
  80         debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
  81
  82         tmp_val = 0x10;
  83         i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  84         /* Verify if enabled */
  85         tmp_val = 0;
  86         i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
  87         debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
  88
  89 #ifdef CONFIG_FSL_DIU_FB
  90         mpc8610hpcd_diu_init();
  91 #endif
  92
  93         return 0;
  94 }
  95
  96 int checkboard(void)
  97 {
  98         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  99         volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
 100         u8 *pixis_base = (u8 *)PIXIS_BASE;
 101
 102         printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
 103                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
 104                 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
 105                 in_8(pixis_base + PIXIS_PVER));
 106
 107         mcm->abcr |= 0x00010000; /* 0 */
 108         mcm->hpmr3 = 0x80000008; /* 4c */
 109         mcm->hpmr0 = 0;
 110         mcm->hpmr1 = 0;
 111         mcm->hpmr2 = 0;
 112         mcm->hpmr4 = 0;
 113         mcm->hpmr5 = 0;
 114
 115         return 0;
 116 }
 117
 118
 119 phys_size_t
 120 initdram(int board_type)
 121 {
 122         phys_size_t dram_size = 0;
 123
 124 #if defined(CONFIG_SPD_EEPROM)
 125         dram_size = fsl_ddr_sdram();
 126 #else
 127         dram_size = fixed_sdram();
 128 #endif
 129
 130 #if defined(CONFIG_SYS_RAMBOOT)
 131         puts(" DDR: ");
 132         return dram_size;
 133 #endif
 134
 135         puts(" DDR: ");
 136         return dram_size;
 137 }
 138
 139
 140 #if !defined(CONFIG_SPD_EEPROM)
 141 /*
 142  * Fixed sdram init -- doesn't use serial presence detect.
 143  */
 144
 145 phys_size_t fixed_sdram(void)
 146 {
 147 #if !defined(CONFIG_SYS_RAMBOOT)
 148         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 149         volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 150         uint d_init;
 151
 152         ddr->cs0_bnds = 0x0000001f;
 153         ddr->cs0_config = 0x80010202;
 154
 155         ddr->timing_cfg_3 = 0x00000000;
 156         ddr->timing_cfg_0 = 0x00260802;
 157         ddr->timing_cfg_1 = 0x3935d322;
 158         ddr->timing_cfg_2 = 0x14904cc8;
 159         ddr->sdram_mode = 0x00480432;
 160         ddr->sdram_mode_2 = 0x00000000;
 161         ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
 162         ddr->sdram_data_init = 0xDEADBEEF;
 163         ddr->sdram_clk_cntl = 0x03800000;
 164         ddr->sdram_cfg_2 = 0x04400010;
 165
 166 #if defined(CONFIG_DDR_ECC)
 167         ddr->err_int_en = 0x0000000d;
 168         ddr->err_disable = 0x00000000;
 169         ddr->err_sbe = 0x00010000;
 170 #endif
 171         asm("sync;isync");
 172
 173         udelay(500);
 174
 175         ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
 176
 177
 178 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 179         d_init = 1;
 180         debug("DDR - 1st controller: memory initializing\n");
 181         /*
 182          * Poll until memory is initialized.
 183          * 512 Meg at 400 might hit this 200 times or so.
 184          */
 185         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 186                 udelay(1000);
 187
 188         debug("DDR: memory initialized\n\n");
 189         asm("sync; isync");
 190         udelay(500);
 191 #endif
 192
 193         return 512 * 1024 * 1024;
 194 #endif
 195         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 196 }
 197
 198 #endif
 199
 200 #if defined(CONFIG_PCI)
 201 /*
 202  * Initialize PCI Devices, report devices found.
 203  */
 204
 205 #ifndef CONFIG_PCI_PNP
 206 static struct pci_config_table pci_fsl86xxads_config_table[] = {
 207         {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 208          PCI_IDSEL_NUMBER, PCI_ANY_ID,
 209          pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
 210                                  PCI_ENET0_MEMADDR,
 211                                  PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
 212         {}
 213 };
 214 #endif
 215
 216
 217 static struct pci_controller pci1_hose = {
 218 #ifndef CONFIG_PCI_PNP
 219 config_table:pci_mpc86xxcts_config_table
 220 #endif
 221 };
 222 #endif /* CONFIG_PCI */
 223
 224 #ifdef CONFIG_PCIE1
 225 static struct pci_controller pcie1_hose;
 226 #endif
 227
 228 #ifdef CONFIG_PCIE2
 229 static struct pci_controller pcie2_hose;
 230 #endif
 231
 232 int first_free_busno = 0;
 233
 234 void pci_init_board(void)
 235 {
 236         volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 237         volatile ccsr_gur_t *gur = &immap->im_gur;
 238         uint devdisr = gur->devdisr;
 239         uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
 240                 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
 241         uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
 242                 >> MPC8610_PORBMSR_HA_SHIFT;
 243
 244         printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 245                 devdisr, io_sel, host_agent);
 246
 247 #ifdef CONFIG_PCIE1
 248  {
 249         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 250         struct pci_controller *hose = &pcie1_hose;
 251         int pcie_configured = (io_sel == 1) || (io_sel == 4);
 252         int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
 253                 (host_agent == 5);
 254         struct pci_region *r = hose->regions;
 255
 256         if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
 257                 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
 258                         pcie_ep ? "End Point" : "Root Complex",
 259                         (uint)pci);
 260                 if (pci->pme_msg_det)
 261                         pci->pme_msg_det = 0xffffffff;
 262
 263                 /* inbound */
 264                 r += fsl_pci_setup_inbound_windows(r);
 265
 266                 /* outbound memory */
 267                 pci_set_region(r++,
 268                          CONFIG_SYS_PCIE1_MEM_BUS,
 269                          CONFIG_SYS_PCIE1_MEM_PHYS,
 270                          CONFIG_SYS_PCIE1_MEM_SIZE,
 271                          PCI_REGION_MEM);
 272
 273                 /* outbound io */
 274                 pci_set_region(r++,
 275                          CONFIG_SYS_PCIE1_IO_BUS,
 276                          CONFIG_SYS_PCIE1_IO_PHYS,
 277                          CONFIG_SYS_PCIE1_IO_SIZE,
 278                          PCI_REGION_IO);
 279
 280                 hose->region_count = r - hose->regions;
 281
 282                 hose->first_busno = first_free_busno;
 283                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 284                                  (int)&pci->cfg_data);
 285
 286                 fsl_pci_init(hose);
 287
 288                 first_free_busno = hose->last_busno + 1;
 289                 printf(" PCI-Express 1 on bus %02x - %02x\n",
 290                         hose->first_busno, hose->last_busno);
 291
 292         } else
 293                 puts(" PCI-Express 1: Disabled\n");
 294  }
 295 #else
 296         puts("PCI-Express 1: Disabled\n");
 297 #endif /* CONFIG_PCIE1 */
 298
 299
 300 #ifdef CONFIG_PCIE2
 301  {
 302         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 303         struct pci_controller *hose = &pcie2_hose;
 304         struct pci_region *r = hose->regions;
 305
 306         int pcie_configured = (io_sel == 0) || (io_sel == 4);
 307         int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
 308                 (host_agent == 4);
 309
 310         if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
 311                 printf(" PCI-Express 2 connected to slot as %s" \
 312                         " (base address %x)\n",
 313                         pcie_ep ? "End Point" : "Root Complex",
 314                         (uint)pci);
 315                 if (pci->pme_msg_det)
 316                         pci->pme_msg_det = 0xffffffff;
 317
 318                 /* inbound */
 319                 r += fsl_pci_setup_inbound_windows(r);
 320
 321                 /* outbound memory */
 322                 pci_set_region(r++,
 323                          CONFIG_SYS_PCIE2_MEM_BUS,
 324                          CONFIG_SYS_PCIE2_MEM_PHYS,
 325                          CONFIG_SYS_PCIE2_MEM_SIZE,
 326                          PCI_REGION_MEM);
 327
 328                 /* outbound io */
 329                 pci_set_region(r++,
 330                          CONFIG_SYS_PCIE2_IO_BUS,
 331                          CONFIG_SYS_PCIE2_IO_PHYS,
 332                          CONFIG_SYS_PCIE2_IO_SIZE,
 333                          PCI_REGION_IO);
 334
 335                 hose->region_count = r - hose->regions;
 336
 337                 hose->first_busno = first_free_busno;
 338                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 339                                  (int)&pci->cfg_data);
 340
 341                 fsl_pci_init(hose);
 342
 343                 first_free_busno = hose->last_busno + 1;
 344                 printf(" PCI-Express 2 on bus %02x - %02x\n",
 345                         hose->first_busno, hose->last_busno);
 346         } else
 347                 puts(" PCI-Express 2: Disabled\n");
 348  }
 349 #else
 350         puts("PCI-Express 2: Disabled\n");
 351 #endif /* CONFIG_PCIE2 */
 352
 353
 354 #ifdef CONFIG_PCI1
 355  {
 356         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 357         struct pci_controller *hose = &pci1_hose;
 358         int pci_agent = (host_agent >= 4) && (host_agent <= 6);
 359         struct pci_region *r = hose->regions;
 360
 361         if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
 362                 printf(" PCI connected to PCI slots as %s" \
 363                         " (base address %x)\n",
 364                         pci_agent ? "Agent" : "Host",
 365                         (uint)pci);
 366
 367                 /* inbound */
 368                 r += fsl_pci_setup_inbound_windows(r);
 369
 370                 /* outbound memory */
 371                 pci_set_region(r++,
 372                          CONFIG_SYS_PCI1_MEM_BUS,
 373                          CONFIG_SYS_PCI1_MEM_PHYS,
 374                          CONFIG_SYS_PCI1_MEM_SIZE,
 375                          PCI_REGION_MEM);
 376
 377                 /* outbound io */
 378                 pci_set_region(r++,
 379                          CONFIG_SYS_PCI1_IO_BUS,
 380                          CONFIG_SYS_PCI1_IO_PHYS,
 381                          CONFIG_SYS_PCI1_IO_SIZE,
 382                          PCI_REGION_IO);
 383
 384                 hose->region_count = r - hose->regions;
 385
 386                 hose->first_busno = first_free_busno;
 387                 pci_setup_indirect(hose, (int) &pci->cfg_addr,
 388                                  (int) &pci->cfg_data);
 389
 390                 fsl_pci_init(hose);
 391
 392                 first_free_busno = hose->last_busno + 1;
 393                 printf(" PCI on bus %02x - %02x\n",
 394                         hose->first_busno, hose->last_busno);
 395
 396
 397         } else
 398                 puts(" PCI: Disabled\n");
 399  }
 400 #endif /* CONFIG_PCI1 */
 401 }
 402
 403 #if defined(CONFIG_OF_BOARD_SETUP)
 404 void
 405 ft_board_setup(void *blob, bd_t *bd)
 406 {
 407         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 408                              "timebase-frequency", bd->bi_busfreq / 4, 1);
 409         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 410                              "bus-frequency", bd->bi_busfreq, 1);
 411         do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
 412                              "clock-frequency", bd->bi_intfreq, 1);
 413         do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
 414                              "bus-frequency", bd->bi_busfreq, 1);
 415
 416         do_fixup_by_compat_u32(blob, "ns16550",
 417                                "clock-frequency", bd->bi_busfreq, 1);
 418
 419         fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
 420
 421 #ifdef CONFIG_PCI1
 422         ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
 423 #endif
 424 #ifdef CONFIG_PCIE1
 425         ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
 426 #endif
 427 #ifdef CONFIG_PCIE2
 428         ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
 429 #endif
 430 }
 431 #endif
 432
 433 /*
 434  * get_board_sys_clk
 435  * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
 436  */
 437
 438 unsigned long
 439 get_board_sys_clk(ulong dummy)
 440 {
 441         u8 i;
 442         ulong val = 0;
 443         u8 *pixis_base = (u8 *)PIXIS_BASE;
 444
 445         i = in_8(pixis_base + PIXIS_SPD);
 446         i &= 0x07;
 447
 448         switch (i) {
 449         case 0:
 450                 val = 33333000;
 451                 break;
 452         case 1:
 453                 val = 39999600;
 454                 break;
 455         case 2:
 456                 val = 49999500;
 457                 break;
 458         case 3:
 459                 val = 66666000;
 460                 break;
 461         case 4:
 462                 val = 83332500;
 463                 break;
 464         case 5:
 465                 val = 99999000;
 466                 break;
 467         case 6:
 468                 val = 133332000;
 469                 break;
 470         case 7:
 471                 val = 166665000;
 472                 break;
 473         }
 474
 475         return val;
 476 }
 477
 478 int board_eth_init(bd_t *bis)
 479 {
 480         return pci_eth_init(bis);
 481 }
 482
 483 void board_reset(void)
 484 {
 485         u8 *pixis_base = (u8 *)PIXIS_BASE;
 486
 487         out_8(pixis_base + PIXIS_RST, 0);
 488
 489         while (1)
 490                 ;
 491 }