board/freescale/mx53ard/mx53ard.c

   1 /*
   2  * (C) Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/clock.h>
  30 #include <asm/arch/iomux.h>
  31 #include <asm/errno.h>
  32 #include <netdev.h>
  33 #include <mmc.h>
  34 #include <fsl_esdhc.h>
  35 #include <asm/gpio.h>
  36
  37 #define ETHERNET_INT            IMX_GPIO_NR(2, 31)
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 int dram_init(void)
  42 {
  43         u32 size1, size2;
  44
  45         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  46         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  47
  48         gd->ram_size = size1 + size2;
  49
  50         return 0;
  51 }
  52 void dram_init_banksize(void)
  53 {
  54         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  55         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  56
  57         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  58         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  59 }
  60
  61 #ifdef CONFIG_NAND_MXC
  62 static void setup_iomux_nand(void)
  63 {
  64         u32 i, reg;
  65
  66         reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
  67         reg &= ~M4IF_GENP_WEIM_MM_MASK;
  68         __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
  69         for (i = 0x4; i < 0x94; i += 0x18) {
  70                 reg = __raw_readl(WEIM_BASE_ADDR + i);
  71                 reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
  72                 __raw_writel(reg, WEIM_BASE_ADDR + i);
  73         }
  74
  75         mxc_request_iomux(MX53_PIN_NANDF_CS0, IOMUX_CONFIG_ALT0);
  76         mxc_iomux_set_pad(MX53_PIN_NANDF_CS0, PAD_CTL_DRV_HIGH);
  77         mxc_request_iomux(MX53_PIN_NANDF_CS1, IOMUX_CONFIG_ALT0);
  78         mxc_iomux_set_pad(MX53_PIN_NANDF_CS1, PAD_CTL_DRV_HIGH);
  79         mxc_request_iomux(MX53_PIN_NANDF_RB0, IOMUX_CONFIG_ALT0);
  80         mxc_iomux_set_pad(MX53_PIN_NANDF_RB0, PAD_CTL_PKE_ENABLE |
  81                                         PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
  82         mxc_request_iomux(MX53_PIN_NANDF_CLE, IOMUX_CONFIG_ALT0);
  83         mxc_iomux_set_pad(MX53_PIN_NANDF_CLE, PAD_CTL_DRV_HIGH);
  84         mxc_request_iomux(MX53_PIN_NANDF_ALE, IOMUX_CONFIG_ALT0);
  85         mxc_iomux_set_pad(MX53_PIN_NANDF_ALE, PAD_CTL_DRV_HIGH);
  86         mxc_request_iomux(MX53_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT0);
  87         mxc_iomux_set_pad(MX53_PIN_NANDF_WP_B, PAD_CTL_PKE_ENABLE |
  88                                         PAD_CTL_PUE_PULL | PAD_CTL_100K_PU);
  89         mxc_request_iomux(MX53_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT0);
  90         mxc_iomux_set_pad(MX53_PIN_NANDF_RE_B, PAD_CTL_DRV_HIGH);
  91         mxc_request_iomux(MX53_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT0);
  92         mxc_iomux_set_pad(MX53_PIN_NANDF_WE_B, PAD_CTL_DRV_HIGH);
  93         mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
  94         mxc_iomux_set_pad(MX53_PIN_EIM_DA0, PAD_CTL_PKE_ENABLE |
  95                                         PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
  96         mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
  97         mxc_iomux_set_pad(MX53_PIN_EIM_DA1, PAD_CTL_PKE_ENABLE |
  98                                         PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
  99         mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
 100         mxc_iomux_set_pad(MX53_PIN_EIM_DA2, PAD_CTL_PKE_ENABLE |
 101                                         PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
 102         mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
 103         mxc_iomux_set_pad(MX53_PIN_EIM_DA3, PAD_CTL_PKE_ENABLE |
 104                                         PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
 105         mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
 106         mxc_iomux_set_pad(MX53_PIN_EIM_DA4, PAD_CTL_PKE_ENABLE |
 107                                         PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
 108         mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
 109         mxc_iomux_set_pad(MX53_PIN_EIM_DA5, PAD_CTL_PKE_ENABLE |
 110                                         PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
 111         mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
 112         mxc_iomux_set_pad(MX53_PIN_EIM_DA6, PAD_CTL_PKE_ENABLE |
 113                                         PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
 114         mxc_request_iomux(MX53_PIN_EIM_DA7, IOMUX_CONFIG_ALT0);
 115         mxc_iomux_set_pad(MX53_PIN_EIM_DA7, PAD_CTL_PKE_ENABLE |
 116                                         PAD_CTL_100K_PU | PAD_CTL_DRV_HIGH);
 117 }
 118 #else
 119 static void setup_iomux_nand(void)
 120 {
 121 }
 122 #endif
 123
 124 static void setup_iomux_uart(void)
 125 {
 126         /* UART1 RXD */
 127         mxc_request_iomux(MX53_PIN_ATA_DMACK, IOMUX_CONFIG_ALT3);
 128         mxc_iomux_set_pad(MX53_PIN_ATA_DMACK,
 129                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 130                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 131                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
 132                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 133         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x3);
 134
 135         /* UART1 TXD */
 136         mxc_request_iomux(MX53_PIN_ATA_DIOW, IOMUX_CONFIG_ALT3);
 137         mxc_iomux_set_pad(MX53_PIN_ATA_DIOW,
 138                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 139                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 140                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
 141                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
 142 }
 143
 144 #ifdef CONFIG_FSL_ESDHC
 145 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 146         {MMC_SDHC1_BASE_ADDR},
 147         {MMC_SDHC2_BASE_ADDR},
 148 };
 149
 150 int board_mmc_getcd(struct mmc *mmc)
 151 {
 152         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 153         int ret;
 154
 155         mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1);
 156         gpio_direction_input(IMX_GPIO_NR(1, 1));
 157         mxc_request_iomux(MX53_PIN_GPIO_4, IOMUX_CONFIG_ALT1);
 158         gpio_direction_input(IMX_GPIO_NR(1, 4));
 159
 160         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 161                 ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
 162         else
 163                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 164
 165         return ret;
 166 }
 167
 168 int board_mmc_init(bd_t *bis)
 169 {
 170         u32 index;
 171         s32 status = 0;
 172
 173         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 174         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 175
 176         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 177                 switch (index) {
 178                 case 0:
 179                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 180                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 181                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 182                                                 IOMUX_CONFIG_ALT0);
 183                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 184                                                 IOMUX_CONFIG_ALT0);
 185                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 186                                                 IOMUX_CONFIG_ALT0);
 187                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 188                                                 IOMUX_CONFIG_ALT0);
 189
 190                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD, 0x1E4);
 191                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK, 0xD4);
 192                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0, 0x1D4);
 193                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1, 0x1D4);
 194                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2, 0x1D4);
 195                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3, 0x1D4);
 196                         break;
 197                 case 1:
 198                         mxc_request_iomux(MX53_PIN_SD2_CMD,
 199                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 200                         mxc_request_iomux(MX53_PIN_SD2_CLK,
 201                                 IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);
 202                         mxc_request_iomux(MX53_PIN_SD2_DATA0,
 203                                                 IOMUX_CONFIG_ALT0);
 204                         mxc_request_iomux(MX53_PIN_SD2_DATA1,
 205                                                 IOMUX_CONFIG_ALT0);
 206                         mxc_request_iomux(MX53_PIN_SD2_DATA2,
 207                                                 IOMUX_CONFIG_ALT0);
 208                         mxc_request_iomux(MX53_PIN_SD2_DATA3,
 209                                                 IOMUX_CONFIG_ALT0);
 210                         mxc_request_iomux(MX53_PIN_ATA_DATA12,
 211                                                 IOMUX_CONFIG_ALT2);
 212                         mxc_request_iomux(MX53_PIN_ATA_DATA13,
 213                                                 IOMUX_CONFIG_ALT2);
 214                         mxc_request_iomux(MX53_PIN_ATA_DATA14,
 215                                                 IOMUX_CONFIG_ALT2);
 216                         mxc_request_iomux(MX53_PIN_ATA_DATA15,
 217                                                 IOMUX_CONFIG_ALT2);
 218
 219                         mxc_iomux_set_pad(MX53_PIN_SD2_CMD, 0x1E4);
 220                         mxc_iomux_set_pad(MX53_PIN_SD2_CLK, 0xD4);
 221                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA0, 0x1D4);
 222                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA1, 0x1D4);
 223                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA2, 0x1D4);
 224                         mxc_iomux_set_pad(MX53_PIN_SD2_DATA3, 0x1D4);
 225                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA12, 0x1D4);
 226                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA13, 0x1D4);
 227                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA14, 0x1D4);
 228                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA15, 0x1D4);
 229                         break;
 230                 default:
 231                         printf("Warning: you configured more ESDHC controller"
 232                                 "(%d) as supported by the board(2)\n",
 233                                 CONFIG_SYS_FSL_ESDHC_NUM);
 234                         return status;
 235                 }
 236                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 237         }
 238
 239         return status;
 240 }
 241 #endif
 242
 243 static void weim_smc911x_iomux(void)
 244 {
 245         /* ETHERNET_INT as GPIO2_31 */
 246         mxc_request_iomux(MX53_PIN_EIM_EB3, IOMUX_CONFIG_ALT1);
 247         gpio_direction_input(ETHERNET_INT);
 248
 249         /* Data bus */
 250         mxc_request_iomux(MX53_PIN_EIM_D16, IOMUX_CONFIG_ALT0);
 251         mxc_iomux_set_pad(MX53_PIN_EIM_D16, 0xA4);
 252
 253         mxc_request_iomux(MX53_PIN_EIM_D17, IOMUX_CONFIG_ALT0);
 254         mxc_iomux_set_pad(MX53_PIN_EIM_D17, 0xA4);
 255
 256         mxc_request_iomux(MX53_PIN_EIM_D18, IOMUX_CONFIG_ALT0);
 257         mxc_iomux_set_pad(MX53_PIN_EIM_D18, 0xA4);
 258
 259         mxc_request_iomux(MX53_PIN_EIM_D19, IOMUX_CONFIG_ALT0);
 260         mxc_iomux_set_pad(MX53_PIN_EIM_D19, 0xA4);
 261
 262         mxc_request_iomux(MX53_PIN_EIM_D20, IOMUX_CONFIG_ALT0);
 263         mxc_iomux_set_pad(MX53_PIN_EIM_D20, 0xA4);
 264
 265         mxc_request_iomux(MX53_PIN_EIM_D21, IOMUX_CONFIG_ALT0);
 266         mxc_iomux_set_pad(MX53_PIN_EIM_D21, 0xA4);
 267
 268         mxc_request_iomux(MX53_PIN_EIM_D22, IOMUX_CONFIG_ALT0);
 269         mxc_iomux_set_pad(MX53_PIN_EIM_D22, 0xA4);
 270
 271         mxc_request_iomux(MX53_PIN_EIM_D23, IOMUX_CONFIG_ALT0);
 272         mxc_iomux_set_pad(MX53_PIN_EIM_D23, 0xA4);
 273
 274         mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT0);
 275         mxc_iomux_set_pad(MX53_PIN_EIM_D24, 0xA4);
 276
 277         mxc_request_iomux(MX53_PIN_EIM_D25, IOMUX_CONFIG_ALT0);
 278         mxc_iomux_set_pad(MX53_PIN_EIM_D25, 0xA4);
 279
 280         mxc_request_iomux(MX53_PIN_EIM_D26, IOMUX_CONFIG_ALT0);
 281         mxc_iomux_set_pad(MX53_PIN_EIM_D26, 0xA4);
 282
 283         mxc_request_iomux(MX53_PIN_EIM_D27, IOMUX_CONFIG_ALT0);
 284         mxc_iomux_set_pad(MX53_PIN_EIM_D27, 0xA4);
 285
 286         mxc_request_iomux(MX53_PIN_EIM_D28, IOMUX_CONFIG_ALT0);
 287         mxc_iomux_set_pad(MX53_PIN_EIM_D28, 0xA4);
 288
 289         mxc_request_iomux(MX53_PIN_EIM_D29, IOMUX_CONFIG_ALT0);
 290         mxc_iomux_set_pad(MX53_PIN_EIM_D29, 0xA4);
 291
 292         mxc_request_iomux(MX53_PIN_EIM_D30, IOMUX_CONFIG_ALT0);
 293         mxc_iomux_set_pad(MX53_PIN_EIM_D30, 0xA4);
 294
 295         mxc_request_iomux(MX53_PIN_EIM_D31, IOMUX_CONFIG_ALT0);
 296         mxc_iomux_set_pad(MX53_PIN_EIM_D31, 0xA4);
 297
 298         /* Address lines */
 299         mxc_request_iomux(MX53_PIN_EIM_DA0, IOMUX_CONFIG_ALT0);
 300         mxc_iomux_set_pad(MX53_PIN_EIM_DA0, 0xA4);
 301
 302         mxc_request_iomux(MX53_PIN_EIM_DA1, IOMUX_CONFIG_ALT0);
 303         mxc_iomux_set_pad(MX53_PIN_EIM_DA1, 0xA4);
 304
 305         mxc_request_iomux(MX53_PIN_EIM_DA2, IOMUX_CONFIG_ALT0);
 306         mxc_iomux_set_pad(MX53_PIN_EIM_DA2, 0xA4);
 307
 308         mxc_request_iomux(MX53_PIN_EIM_DA3, IOMUX_CONFIG_ALT0);
 309         mxc_iomux_set_pad(MX53_PIN_EIM_DA3, 0xA4);
 310
 311         mxc_request_iomux(MX53_PIN_EIM_DA4, IOMUX_CONFIG_ALT0);
 312         mxc_iomux_set_pad(MX53_PIN_EIM_DA4, 0xA4);
 313
 314         mxc_request_iomux(MX53_PIN_EIM_DA5, IOMUX_CONFIG_ALT0);
 315         mxc_iomux_set_pad(MX53_PIN_EIM_DA5, 0xA4);
 316
 317         mxc_request_iomux(MX53_PIN_EIM_DA6, IOMUX_CONFIG_ALT0);
 318         mxc_iomux_set_pad(MX53_PIN_EIM_DA6, 0xA4);
 319
 320         /* other EIM signals for ethernet */
 321         mxc_request_iomux(MX53_PIN_EIM_OE, IOMUX_CONFIG_ALT0);
 322         mxc_request_iomux(MX53_PIN_EIM_RW, IOMUX_CONFIG_ALT0);
 323         mxc_request_iomux(MX53_PIN_EIM_CS1, IOMUX_CONFIG_ALT0);
 324 }
 325
 326 static void weim_cs1_settings(void)
 327 {
 328         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 329
 330         writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
 331         writel(0x0, &weim_regs->cs1gcr2);
 332         writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
 333         writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
 334         writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
 335         writel(0x0, &weim_regs->cs1wcr2);
 336         writel(0x0, &weim_regs->wcr);
 337
 338         set_chipselect_size(CS0_64M_CS1_64M);
 339 }
 340
 341 int board_early_init_f(void)
 342 {
 343         setup_iomux_nand();
 344         setup_iomux_uart();
 345         return 0;
 346 }
 347
 348 int board_init(void)
 349 {
 350         /* address of boot parameters */
 351         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 352
 353         return 0;
 354 }
 355
 356 int board_eth_init(bd_t *bis)
 357 {
 358         int rc = -ENODEV;
 359
 360         weim_smc911x_iomux();
 361         weim_cs1_settings();
 362
 363 #ifdef CONFIG_SMC911X
 364         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 365 #endif
 366         return rc;
 367 }
 368
 369 int checkboard(void)
 370 {
 371         puts("Board: MX53ARD\n");
 372
 373         return 0;
 374 }