board/freescale/mx53ard/mx53ard.c

   1 /*
   2  * (C) Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/imx-regs.h>
  10 #include <asm/arch/sys_proto.h>
  11 #include <asm/arch/crm_regs.h>
  12 #include <asm/arch/clock.h>
  13 #include <asm/arch/iomux-mx53.h>
  14 #include <asm/errno.h>
  15 #include <netdev.h>
  16 #include <mmc.h>
  17 #include <fsl_esdhc.h>
  18 #include <asm/gpio.h>
  19
  20 #define ETHERNET_INT            IMX_GPIO_NR(2, 31)
  21
  22 DECLARE_GLOBAL_DATA_PTR;
  23
  24 int dram_init(void)
  25 {
  26         u32 size1, size2;
  27
  28         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  29         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  30
  31         gd->ram_size = size1 + size2;
  32
  33         return 0;
  34 }
  35 void dram_init_banksize(void)
  36 {
  37         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  38         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  39
  40         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  41         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  42 }
  43
  44 #ifdef CONFIG_NAND_MXC
  45 static void setup_iomux_nand(void)
  46 {
  47         static const iomux_v3_cfg_t nand_pads[] = {
  48                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0,
  49                                 PAD_CTL_DSE_HIGH),
  50                 NEW_PAD_CTRL(MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1,
  51                                 PAD_CTL_DSE_HIGH),
  52                 NEW_PAD_CTRL(MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0,
  53                                 PAD_CTL_PUS_100K_UP),
  54                 NEW_PAD_CTRL(MX53_PAD_NANDF_CLE__EMI_NANDF_CLE,
  55                                 PAD_CTL_DSE_HIGH),
  56                 NEW_PAD_CTRL(MX53_PAD_NANDF_ALE__EMI_NANDF_ALE,
  57                                 PAD_CTL_DSE_HIGH),
  58                 NEW_PAD_CTRL(MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B,
  59                                 PAD_CTL_PUS_100K_UP),
  60                 NEW_PAD_CTRL(MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B,
  61                                 PAD_CTL_DSE_HIGH),
  62                 NEW_PAD_CTRL(MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B,
  63                                 PAD_CTL_DSE_HIGH),
  64                 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
  65                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  66                 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
  67                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  68                 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
  69                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  70                 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
  71                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  72                 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
  73                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  74                 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
  75                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  76                 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
  77                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  78                 NEW_PAD_CTRL(MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7,
  79                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
  80         };
  81
  82         u32 i, reg;
  83
  84         reg = __raw_readl(M4IF_BASE_ADDR + 0xc);
  85         reg &= ~M4IF_GENP_WEIM_MM_MASK;
  86         __raw_writel(reg, M4IF_BASE_ADDR + 0xc);
  87         for (i = 0x4; i < 0x94; i += 0x18) {
  88                 reg = __raw_readl(WEIM_BASE_ADDR + i);
  89                 reg &= ~WEIM_GCR2_MUX16_BYP_GRANT_MASK;
  90                 __raw_writel(reg, WEIM_BASE_ADDR + i);
  91         }
  92
  93         imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  94 }
  95 #else
  96 static void setup_iomux_nand(void)
  97 {
  98 }
  99 #endif
 100
 101 #define UART_PAD_CTRL   (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 102                          PAD_CTL_PUS_100K_UP | PAD_CTL_ODE)
 103
 104 static void setup_iomux_uart(void)
 105 {
 106         static const iomux_v3_cfg_t uart_pads[] = {
 107                 NEW_PAD_CTRL(MX53_PAD_PATA_DMACK__UART1_RXD_MUX, UART_PAD_CTRL),
 108                 NEW_PAD_CTRL(MX53_PAD_PATA_DIOW__UART1_TXD_MUX, UART_PAD_CTRL),
 109         };
 110
 111         imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
 112 }
 113
 114 #ifdef CONFIG_FSL_ESDHC
 115 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 116         {MMC_SDHC1_BASE_ADDR},
 117         {MMC_SDHC2_BASE_ADDR},
 118 };
 119
 120 int board_mmc_getcd(struct mmc *mmc)
 121 {
 122         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 123         int ret;
 124
 125         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_1__GPIO1_1);
 126         gpio_direction_input(IMX_GPIO_NR(1, 1));
 127         imx_iomux_v3_setup_pad(MX53_PAD_GPIO_4__GPIO1_4);
 128         gpio_direction_input(IMX_GPIO_NR(1, 4));
 129
 130         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 131                 ret = !gpio_get_value(IMX_GPIO_NR(1, 1));
 132         else
 133                 ret = !gpio_get_value(IMX_GPIO_NR(1, 4));
 134
 135         return ret;
 136 }
 137
 138 #define SD_CMD_PAD_CTRL         (PAD_CTL_HYS | PAD_CTL_DSE_HIGH | \
 139                                  PAD_CTL_PUS_100K_UP)
 140 #define SD_CLK_PAD_CTRL         (PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
 141 #define SD_PAD_CTRL             (PAD_CTL_HYS | PAD_CTL_PUS_47K_UP | \
 142                                  PAD_CTL_DSE_HIGH)
 143
 144 int board_mmc_init(bd_t *bis)
 145 {
 146         static const iomux_v3_cfg_t sd1_pads[] = {
 147                 NEW_PAD_CTRL(MX53_PAD_SD1_CMD__ESDHC1_CMD, SD_CMD_PAD_CTRL),
 148                 NEW_PAD_CTRL(MX53_PAD_SD1_CLK__ESDHC1_CLK, SD_CLK_PAD_CTRL),
 149                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA0__ESDHC1_DAT0, SD_PAD_CTRL),
 150                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA1__ESDHC1_DAT1, SD_PAD_CTRL),
 151                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA2__ESDHC1_DAT2, SD_PAD_CTRL),
 152                 NEW_PAD_CTRL(MX53_PAD_SD1_DATA3__ESDHC1_DAT3, SD_PAD_CTRL),
 153         };
 154
 155         static const iomux_v3_cfg_t sd2_pads[] = {
 156                 NEW_PAD_CTRL(MX53_PAD_SD2_CMD__ESDHC2_CMD, SD_CMD_PAD_CTRL),
 157                 NEW_PAD_CTRL(MX53_PAD_SD2_CLK__ESDHC2_CLK, SD_CLK_PAD_CTRL),
 158                 NEW_PAD_CTRL(MX53_PAD_SD2_DATA0__ESDHC2_DAT0, SD_PAD_CTRL),
 159                 NEW_PAD_CTRL(MX53_PAD_SD2_DATA1__ESDHC2_DAT1, SD_PAD_CTRL),
 160                 NEW_PAD_CTRL(MX53_PAD_SD2_DATA2__ESDHC2_DAT2, SD_PAD_CTRL),
 161                 NEW_PAD_CTRL(MX53_PAD_SD2_DATA3__ESDHC2_DAT3, SD_PAD_CTRL),
 162                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA12__ESDHC2_DAT4, SD_PAD_CTRL),
 163                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA13__ESDHC2_DAT5, SD_PAD_CTRL),
 164                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA14__ESDHC2_DAT6, SD_PAD_CTRL),
 165                 NEW_PAD_CTRL(MX53_PAD_PATA_DATA15__ESDHC2_DAT7, SD_PAD_CTRL),
 166         };
 167
 168         u32 index;
 169         int ret;
 170
 171         esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
 172         esdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 173
 174         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 175                 switch (index) {
 176                 case 0:
 177                         imx_iomux_v3_setup_multiple_pads(sd1_pads,
 178                                                          ARRAY_SIZE(sd1_pads));
 179                         break;
 180                 case 1:
 181                         imx_iomux_v3_setup_multiple_pads(sd2_pads,
 182                                                          ARRAY_SIZE(sd2_pads));
 183                         break;
 184                 default:
 185                         printf("Warning: you configured more ESDHC controller"
 186                                 "(%d) as supported by the board(2)\n",
 187                                 CONFIG_SYS_FSL_ESDHC_NUM);
 188                         return -EINVAL;
 189                 }
 190                 ret = fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 191                 if (ret)
 192                         return ret;
 193         }
 194
 195         return 0;
 196 }
 197 #endif
 198
 199 static void weim_smc911x_iomux(void)
 200 {
 201         static const iomux_v3_cfg_t weim_smc911x_pads[] = {
 202                 /* Data bus */
 203                 NEW_PAD_CTRL(MX53_PAD_EIM_D16__EMI_WEIM_D_16,
 204                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 205                 NEW_PAD_CTRL(MX53_PAD_EIM_D17__EMI_WEIM_D_17,
 206                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 207                 NEW_PAD_CTRL(MX53_PAD_EIM_D18__EMI_WEIM_D_18,
 208                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 209                 NEW_PAD_CTRL(MX53_PAD_EIM_D19__EMI_WEIM_D_19,
 210                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 211                 NEW_PAD_CTRL(MX53_PAD_EIM_D20__EMI_WEIM_D_20,
 212                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 213                 NEW_PAD_CTRL(MX53_PAD_EIM_D21__EMI_WEIM_D_21,
 214                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 215                 NEW_PAD_CTRL(MX53_PAD_EIM_D22__EMI_WEIM_D_22,
 216                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 217                 NEW_PAD_CTRL(MX53_PAD_EIM_D23__EMI_WEIM_D_23,
 218                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 219                 NEW_PAD_CTRL(MX53_PAD_EIM_D24__EMI_WEIM_D_24,
 220                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 221                 NEW_PAD_CTRL(MX53_PAD_EIM_D25__EMI_WEIM_D_25,
 222                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 223                 NEW_PAD_CTRL(MX53_PAD_EIM_D26__EMI_WEIM_D_26,
 224                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 225                 NEW_PAD_CTRL(MX53_PAD_EIM_D27__EMI_WEIM_D_27,
 226                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 227                 NEW_PAD_CTRL(MX53_PAD_EIM_D28__EMI_WEIM_D_28,
 228                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 229                 NEW_PAD_CTRL(MX53_PAD_EIM_D29__EMI_WEIM_D_29,
 230                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 231                 NEW_PAD_CTRL(MX53_PAD_EIM_D30__EMI_WEIM_D_30,
 232                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 233                 NEW_PAD_CTRL(MX53_PAD_EIM_D31__EMI_WEIM_D_31,
 234                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 235
 236                 /* Address lines */
 237                 NEW_PAD_CTRL(MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0,
 238                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 239                 NEW_PAD_CTRL(MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1,
 240                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 241                 NEW_PAD_CTRL(MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2,
 242                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 243                 NEW_PAD_CTRL(MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3,
 244                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 245                 NEW_PAD_CTRL(MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4,
 246                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 247                 NEW_PAD_CTRL(MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5,
 248                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 249                 NEW_PAD_CTRL(MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6,
 250                                 PAD_CTL_PKE | PAD_CTL_DSE_HIGH),
 251
 252                 /* other EIM signals for ethernet */
 253                 MX53_PAD_EIM_OE__EMI_WEIM_OE,
 254                 MX53_PAD_EIM_RW__EMI_WEIM_RW,
 255                 MX53_PAD_EIM_CS1__EMI_WEIM_CS_1,
 256         };
 257
 258         /* ETHERNET_INT as GPIO2_31 */
 259         imx_iomux_v3_setup_pad(MX53_PAD_EIM_EB3__GPIO2_31);
 260         gpio_direction_input(ETHERNET_INT);
 261
 262         /* WEIM bus */
 263         imx_iomux_v3_setup_multiple_pads(weim_smc911x_pads,
 264                                                 ARRAY_SIZE(weim_smc911x_pads));
 265 }
 266
 267 static void weim_cs1_settings(void)
 268 {
 269         struct weim *weim_regs = (struct weim *)WEIM_BASE_ADDR;
 270
 271         writel(MX53ARD_CS1GCR1, &weim_regs->cs1gcr1);
 272         writel(0x0, &weim_regs->cs1gcr2);
 273         writel(MX53ARD_CS1RCR1, &weim_regs->cs1rcr1);
 274         writel(MX53ARD_CS1RCR2, &weim_regs->cs1rcr2);
 275         writel(MX53ARD_CS1WCR1, &weim_regs->cs1wcr1);
 276         writel(0x0, &weim_regs->cs1wcr2);
 277         writel(0x0, &weim_regs->wcr);
 278
 279         set_chipselect_size(CS0_64M_CS1_64M);
 280 }
 281
 282 int board_early_init_f(void)
 283 {
 284         setup_iomux_nand();
 285         setup_iomux_uart();
 286         return 0;
 287 }
 288
 289 int board_init(void)
 290 {
 291         /* address of boot parameters */
 292         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 293
 294         return 0;
 295 }
 296
 297 int board_eth_init(bd_t *bis)
 298 {
 299         int rc = -ENODEV;
 300
 301         weim_smc911x_iomux();
 302         weim_cs1_settings();
 303
 304 #ifdef CONFIG_SMC911X
 305         rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
 306 #endif
 307         return rc;
 308 }
 309
 310 int checkboard(void)
 311 {
 312         puts("Board: MX53ARD\n");
 313
 314         return 0;
 315 }