board/freescale/mx53loco/mx53loco.c

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc.
   3  * Jason Liu <r64343@freescale.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #include <common.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/mx5x_pins.h>
  28 #include <asm/arch/sys_proto.h>
  29 #include <asm/arch/crm_regs.h>
  30 #include <asm/arch/iomux.h>
  31 #include <asm/arch/clock.h>
  32 #include <asm/errno.h>
  33 #include <netdev.h>
  34 #include <i2c.h>
  35 #include <mmc.h>
  36 #include <fsl_esdhc.h>
  37 #include <asm/gpio.h>
  38
  39 DECLARE_GLOBAL_DATA_PTR;
  40
  41 int dram_init(void)
  42 {
  43         u32 size1, size2;
  44
  45         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  46         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  47
  48         gd->ram_size = size1 + size2;
  49
  50         return 0;
  51 }
  52 void dram_init_banksize(void)
  53 {
  54         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  55         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  56
  57         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  58         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  59 }
  60
  61 static void setup_iomux_uart(void)
  62 {
  63         /* UART1 RXD */
  64         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  65         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  66                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  67                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  68                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  69                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  70         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  71
  72         /* UART1 TXD */
  73         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  74         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  75                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  76                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  77                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  78                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  79 }
  80
  81 #ifdef CONFIG_USB_EHCI_MX5
  82 int board_ehci_hcd_init(int port)
  83 {
  84         /* request VBUS power enable pin, GPIO[8}, gpio7 */
  85         mxc_request_iomux(MX53_PIN_ATA_DA_2, IOMUX_CONFIG_ALT1);
  86         gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 0);
  87         gpio_set_value(IOMUX_TO_GPIO(MX53_PIN_ATA_DA_2), 1);
  88         return 0;
  89 }
  90 #endif
  91
  92 static void setup_iomux_fec(void)
  93 {
  94         /*FEC_MDIO*/
  95         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
  96         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
  97                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  98                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  99                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
 100         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
 101
 102         /*FEC_MDC*/
 103         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
 104         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
 105
 106         /* FEC RXD1 */
 107         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
 108         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 109                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 110
 111         /* FEC RXD0 */
 112         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 113         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 114                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 115
 116          /* FEC TXD1 */
 117         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 118         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 119
 120         /* FEC TXD0 */
 121         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 122         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 123
 124         /* FEC TX_EN */
 125         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 126         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 127
 128         /* FEC TX_CLK */
 129         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 130         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 131                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 132
 133         /* FEC RX_ER */
 134         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 135         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 136                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 137
 138         /* FEC CRS */
 139         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 140         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 141                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 142 }
 143
 144 #ifdef CONFIG_FSL_ESDHC
 145 struct fsl_esdhc_cfg esdhc_cfg[2] = {
 146         {MMC_SDHC1_BASE_ADDR, 1},
 147         {MMC_SDHC3_BASE_ADDR, 1},
 148 };
 149
 150 int board_mmc_getcd(struct mmc *mmc)
 151 {
 152         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 153         int ret;
 154
 155         mxc_request_iomux(MX53_PIN_EIM_DA11, IOMUX_CONFIG_ALT1);
 156         gpio_direction_input(75);
 157         mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
 158         gpio_direction_input(77);
 159
 160         if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
 161                 ret = !gpio_get_value(77); /* GPIO3_13 */
 162         else
 163                 ret = !gpio_get_value(75); /* GPIO3_11 */
 164
 165         return ret;
 166 }
 167
 168 int board_mmc_init(bd_t *bis)
 169 {
 170         u32 index;
 171         s32 status = 0;
 172
 173         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 174                 switch (index) {
 175                 case 0:
 176                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 177                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 178                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 179                                                 IOMUX_CONFIG_ALT0);
 180                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 181                                                 IOMUX_CONFIG_ALT0);
 182                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 183                                                 IOMUX_CONFIG_ALT0);
 184                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 185                                                 IOMUX_CONFIG_ALT0);
 186                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 187                                                 IOMUX_CONFIG_ALT1);
 188
 189                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 190                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 191                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 192                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 193                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 194                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 195                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 196                                 PAD_CTL_DRV_HIGH);
 197                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 198                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 199                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 200                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 201                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 202                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 203                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 204                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 205                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 206                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 207                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 208                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 209                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 210                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 211                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 212                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 213                         break;
 214                 case 1:
 215                         mxc_request_iomux(MX53_PIN_ATA_RESET_B,
 216                                                 IOMUX_CONFIG_ALT2);
 217                         mxc_request_iomux(MX53_PIN_ATA_IORDY,
 218                                                 IOMUX_CONFIG_ALT2);
 219                         mxc_request_iomux(MX53_PIN_ATA_DATA8,
 220                                                 IOMUX_CONFIG_ALT4);
 221                         mxc_request_iomux(MX53_PIN_ATA_DATA9,
 222                                                 IOMUX_CONFIG_ALT4);
 223                         mxc_request_iomux(MX53_PIN_ATA_DATA10,
 224                                                 IOMUX_CONFIG_ALT4);
 225                         mxc_request_iomux(MX53_PIN_ATA_DATA11,
 226                                                 IOMUX_CONFIG_ALT4);
 227                         mxc_request_iomux(MX53_PIN_ATA_DATA0,
 228                                                 IOMUX_CONFIG_ALT4);
 229                         mxc_request_iomux(MX53_PIN_ATA_DATA1,
 230                                                 IOMUX_CONFIG_ALT4);
 231                         mxc_request_iomux(MX53_PIN_ATA_DATA2,
 232                                                 IOMUX_CONFIG_ALT4);
 233                         mxc_request_iomux(MX53_PIN_ATA_DATA3,
 234                                                 IOMUX_CONFIG_ALT4);
 235                         mxc_request_iomux(MX53_PIN_EIM_DA11,
 236                                                 IOMUX_CONFIG_ALT1);
 237
 238                         mxc_iomux_set_pad(MX53_PIN_ATA_RESET_B,
 239                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 240                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 241                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 242                         mxc_iomux_set_pad(MX53_PIN_ATA_IORDY,
 243                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 244                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 245                                 PAD_CTL_DRV_HIGH);
 246                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA8,
 247                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 248                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 249                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 250                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA9,
 251                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 252                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 253                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 254                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA10,
 255                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 256                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 257                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 258                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA11,
 259                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 260                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 261                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 262                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA0,
 263                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 264                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 265                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 266                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA1,
 267                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 268                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 269                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 270                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA2,
 271                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 272                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 273                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 274                         mxc_iomux_set_pad(MX53_PIN_ATA_DATA3,
 275                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 276                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 277                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 278
 279                         break;
 280                 default:
 281                         printf("Warning: you configured more ESDHC controller"
 282                                 "(%d) as supported by the board(2)\n",
 283                                 CONFIG_SYS_FSL_ESDHC_NUM);
 284                         return status;
 285                 }
 286                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 287         }
 288
 289         return status;
 290 }
 291 #endif
 292
 293 int board_early_init_f(void)
 294 {
 295         setup_iomux_uart();
 296         setup_iomux_fec();
 297
 298         return 0;
 299 }
 300
 301 int board_init(void)
 302 {
 303         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 304
 305         return 0;
 306 }
 307
 308 int checkboard(void)
 309 {
 310         puts("Board: MX53 LOCO\n");
 311
 312         return 0;
 313 }