board/freescale/mx53smd/mx53smd.c

   1 /*
   2  * (C) Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc.h>
  34 #include <asm/gpio.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 int dram_init(void)
  39 {
  40         u32 size1, size2;
  41
  42         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  43         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  44
  45         gd->ram_size = size1 + size2;
  46
  47         return 0;
  48 }
  49 void dram_init_banksize(void)
  50 {
  51         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  52         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  53
  54         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  55         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  56 }
  57
  58 static void setup_iomux_uart(void)
  59 {
  60         /* UART1 RXD */
  61         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  62         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  63                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  64                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  65                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  66                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  67         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  68
  69         /* UART1 TXD */
  70         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  71         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  72                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  73                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  74                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  75                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  76 }
  77
  78 static void setup_iomux_fec(void)
  79 {
  80         /*FEC_MDIO*/
  81         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
  82         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
  83                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  84                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  85                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
  86         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
  87
  88         /*FEC_MDC*/
  89         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
  90         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
  91
  92         /* FEC RXD1 */
  93         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
  94         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
  95                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
  96
  97         /* FEC RXD0 */
  98         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
  99         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 100                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 101
 102          /* FEC TXD1 */
 103         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 104         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 105
 106         /* FEC TXD0 */
 107         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 108         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 109
 110         /* FEC TX_EN */
 111         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 112         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 113
 114         /* FEC TX_CLK */
 115         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 116         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 117                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 118
 119         /* FEC RX_ER */
 120         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 121         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 122                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 123
 124         /* FEC CRS */
 125         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 126         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 127                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 128 }
 129
 130 #ifdef CONFIG_FSL_ESDHC
 131 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 132         {MMC_SDHC1_BASE_ADDR, 1},
 133 };
 134
 135 int board_mmc_getcd(struct mmc *mmc)
 136 {
 137         mxc_request_iomux(MX53_PIN_EIM_DA13, IOMUX_CONFIG_ALT1);
 138         return !gpio_get_value(77); /* GPIO3_13 */
 139 }
 140
 141 int board_mmc_init(bd_t *bis)
 142 {
 143         u32 index;
 144         s32 status = 0;
 145
 146         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 147                 switch (index) {
 148                 case 0:
 149                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 150                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 151                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 152                                                 IOMUX_CONFIG_ALT0);
 153                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 154                                                 IOMUX_CONFIG_ALT0);
 155                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 156                                                 IOMUX_CONFIG_ALT0);
 157                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 158                                                 IOMUX_CONFIG_ALT0);
 159                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 160                                                 IOMUX_CONFIG_ALT1);
 161
 162                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 163                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 164                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 165                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 166                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 167                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 168                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 169                                 PAD_CTL_DRV_HIGH);
 170                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 171                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 172                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 173                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 174                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 175                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 176                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 177                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 178                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 179                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 180                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 181                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 182                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 183                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 184                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 185                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 186                         break;
 187
 188                 default:
 189                         printf("Warning: you configured more ESDHC controller"
 190                                 "(%d) as supported by the board(1)\n",
 191                                 CONFIG_SYS_FSL_ESDHC_NUM);
 192                         return status;
 193                 }
 194                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 195         }
 196
 197         return status;
 198 }
 199 #endif
 200
 201 int board_early_init_f(void)
 202 {
 203         setup_iomux_uart();
 204         setup_iomux_fec();
 205
 206         return 0;
 207 }
 208
 209 int board_init(void)
 210 {
 211         /* address of boot parameters */
 212         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 213
 214         return 0;
 215 }
 216
 217 int checkboard(void)
 218 {
 219         puts("Board: MX53SMD\n");
 220
 221         return 0;
 222 }