board/freescale/mx53smd/mx53smd.c

   1 /*
   2  * (C) Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/imx-regs.h>
  26 #include <asm/arch/mx5x_pins.h>
  27 #include <asm/arch/sys_proto.h>
  28 #include <asm/arch/crm_regs.h>
  29 #include <asm/arch/iomux.h>
  30 #include <asm/errno.h>
  31 #include <netdev.h>
  32 #include <mmc.h>
  33 #include <fsl_esdhc.h>
  34 #include <mxc_gpio.h>
  35
  36 DECLARE_GLOBAL_DATA_PTR;
  37
  38 u32 get_board_rev(void)
  39 {
  40         return get_cpu_rev();
  41 }
  42
  43 int dram_init(void)
  44 {
  45         u32 size1, size2;
  46
  47         size1 = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
  48         size2 = get_ram_size((void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE);
  49
  50         gd->ram_size = size1 + size2;
  51
  52         return 0;
  53 }
  54 void dram_init_banksize(void)
  55 {
  56         gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  57         gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  58
  59         gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  60         gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
  61 }
  62
  63 static void setup_iomux_uart(void)
  64 {
  65         /* UART1 RXD */
  66         mxc_request_iomux(MX53_PIN_CSI0_D11, IOMUX_CONFIG_ALT2);
  67         mxc_iomux_set_pad(MX53_PIN_CSI0_D11,
  68                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  69                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  70                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  71                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  72         mxc_iomux_set_input(MX53_UART1_IPP_UART_RXD_MUX_SELECT_INPUT, 0x1);
  73
  74         /* UART1 TXD */
  75         mxc_request_iomux(MX53_PIN_CSI0_D10, IOMUX_CONFIG_ALT2);
  76         mxc_iomux_set_pad(MX53_PIN_CSI0_D10,
  77                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  78                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  79                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU |
  80                                 PAD_CTL_ODE_OPENDRAIN_ENABLE);
  81 }
  82
  83 static void setup_iomux_fec(void)
  84 {
  85         /*FEC_MDIO*/
  86         mxc_request_iomux(MX53_PIN_FEC_MDIO, IOMUX_CONFIG_ALT0);
  87         mxc_iomux_set_pad(MX53_PIN_FEC_MDIO,
  88                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
  89                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
  90                                 PAD_CTL_22K_PU | PAD_CTL_ODE_OPENDRAIN_ENABLE);
  91         mxc_iomux_set_input(MX53_FEC_FEC_MDI_SELECT_INPUT, 0x1);
  92
  93         /*FEC_MDC*/
  94         mxc_request_iomux(MX53_PIN_FEC_MDC, IOMUX_CONFIG_ALT0);
  95         mxc_iomux_set_pad(MX53_PIN_FEC_MDC, PAD_CTL_DRV_HIGH);
  96
  97         /* FEC RXD1 */
  98         mxc_request_iomux(MX53_PIN_FEC_RXD1, IOMUX_CONFIG_ALT0);
  99         mxc_iomux_set_pad(MX53_PIN_FEC_RXD1,
 100                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 101
 102         /* FEC RXD0 */
 103         mxc_request_iomux(MX53_PIN_FEC_RXD0, IOMUX_CONFIG_ALT0);
 104         mxc_iomux_set_pad(MX53_PIN_FEC_RXD0,
 105                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 106
 107          /* FEC TXD1 */
 108         mxc_request_iomux(MX53_PIN_FEC_TXD1, IOMUX_CONFIG_ALT0);
 109         mxc_iomux_set_pad(MX53_PIN_FEC_TXD1, PAD_CTL_DRV_HIGH);
 110
 111         /* FEC TXD0 */
 112         mxc_request_iomux(MX53_PIN_FEC_TXD0, IOMUX_CONFIG_ALT0);
 113         mxc_iomux_set_pad(MX53_PIN_FEC_TXD0, PAD_CTL_DRV_HIGH);
 114
 115         /* FEC TX_EN */
 116         mxc_request_iomux(MX53_PIN_FEC_TX_EN, IOMUX_CONFIG_ALT0);
 117         mxc_iomux_set_pad(MX53_PIN_FEC_TX_EN, PAD_CTL_DRV_HIGH);
 118
 119         /* FEC TX_CLK */
 120         mxc_request_iomux(MX53_PIN_FEC_REF_CLK, IOMUX_CONFIG_ALT0);
 121         mxc_iomux_set_pad(MX53_PIN_FEC_REF_CLK,
 122                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 123
 124         /* FEC RX_ER */
 125         mxc_request_iomux(MX53_PIN_FEC_RX_ER, IOMUX_CONFIG_ALT0);
 126         mxc_iomux_set_pad(MX53_PIN_FEC_RX_ER,
 127                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 128
 129         /* FEC CRS */
 130         mxc_request_iomux(MX53_PIN_FEC_CRS_DV, IOMUX_CONFIG_ALT0);
 131         mxc_iomux_set_pad(MX53_PIN_FEC_CRS_DV,
 132                         PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);
 133 }
 134
 135 #ifdef CONFIG_FSL_ESDHC
 136 struct fsl_esdhc_cfg esdhc_cfg[1] = {
 137         {MMC_SDHC1_BASE_ADDR, 1},
 138 };
 139
 140 int board_mmc_getcd(u8 *cd, struct mmc *mmc)
 141 {
 142         *cd = mxc_gpio_get(77); /*GPIO3_13*/
 143
 144         return 0;
 145 }
 146
 147 int board_mmc_init(bd_t *bis)
 148 {
 149         u32 index;
 150         s32 status = 0;
 151
 152         for (index = 0; index < CONFIG_SYS_FSL_ESDHC_NUM; index++) {
 153                 switch (index) {
 154                 case 0:
 155                         mxc_request_iomux(MX53_PIN_SD1_CMD, IOMUX_CONFIG_ALT0);
 156                         mxc_request_iomux(MX53_PIN_SD1_CLK, IOMUX_CONFIG_ALT0);
 157                         mxc_request_iomux(MX53_PIN_SD1_DATA0,
 158                                                 IOMUX_CONFIG_ALT0);
 159                         mxc_request_iomux(MX53_PIN_SD1_DATA1,
 160                                                 IOMUX_CONFIG_ALT0);
 161                         mxc_request_iomux(MX53_PIN_SD1_DATA2,
 162                                                 IOMUX_CONFIG_ALT0);
 163                         mxc_request_iomux(MX53_PIN_SD1_DATA3,
 164                                                 IOMUX_CONFIG_ALT0);
 165                         mxc_request_iomux(MX53_PIN_EIM_DA13,
 166                                                 IOMUX_CONFIG_ALT1);
 167
 168                         mxc_iomux_set_pad(MX53_PIN_SD1_CMD,
 169                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 170                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 171                                 PAD_CTL_HYS_ENABLE | PAD_CTL_100K_PU);
 172                         mxc_iomux_set_pad(MX53_PIN_SD1_CLK,
 173                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 174                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU |
 175                                 PAD_CTL_DRV_HIGH);
 176                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA0,
 177                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 178                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 179                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 180                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA1,
 181                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 182                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 183                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 184                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA2,
 185                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 186                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 187                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 188                         mxc_iomux_set_pad(MX53_PIN_SD1_DATA3,
 189                                 PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH |
 190                                 PAD_CTL_PUE_PULL | PAD_CTL_PKE_ENABLE |
 191                                 PAD_CTL_HYS_ENABLE | PAD_CTL_47K_PU);
 192                         break;
 193
 194                 default:
 195                         printf("Warning: you configured more ESDHC controller"
 196                                 "(%d) as supported by the board(1)\n",
 197                                 CONFIG_SYS_FSL_ESDHC_NUM);
 198                         return status;
 199                 }
 200                 status |= fsl_esdhc_initialize(bis, &esdhc_cfg[index]);
 201         }
 202
 203         return status;
 204 }
 205 #endif
 206
 207 int board_early_init_f(void)
 208 {
 209         setup_iomux_uart();
 210         setup_iomux_fec();
 211
 212         return 0;
 213 }
 214
 215 int board_init(void)
 216 {
 217         gd->bd->bi_arch_number = MACH_TYPE_MX53_SMD;
 218         /* address of boot parameters */
 219         gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 220
 221         return 0;
 222 }
 223
 224 int checkboard(void)
 225 {
 226         puts("Board: MX53SMD\n");
 227
 228         return 0;
 229 }