board/freescale/mx6qsabrelite/mx6qsabrelite.c

   1 /*
   2  * Copyright (C) 2010-2011 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <asm/io.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/imx-regs.h>
  27 #include <asm/arch/iomux.h>
  28 #include <asm/arch/mx6x_pins.h>
  29 #include <asm/errno.h>
  30 #include <asm/gpio.h>
  31 #include <asm/imx-common/iomux-v3.h>
  32 #include <asm/imx-common/mxc_i2c.h>
  33 #include <asm/imx-common/boot_mode.h>
  34 #include <mmc.h>
  35 #include <fsl_esdhc.h>
  36 #include <micrel.h>
  37 #include <miiphy.h>
  38 #include <netdev.h>
  39 #include <linux/fb.h>
  40 #include <ipu_pixfmt.h>
  41 #include <asm/arch/crm_regs.h>
  42 #include <asm/arch/mxc_hdmi.h>
  43 #include <i2c.h>
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |            \
  48        PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  49        PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  50
  51 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  52        PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  53        PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  54
  55 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  56         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  57         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  58
  59 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  60         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  61         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  62
  63 #define BUTTON_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |            \
  64         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  65         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  66
  67 #define I2C_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_PUE |            \
  68         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  69         PAD_CTL_DSE_40ohm | PAD_CTL_HYS |                       \
  70         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  71
  72 int dram_init(void)
  73 {
  74        gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  75
  76        return 0;
  77 }
  78
  79 iomux_v3_cfg_t const uart1_pads[] = {
  80         MX6Q_PAD_SD3_DAT6__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  81         MX6Q_PAD_SD3_DAT7__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  82 };
  83
  84 iomux_v3_cfg_t const uart2_pads[] = {
  85        MX6Q_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  86        MX6Q_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
  87 };
  88
  89 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
  90
  91 /* I2C1, SGTL5000 */
  92 struct i2c_pads_info i2c_pad_info0 = {
  93         .scl = {
  94                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
  95                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO_3_21 | PC,
  96                 .gp = IMX_GPIO_NR(3, 21)
  97         },
  98         .sda = {
  99                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 100                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO_3_28 | PC,
 101                 .gp = IMX_GPIO_NR(3, 28)
 102         }
 103 };
 104
 105 /* I2C2 Camera, MIPI */
 106 struct i2c_pads_info i2c_pad_info1 = {
 107         .scl = {
 108                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 109                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO_4_12 | PC,
 110                 .gp = IMX_GPIO_NR(4, 12)
 111         },
 112         .sda = {
 113                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 114                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO_4_13 | PC,
 115                 .gp = IMX_GPIO_NR(4, 13)
 116         }
 117 };
 118
 119 /* I2C3, J15 - RGB connector */
 120 struct i2c_pads_info i2c_pad_info2 = {
 121         .scl = {
 122                 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL | PC,
 123                 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO_1_5 | PC,
 124                 .gp = IMX_GPIO_NR(1, 5)
 125         },
 126         .sda = {
 127                 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA | PC,
 128                 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO_7_11 | PC,
 129                 .gp = IMX_GPIO_NR(7, 11)
 130         }
 131 };
 132
 133 iomux_v3_cfg_t const usdhc3_pads[] = {
 134        MX6Q_PAD_SD3_CLK__USDHC3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 135        MX6Q_PAD_SD3_CMD__USDHC3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 136        MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 137        MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 138        MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 139        MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 140        MX6Q_PAD_SD3_DAT5__GPIO_7_0    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 141 };
 142
 143 iomux_v3_cfg_t const usdhc4_pads[] = {
 144        MX6Q_PAD_SD4_CLK__USDHC4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 145        MX6Q_PAD_SD4_CMD__USDHC4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 146        MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 147        MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 148        MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 149        MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 150        MX6Q_PAD_NANDF_D6__GPIO_2_6    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 151 };
 152
 153 iomux_v3_cfg_t const enet_pads1[] = {
 154         MX6Q_PAD_ENET_MDIO__ENET_MDIO           | MUX_PAD_CTRL(ENET_PAD_CTRL),
 155         MX6Q_PAD_ENET_MDC__ENET_MDC             | MUX_PAD_CTRL(ENET_PAD_CTRL),
 156         MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 157         MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 158         MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 159         MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 160         MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 161         MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
 162         MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 163         /* pin 35 - 1 (PHY_AD2) on reset */
 164         MX6Q_PAD_RGMII_RXC__GPIO_6_30           | MUX_PAD_CTRL(NO_PAD_CTRL),
 165         /* pin 32 - 1 - (MODE0) all */
 166         MX6Q_PAD_RGMII_RD0__GPIO_6_25           | MUX_PAD_CTRL(NO_PAD_CTRL),
 167         /* pin 31 - 1 - (MODE1) all */
 168         MX6Q_PAD_RGMII_RD1__GPIO_6_27           | MUX_PAD_CTRL(NO_PAD_CTRL),
 169         /* pin 28 - 1 - (MODE2) all */
 170         MX6Q_PAD_RGMII_RD2__GPIO_6_28           | MUX_PAD_CTRL(NO_PAD_CTRL),
 171         /* pin 27 - 1 - (MODE3) all */
 172         MX6Q_PAD_RGMII_RD3__GPIO_6_29           | MUX_PAD_CTRL(NO_PAD_CTRL),
 173         /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */
 174         MX6Q_PAD_RGMII_RX_CTL__GPIO_6_24        | MUX_PAD_CTRL(NO_PAD_CTRL),
 175         /* pin 42 PHY nRST */
 176         MX6Q_PAD_EIM_D23__GPIO_3_23             | MUX_PAD_CTRL(NO_PAD_CTRL),
 177 };
 178
 179 iomux_v3_cfg_t const enet_pads2[] = {
 180         MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 181         MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 182         MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 183         MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 184         MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3      | MUX_PAD_CTRL(ENET_PAD_CTRL),
 185         MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL     | MUX_PAD_CTRL(ENET_PAD_CTRL),
 186 };
 187
 188 /* Button assignments for J14 */
 189 static iomux_v3_cfg_t const button_pads[] = {
 190         /* Menu */
 191         MX6Q_PAD_NANDF_D1__GPIO_2_1     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 192         /* Back */
 193         MX6Q_PAD_NANDF_D2__GPIO_2_2     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 194         /* Labelled Search (mapped to Power under Android) */
 195         MX6Q_PAD_NANDF_D3__GPIO_2_3     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 196         /* Home */
 197         MX6Q_PAD_NANDF_D4__GPIO_2_4     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 198         /* Volume Down */
 199         MX6Q_PAD_GPIO_19__GPIO_4_5      | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 200         /* Volume Up */
 201         MX6Q_PAD_GPIO_18__GPIO_7_13     | MUX_PAD_CTRL(BUTTON_PAD_CTRL),
 202 };
 203
 204 static void setup_iomux_enet(void)
 205 {
 206         gpio_direction_output(IMX_GPIO_NR(3, 23), 0);
 207         gpio_direction_output(IMX_GPIO_NR(6, 30), 1);
 208         gpio_direction_output(IMX_GPIO_NR(6, 25), 1);
 209         gpio_direction_output(IMX_GPIO_NR(6, 27), 1);
 210         gpio_direction_output(IMX_GPIO_NR(6, 28), 1);
 211         gpio_direction_output(IMX_GPIO_NR(6, 29), 1);
 212         imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1));
 213         gpio_direction_output(IMX_GPIO_NR(6, 24), 1);
 214
 215         /* Need delay 10ms according to KSZ9021 spec */
 216         udelay(1000 * 10);
 217         gpio_set_value(IMX_GPIO_NR(3, 23), 1);
 218
 219         imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2));
 220 }
 221
 222 iomux_v3_cfg_t const usb_pads[] = {
 223         MX6Q_PAD_GPIO_17__GPIO_7_12 | MUX_PAD_CTRL(NO_PAD_CTRL),
 224 };
 225
 226 static void setup_iomux_uart(void)
 227 {
 228         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 229        imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 230 }
 231
 232 #ifdef CONFIG_USB_EHCI_MX6
 233 int board_ehci_hcd_init(int port)
 234 {
 235         imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
 236
 237         /* Reset USB hub */
 238         gpio_direction_output(IMX_GPIO_NR(7, 12), 0);
 239         mdelay(2);
 240         gpio_set_value(IMX_GPIO_NR(7, 12), 1);
 241
 242         return 0;
 243 }
 244 #endif
 245
 246 #ifdef CONFIG_FSL_ESDHC
 247 struct fsl_esdhc_cfg usdhc_cfg[2] = {
 248        {USDHC3_BASE_ADDR},
 249        {USDHC4_BASE_ADDR},
 250 };
 251
 252 int board_mmc_getcd(struct mmc *mmc)
 253 {
 254        struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 255        int ret;
 256
 257        if (cfg->esdhc_base == USDHC3_BASE_ADDR) {
 258                 gpio_direction_input(IMX_GPIO_NR(7, 0));
 259                 ret = !gpio_get_value(IMX_GPIO_NR(7, 0));
 260        } else {
 261                 gpio_direction_input(IMX_GPIO_NR(2, 6));
 262                 ret = !gpio_get_value(IMX_GPIO_NR(2, 6));
 263        }
 264
 265        return ret;
 266 }
 267
 268 int board_mmc_init(bd_t *bis)
 269 {
 270        s32 status = 0;
 271        u32 index = 0;
 272
 273         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 274         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 275
 276        for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
 277                switch (index) {
 278                case 0:
 279                        imx_iomux_v3_setup_multiple_pads(
 280                                usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 281                        break;
 282                case 1:
 283                        imx_iomux_v3_setup_multiple_pads(
 284                                usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 285                        break;
 286                default:
 287                        printf("Warning: you configured more USDHC controllers"
 288                                "(%d) then supported by the board (%d)\n",
 289                                index + 1, CONFIG_SYS_FSL_USDHC_NUM);
 290                        return status;
 291                }
 292
 293                status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
 294        }
 295
 296        return status;
 297 }
 298 #endif
 299
 300 u32 get_board_rev(void)
 301 {
 302         return 0x63000 ;
 303 }
 304
 305 #ifdef CONFIG_MXC_SPI
 306 iomux_v3_cfg_t const ecspi1_pads[] = {
 307         /* SS1 */
 308         MX6Q_PAD_EIM_D19__GPIO_3_19   | MUX_PAD_CTRL(SPI_PAD_CTRL),
 309         MX6Q_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 310         MX6Q_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 311         MX6Q_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 312 };
 313
 314 void setup_spi(void)
 315 {
 316         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 317         imx_iomux_v3_setup_multiple_pads(ecspi1_pads,
 318                                          ARRAY_SIZE(ecspi1_pads));
 319 }
 320 #endif
 321
 322 int board_phy_config(struct phy_device *phydev)
 323 {
 324         /* min rx data delay */
 325         ksz9021_phy_extended_write(phydev,
 326                         MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, 0x0);
 327         /* min tx data delay */
 328         ksz9021_phy_extended_write(phydev,
 329                         MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, 0x0);
 330         /* max rx/tx clock delay, min rx/tx control */
 331         ksz9021_phy_extended_write(phydev,
 332                         MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, 0xf0f0);
 333         if (phydev->drv->config)
 334                 phydev->drv->config(phydev);
 335
 336         return 0;
 337 }
 338
 339 int board_eth_init(bd_t *bis)
 340 {
 341         int ret;
 342
 343         setup_iomux_enet();
 344
 345         ret = cpu_eth_init(bis);
 346         if (ret)
 347                 printf("FEC MXC: %s:failed\n", __func__);
 348
 349         return 0;
 350 }
 351
 352 static void setup_buttons(void)
 353 {
 354         imx_iomux_v3_setup_multiple_pads(button_pads,
 355                                          ARRAY_SIZE(button_pads));
 356 }
 357
 358 #ifdef CONFIG_CMD_SATA
 359
 360 int setup_sata(void)
 361 {
 362         struct iomuxc_base_regs *const iomuxc_regs
 363                 = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
 364         int ret = enable_sata_clock();
 365         if (ret)
 366                 return ret;
 367
 368         clrsetbits_le32(&iomuxc_regs->gpr[13],
 369                         IOMUXC_GPR13_SATA_MASK,
 370                         IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
 371                         |IOMUXC_GPR13_SATA_PHY_7_SATA2M
 372                         |IOMUXC_GPR13_SATA_SPEED_3G
 373                         |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
 374                         |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
 375                         |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
 376                         |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
 377                         |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
 378                         |IOMUXC_GPR13_SATA_PHY_1_SLOW);
 379
 380         return 0;
 381 }
 382 #endif
 383
 384 #if defined(CONFIG_VIDEO_IPUV3)
 385
 386 static iomux_v3_cfg_t const backlight_pads[] = {
 387         /* Backlight on RGB connector: J15 */
 388         MX6Q_PAD_SD1_DAT3__GPIO_1_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
 389 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(1, 21)
 390
 391         /* Backlight on LVDS connector: J6 */
 392         MX6Q_PAD_SD1_CMD__GPIO_1_18 | MUX_PAD_CTRL(NO_PAD_CTRL),
 393 #define LVDS_BACKLIGHT_GP IMX_GPIO_NR(1, 18)
 394 };
 395
 396 static iomux_v3_cfg_t const rgb_pads[] = {
 397         MX6Q_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
 398         MX6Q_PAD_DI0_PIN15__IPU1_DI0_PIN15,
 399         MX6Q_PAD_DI0_PIN2__IPU1_DI0_PIN2,
 400         MX6Q_PAD_DI0_PIN3__IPU1_DI0_PIN3,
 401         MX6Q_PAD_DI0_PIN4__GPIO_4_20,
 402         MX6Q_PAD_DISP0_DAT0__IPU1_DISP0_DAT_0,
 403         MX6Q_PAD_DISP0_DAT1__IPU1_DISP0_DAT_1,
 404         MX6Q_PAD_DISP0_DAT2__IPU1_DISP0_DAT_2,
 405         MX6Q_PAD_DISP0_DAT3__IPU1_DISP0_DAT_3,
 406         MX6Q_PAD_DISP0_DAT4__IPU1_DISP0_DAT_4,
 407         MX6Q_PAD_DISP0_DAT5__IPU1_DISP0_DAT_5,
 408         MX6Q_PAD_DISP0_DAT6__IPU1_DISP0_DAT_6,
 409         MX6Q_PAD_DISP0_DAT7__IPU1_DISP0_DAT_7,
 410         MX6Q_PAD_DISP0_DAT8__IPU1_DISP0_DAT_8,
 411         MX6Q_PAD_DISP0_DAT9__IPU1_DISP0_DAT_9,
 412         MX6Q_PAD_DISP0_DAT10__IPU1_DISP0_DAT_10,
 413         MX6Q_PAD_DISP0_DAT11__IPU1_DISP0_DAT_11,
 414         MX6Q_PAD_DISP0_DAT12__IPU1_DISP0_DAT_12,
 415         MX6Q_PAD_DISP0_DAT13__IPU1_DISP0_DAT_13,
 416         MX6Q_PAD_DISP0_DAT14__IPU1_DISP0_DAT_14,
 417         MX6Q_PAD_DISP0_DAT15__IPU1_DISP0_DAT_15,
 418         MX6Q_PAD_DISP0_DAT16__IPU1_DISP0_DAT_16,
 419         MX6Q_PAD_DISP0_DAT17__IPU1_DISP0_DAT_17,
 420         MX6Q_PAD_DISP0_DAT18__IPU1_DISP0_DAT_18,
 421         MX6Q_PAD_DISP0_DAT19__IPU1_DISP0_DAT_19,
 422         MX6Q_PAD_DISP0_DAT20__IPU1_DISP0_DAT_20,
 423         MX6Q_PAD_DISP0_DAT21__IPU1_DISP0_DAT_21,
 424         MX6Q_PAD_DISP0_DAT22__IPU1_DISP0_DAT_22,
 425         MX6Q_PAD_DISP0_DAT23__IPU1_DISP0_DAT_23,
 426 };
 427
 428 struct display_info_t {
 429         int     bus;
 430         int     addr;
 431         int     pixfmt;
 432         int     (*detect)(struct display_info_t const *dev);
 433         void    (*enable)(struct display_info_t const *dev);
 434         struct  fb_videomode mode;
 435 };
 436
 437
 438 static int detect_hdmi(struct display_info_t const *dev)
 439 {
 440         return __raw_readb(HDMI_ARB_BASE_ADDR+HDMI_PHY_STAT0) & HDMI_PHY_HPD;
 441 }
 442
 443 static void enable_hdmi(struct display_info_t const *dev)
 444 {
 445         u8 reg;
 446         printf("%s: setup HDMI monitor\n", __func__);
 447         reg = __raw_readb(
 448                         HDMI_ARB_BASE_ADDR
 449                         +HDMI_PHY_CONF0);
 450         reg |= HDMI_PHY_CONF0_PDZ_MASK;
 451         __raw_writeb(reg,
 452                      HDMI_ARB_BASE_ADDR
 453                         +HDMI_PHY_CONF0);
 454         udelay(3000);
 455         reg |= HDMI_PHY_CONF0_ENTMDS_MASK;
 456         __raw_writeb(reg,
 457                      HDMI_ARB_BASE_ADDR
 458                         +HDMI_PHY_CONF0);
 459         udelay(3000);
 460         reg |= HDMI_PHY_CONF0_GEN2_TXPWRON_MASK;
 461         __raw_writeb(reg,
 462                      HDMI_ARB_BASE_ADDR
 463                         +HDMI_PHY_CONF0);
 464         __raw_writeb(HDMI_MC_PHYRSTZ_ASSERT,
 465                      HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
 466 }
 467
 468 static int detect_i2c(struct display_info_t const *dev)
 469 {
 470         return ((0 == i2c_set_bus_num(dev->bus))
 471                 &&
 472                 (0 == i2c_probe(dev->addr)));
 473 }
 474
 475 static void enable_lvds(struct display_info_t const *dev)
 476 {
 477         struct iomuxc *iomux = (struct iomuxc *)
 478                                 IOMUXC_BASE_ADDR;
 479         u32 reg = readl(&iomux->gpr[2]);
 480         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 481         writel(reg, &iomux->gpr[2]);
 482         gpio_direction_output(LVDS_BACKLIGHT_GP, 1);
 483 }
 484
 485 static void enable_rgb(struct display_info_t const *dev)
 486 {
 487         imx_iomux_v3_setup_multiple_pads(
 488                 rgb_pads,
 489                  ARRAY_SIZE(rgb_pads));
 490         gpio_direction_output(RGB_BACKLIGHT_GP, 1);
 491 }
 492
 493 static struct display_info_t const displays[] = {{
 494         .bus    = -1,
 495         .addr   = 0,
 496         .pixfmt = IPU_PIX_FMT_RGB24,
 497         .detect = detect_hdmi,
 498         .enable = enable_hdmi,
 499         .mode   = {
 500                 .name           = "HDMI",
 501                 .refresh        = 60,
 502                 .xres           = 1024,
 503                 .yres           = 768,
 504                 .pixclock       = 15385,
 505                 .left_margin    = 220,
 506                 .right_margin   = 40,
 507                 .upper_margin   = 21,
 508                 .lower_margin   = 7,
 509                 .hsync_len      = 60,
 510                 .vsync_len      = 10,
 511                 .sync           = FB_SYNC_EXT,
 512                 .vmode          = FB_VMODE_NONINTERLACED
 513 } }, {
 514         .bus    = 2,
 515         .addr   = 0x4,
 516         .pixfmt = IPU_PIX_FMT_LVDS666,
 517         .detect = detect_i2c,
 518         .enable = enable_lvds,
 519         .mode   = {
 520                 .name           = "Hannstar-XGA",
 521                 .refresh        = 60,
 522                 .xres           = 1024,
 523                 .yres           = 768,
 524                 .pixclock       = 15385,
 525                 .left_margin    = 220,
 526                 .right_margin   = 40,
 527                 .upper_margin   = 21,
 528                 .lower_margin   = 7,
 529                 .hsync_len      = 60,
 530                 .vsync_len      = 10,
 531                 .sync           = FB_SYNC_EXT,
 532                 .vmode          = FB_VMODE_NONINTERLACED
 533 } }, {
 534         .bus    = 2,
 535         .addr   = 0x38,
 536         .pixfmt = IPU_PIX_FMT_LVDS666,
 537         .detect = detect_i2c,
 538         .enable = enable_lvds,
 539         .mode   = {
 540                 .name           = "wsvga-lvds",
 541                 .refresh        = 60,
 542                 .xres           = 1024,
 543                 .yres           = 600,
 544                 .pixclock       = 15385,
 545                 .left_margin    = 220,
 546                 .right_margin   = 40,
 547                 .upper_margin   = 21,
 548                 .lower_margin   = 7,
 549                 .hsync_len      = 60,
 550                 .vsync_len      = 10,
 551                 .sync           = FB_SYNC_EXT,
 552                 .vmode          = FB_VMODE_NONINTERLACED
 553 } }, {
 554         .bus    = 2,
 555         .addr   = 0x48,
 556         .pixfmt = IPU_PIX_FMT_RGB666,
 557         .detect = detect_i2c,
 558         .enable = enable_rgb,
 559         .mode   = {
 560                 .name           = "wvga-rgb",
 561                 .refresh        = 57,
 562                 .xres           = 800,
 563                 .yres           = 480,
 564                 .pixclock       = 37037,
 565                 .left_margin    = 40,
 566                 .right_margin   = 60,
 567                 .upper_margin   = 10,
 568                 .lower_margin   = 10,
 569                 .hsync_len      = 20,
 570                 .vsync_len      = 10,
 571                 .sync           = 0,
 572                 .vmode          = FB_VMODE_NONINTERLACED
 573 } } };
 574
 575 int board_video_skip(void)
 576 {
 577         int i;
 578         int ret;
 579         char const *panel = getenv("panel");
 580         if (!panel) {
 581                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 582                         struct display_info_t const *dev = displays+i;
 583                         if (dev->detect(dev)) {
 584                                 panel = dev->mode.name;
 585                                 printf("auto-detected panel %s\n", panel);
 586                                 break;
 587                         }
 588                 }
 589                 if (!panel) {
 590                         panel = displays[0].mode.name;
 591                         printf("No panel detected: default to %s\n", panel);
 592                 }
 593         } else {
 594                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 595                         if (!strcmp(panel, displays[i].mode.name))
 596                                 break;
 597                 }
 598         }
 599         if (i < ARRAY_SIZE(displays)) {
 600                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 601                                     displays[i].pixfmt);
 602                 if (!ret) {
 603                         displays[i].enable(displays+i);
 604                         printf("Display: %s (%ux%u)\n",
 605                                displays[i].mode.name,
 606                                displays[i].mode.xres,
 607                                displays[i].mode.yres);
 608                 } else
 609                         printf("LCD %s cannot be configured: %d\n",
 610                                displays[i].mode.name, ret);
 611         } else {
 612                 printf("unsupported panel %s\n", panel);
 613                 ret = -EINVAL;
 614         }
 615         return (0 != ret);
 616 }
 617
 618 static void setup_display(void)
 619 {
 620         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 621         struct anatop_regs *anatop = (struct anatop_regs *)ANATOP_BASE_ADDR;
 622         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 623
 624         int reg;
 625
 626         /* Turn on LDB0,IPU,IPU DI0 clocks */
 627         reg = __raw_readl(&mxc_ccm->CCGR3);
 628         reg |=   MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET
 629                 |MXC_CCM_CCGR3_LDB_DI0_MASK;
 630         writel(reg, &mxc_ccm->CCGR3);
 631
 632         /* Turn on HDMI PHY clock */
 633         reg = __raw_readl(&mxc_ccm->CCGR2);
 634         reg |=  MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK
 635                |MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK;
 636         writel(reg, &mxc_ccm->CCGR2);
 637
 638         /* clear HDMI PHY reset */
 639         __raw_writeb(HDMI_MC_PHYRSTZ_DEASSERT,
 640                      HDMI_ARB_BASE_ADDR+HDMI_MC_PHYRSTZ);
 641
 642         /* set PFD1_FRAC to 0x13 == 455 MHz (480*18)/0x13 */
 643         writel(ANATOP_PFD_480_PFD1_FRAC_MASK, &anatop->pfd_480_clr);
 644         writel(0x13<<ANATOP_PFD_480_PFD1_FRAC_SHIFT, &anatop->pfd_480_set);
 645
 646         /* set LDB0, LDB1 clk select to 011/011 */
 647         reg = readl(&mxc_ccm->cs2cdr);
 648         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 649                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 650         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 651               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 652         writel(reg, &mxc_ccm->cs2cdr);
 653
 654         reg = readl(&mxc_ccm->cscmr2);
 655         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 656         writel(reg, &mxc_ccm->cscmr2);
 657
 658         reg = readl(&mxc_ccm->chsccdr);
 659         reg &= ~(MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK
 660                 |MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK
 661                 |MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK);
 662         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 663                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET)
 664               |(CHSCCDR_PODF_DIVIDE_BY_3
 665                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET)
 666               |(CHSCCDR_IPU_PRE_CLK_540M_PFD
 667                 <<MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
 668         writel(reg, &mxc_ccm->chsccdr);
 669
 670         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 671              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 672              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 673              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 674              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 675              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 676              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 677              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 678              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 679         writel(reg, &iomux->gpr[2]);
 680
 681         reg = readl(&iomux->gpr[3]);
 682         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 683             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 684                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 685         writel(reg, &iomux->gpr[3]);
 686
 687         /* backlights off until needed */
 688         imx_iomux_v3_setup_multiple_pads(backlight_pads,
 689                                          ARRAY_SIZE(backlight_pads));
 690         gpio_direction_input(LVDS_BACKLIGHT_GP);
 691         gpio_direction_input(RGB_BACKLIGHT_GP);
 692 }
 693 #endif
 694
 695 int board_early_init_f(void)
 696 {
 697         setup_iomux_uart();
 698         setup_buttons();
 699
 700 #if defined(CONFIG_VIDEO_IPUV3)
 701         setup_display();
 702 #endif
 703         return 0;
 704 }
 705
 706 /*
 707  * Do not overwrite the console
 708  * Use always serial for U-Boot console
 709  */
 710 int overwrite_console(void)
 711 {
 712         return 1;
 713 }
 714
 715 int board_init(void)
 716 {
 717        /* address of boot parameters */
 718        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 719
 720 #ifdef CONFIG_MXC_SPI
 721         setup_spi();
 722 #endif
 723         setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0);
 724         setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
 725         setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2);
 726
 727 #ifdef CONFIG_CMD_SATA
 728         setup_sata();
 729 #endif
 730
 731        return 0;
 732 }
 733
 734 int checkboard(void)
 735 {
 736        puts("Board: MX6Q-Sabre Lite\n");
 737
 738        return 0;
 739 }
 740
 741 struct button_key {
 742         char const      *name;
 743         unsigned        gpnum;
 744         char            ident;
 745 };
 746
 747 static struct button_key const buttons[] = {
 748         {"back",        IMX_GPIO_NR(2, 2),      'B'},
 749         {"home",        IMX_GPIO_NR(2, 4),      'H'},
 750         {"menu",        IMX_GPIO_NR(2, 1),      'M'},
 751         {"search",      IMX_GPIO_NR(2, 3),      'S'},
 752         {"volup",       IMX_GPIO_NR(7, 13),     'V'},
 753         {"voldown",     IMX_GPIO_NR(4, 5),      'v'},
 754 };
 755
 756 /*
 757  * generate a null-terminated string containing the buttons pressed
 758  * returns number of keys pressed
 759  */
 760 static int read_keys(char *buf)
 761 {
 762         int i, numpressed = 0;
 763         for (i = 0; i < ARRAY_SIZE(buttons); i++) {
 764                 if (!gpio_get_value(buttons[i].gpnum))
 765                         buf[numpressed++] = buttons[i].ident;
 766         }
 767         buf[numpressed] = '\0';
 768         return numpressed;
 769 }
 770
 771 static int do_kbd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
 772 {
 773         char envvalue[ARRAY_SIZE(buttons)+1];
 774         int numpressed = read_keys(envvalue);
 775         setenv("keybd", envvalue);
 776         return numpressed == 0;
 777 }
 778
 779 U_BOOT_CMD(
 780         kbd, 1, 1, do_kbd,
 781         "Tests for keypresses, sets 'keybd' environment variable",
 782         "Returns 0 (true) to shell if key is pressed."
 783 );
 784
 785 #ifdef CONFIG_PREBOOT
 786 static char const kbd_magic_prefix[] = "key_magic";
 787 static char const kbd_command_prefix[] = "key_cmd";
 788
 789 static void preboot_keys(void)
 790 {
 791         int numpressed;
 792         char keypress[ARRAY_SIZE(buttons)+1];
 793         numpressed = read_keys(keypress);
 794         if (numpressed) {
 795                 char *kbd_magic_keys = getenv("magic_keys");
 796                 char *suffix;
 797                 /*
 798                  * loop over all magic keys
 799                  */
 800                 for (suffix = kbd_magic_keys; *suffix; ++suffix) {
 801                         char *keys;
 802                         char magic[sizeof(kbd_magic_prefix) + 1];
 803                         sprintf(magic, "%s%c", kbd_magic_prefix, *suffix);
 804                         keys = getenv(magic);
 805                         if (keys) {
 806                                 if (!strcmp(keys, keypress))
 807                                         break;
 808                         }
 809                 }
 810                 if (*suffix) {
 811                         char cmd_name[sizeof(kbd_command_prefix) + 1];
 812                         char *cmd;
 813                         sprintf(cmd_name, "%s%c", kbd_command_prefix, *suffix);
 814                         cmd = getenv(cmd_name);
 815                         if (cmd) {
 816                                 setenv("preboot", cmd);
 817                                 return;
 818                         }
 819                 }
 820         }
 821 }
 822 #endif
 823
 824 #ifdef CONFIG_CMD_BMODE
 825 static const struct boot_mode board_boot_modes[] = {
 826         /* 4 bit bus width */
 827         {"mmc0",        MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 828         {"mmc1",        MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 829         {NULL,          0},
 830 };
 831 #endif
 832
 833 int misc_init_r(void)
 834 {
 835 #ifdef CONFIG_PREBOOT
 836         preboot_keys();
 837 #endif
 838
 839 #ifdef CONFIG_CMD_BMODE
 840         add_board_boot_modes(board_boot_modes);
 841 #endif
 842         return 0;
 843 }