2 * Copyright (C) 2012 Freescale Semiconductor, Inc.
4 * Author: Fabio Estevam <fabio.estevam@freescale.com>
6 * SPDX-License-Identifier: GPL-2.0+
9 #include <asm/arch/clock.h>
10 #include <asm/arch/imx-regs.h>
11 #include <asm/arch/iomux.h>
12 #include <asm/arch/mx6-pins.h>
13 #include <asm/errno.h>
15 #include <asm/imx-common/iomux-v3.h>
16 #include <asm/imx-common/boot_mode.h>
17 #include <asm/imx-common/video.h>
19 #include <fsl_esdhc.h>
22 #include <asm/arch/mxc_hdmi.h>
23 #include <asm/arch/crm_regs.h>
25 #include <asm/arch/sys_proto.h>
26 DECLARE_GLOBAL_DATA_PTR;
28 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
29 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
30 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
32 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \
33 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
34 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
39 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
40 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
44 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
49 iomux_v3_cfg_t const uart1_pads[] = {
50 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
51 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
54 iomux_v3_cfg_t const enet_pads[] = {
55 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
56 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
57 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
58 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
59 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
60 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
61 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
62 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
63 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),
64 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),
65 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
66 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
67 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),
68 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),
69 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
70 /* AR8031 PHY Reset */
71 MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL),
74 static void setup_iomux_enet(void)
76 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
78 /* Reset AR8031 PHY */
79 gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
81 gpio_set_value(IMX_GPIO_NR(1, 25), 1);
84 iomux_v3_cfg_t const usdhc2_pads[] = {
85 MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86 MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87 MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
88 MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
89 MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
90 MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_NANDF_D4__SD2_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_NANDF_D5__SD2_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_NANDF_D6__SD2_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_NANDF_D7__SD2_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
98 iomux_v3_cfg_t const usdhc3_pads[] = {
99 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
100 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
101 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
102 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108 MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
109 MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
112 iomux_v3_cfg_t const usdhc4_pads[] = {
113 MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 iomux_v3_cfg_t const ecspi1_pads[] = {
126 MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
127 MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
128 MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
129 MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
132 static void setup_spi(void)
134 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
137 iomux_v3_cfg_t const pcie_pads[] = {
138 MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), /* POWER */
139 MX6_PAD_GPIO_17__GPIO7_IO12 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */
142 static void setup_pcie(void)
144 imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
147 iomux_v3_cfg_t const di0_pads[] = {
148 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */
149 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */
150 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */
153 static void setup_iomux_uart(void)
155 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
158 #ifdef CONFIG_FSL_ESDHC
159 struct fsl_esdhc_cfg usdhc_cfg[3] = {
165 #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 2)
166 #define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)
168 int board_mmc_getcd(struct mmc *mmc)
170 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
173 switch (cfg->esdhc_base) {
174 case USDHC2_BASE_ADDR:
175 ret = !gpio_get_value(USDHC2_CD_GPIO);
177 case USDHC3_BASE_ADDR:
178 ret = !gpio_get_value(USDHC3_CD_GPIO);
180 case USDHC4_BASE_ADDR:
181 ret = 1; /* eMMC/uSDHC4 is always present */
188 int board_mmc_init(bd_t *bis)
194 * According to the board_mmc_init() the following map is done:
195 * (U-boot device node) (Physical Port)
200 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
203 imx_iomux_v3_setup_multiple_pads(
204 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
205 gpio_direction_input(USDHC2_CD_GPIO);
206 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
209 imx_iomux_v3_setup_multiple_pads(
210 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
211 gpio_direction_input(USDHC3_CD_GPIO);
212 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
215 imx_iomux_v3_setup_multiple_pads(
216 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
217 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
220 printf("Warning: you configured more USDHC controllers"
221 "(%d) then supported by the board (%d)\n",
222 i + 1, CONFIG_SYS_FSL_USDHC_NUM);
226 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
233 int mx6_rgmii_rework(struct phy_device *phydev)
237 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
238 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
239 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
240 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
242 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
245 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
247 /* introduce tx clock delay */
248 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
249 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
251 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
256 int board_phy_config(struct phy_device *phydev)
258 mx6_rgmii_rework(phydev);
260 if (phydev->drv->config)
261 phydev->drv->config(phydev);
266 #if defined(CONFIG_VIDEO_IPUV3)
268 static int detect_hdmi(struct display_info_t const *dev)
270 struct hdmi_regs *hdmi = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
271 return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
275 static void disable_lvds(struct display_info_t const *dev)
277 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
279 int reg = readl(&iomux->gpr[2]);
281 reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
282 IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
284 writel(reg, &iomux->gpr[2]);
287 static void do_enable_hdmi(struct display_info_t const *dev)
290 imx_enable_hdmi_phy();
293 static void enable_lvds(struct display_info_t const *dev)
295 struct iomuxc *iomux = (struct iomuxc *)
297 u32 reg = readl(&iomux->gpr[2]);
298 reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT |
299 IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT;
300 writel(reg, &iomux->gpr[2]);
303 struct display_info_t const displays[] = {{
306 .pixfmt = IPU_PIX_FMT_RGB666,
308 .enable = enable_lvds,
310 .name = "Hannstar-XGA",
322 .vmode = FB_VMODE_NONINTERLACED
326 .pixfmt = IPU_PIX_FMT_RGB24,
327 .detect = detect_hdmi,
328 .enable = do_enable_hdmi,
342 .vmode = FB_VMODE_NONINTERLACED
344 size_t display_count = ARRAY_SIZE(displays);
346 static void setup_display(void)
348 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
349 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
352 /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
353 imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
358 /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
359 reg = readl(&mxc_ccm->CCGR3);
360 reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
361 writel(reg, &mxc_ccm->CCGR3);
363 /* set LDB0, LDB1 clk select to 011/011 */
364 reg = readl(&mxc_ccm->cs2cdr);
365 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
366 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
367 reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
368 | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
369 writel(reg, &mxc_ccm->cs2cdr);
371 reg = readl(&mxc_ccm->cscmr2);
372 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
373 writel(reg, &mxc_ccm->cscmr2);
375 reg = readl(&mxc_ccm->chsccdr);
376 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
377 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
378 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
379 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
380 writel(reg, &mxc_ccm->chsccdr);
382 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
383 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
384 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
385 | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
386 | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
387 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
388 | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
389 | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
390 | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
391 writel(reg, &iomux->gpr[2]);
393 reg = readl(&iomux->gpr[3]);
394 reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
395 | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
396 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
397 << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
398 writel(reg, &iomux->gpr[3]);
400 #endif /* CONFIG_VIDEO_IPUV3 */
403 * Do not overwrite the console
404 * Use always serial for U-Boot console
406 int overwrite_console(void)
411 int board_eth_init(bd_t *bis)
416 return cpu_eth_init(bis);
419 int board_early_init_f(void)
422 #if defined(CONFIG_VIDEO_IPUV3)
431 /* address of boot parameters */
432 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
434 #ifdef CONFIG_MXC_SPI
441 #ifdef CONFIG_CMD_BMODE
442 static const struct boot_mode board_boot_modes[] = {
443 /* 4 bit bus width */
444 {"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
445 {"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
446 /* 8 bit bus width */
447 {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
452 int board_late_init(void)
454 #ifdef CONFIG_CMD_BMODE
455 add_board_boot_modes(board_boot_modes);
463 puts("Board: MX6-SabreSD\n");