board/freescale/mx6sabresd/mx6sabresd.c

   1 /*
   2  * Copyright (C) 2012 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Fabio Estevam <fabio.estevam@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <asm/arch/clock.h>
  10 #include <asm/arch/imx-regs.h>
  11 #include <asm/arch/iomux.h>
  12 #include <asm/arch/mx6-pins.h>
  13 #include <asm/errno.h>
  14 #include <asm/gpio.h>
  15 #include <asm/imx-common/iomux-v3.h>
  16 #include <asm/imx-common/boot_mode.h>
  17 #include <mmc.h>
  18 #include <fsl_esdhc.h>
  19 #include <miiphy.h>
  20 #include <netdev.h>
  21 #include <asm/arch/mxc_hdmi.h>
  22 #include <asm/arch/crm_regs.h>
  23 #include <linux/fb.h>
  24 #include <ipu_pixfmt.h>
  25 #include <asm/io.h>
  26 #include <asm/arch/sys_proto.h>
  27 DECLARE_GLOBAL_DATA_PTR;
  28
  29 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  30         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |                 \
  31         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  32
  33 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |                    \
  34         PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |                 \
  35         PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  36
  37 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                   \
  38         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  39
  40 int dram_init(void)
  41 {
  42         gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
  43
  44         return 0;
  45 }
  46
  47 iomux_v3_cfg_t const uart1_pads[] = {
  48         MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  49         MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  50 };
  51
  52 iomux_v3_cfg_t const enet_pads[] = {
  53         MX6_PAD_ENET_MDIO__ENET_MDIO            | MUX_PAD_CTRL(ENET_PAD_CTRL),
  54         MX6_PAD_ENET_MDC__ENET_MDC              | MUX_PAD_CTRL(ENET_PAD_CTRL),
  55         MX6_PAD_RGMII_TXC__RGMII_TXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  56         MX6_PAD_RGMII_TD0__RGMII_TD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  57         MX6_PAD_RGMII_TD1__RGMII_TD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  58         MX6_PAD_RGMII_TD2__RGMII_TD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  59         MX6_PAD_RGMII_TD3__RGMII_TD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  60         MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  61         MX6_PAD_ENET_REF_CLK__ENET_TX_CLK       | MUX_PAD_CTRL(ENET_PAD_CTRL),
  62         MX6_PAD_RGMII_RXC__RGMII_RXC    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  63         MX6_PAD_RGMII_RD0__RGMII_RD0    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  64         MX6_PAD_RGMII_RD1__RGMII_RD1    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  65         MX6_PAD_RGMII_RD2__RGMII_RD2    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  66         MX6_PAD_RGMII_RD3__RGMII_RD3    | MUX_PAD_CTRL(ENET_PAD_CTRL),
  67         MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL      | MUX_PAD_CTRL(ENET_PAD_CTRL),
  68         /* AR8031 PHY Reset */
  69         MX6_PAD_ENET_CRS_DV__GPIO1_IO25         | MUX_PAD_CTRL(NO_PAD_CTRL),
  70 };
  71
  72 static void setup_iomux_enet(void)
  73 {
  74         imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  75
  76         /* Reset AR8031 PHY */
  77         gpio_direction_output(IMX_GPIO_NR(1, 25) , 0);
  78         udelay(500);
  79         gpio_set_value(IMX_GPIO_NR(1, 25), 1);
  80 }
  81
  82 iomux_v3_cfg_t const usdhc2_pads[] = {
  83         MX6_PAD_SD2_CLK__SD2_CLK        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  84         MX6_PAD_SD2_CMD__SD2_CMD        | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  85         MX6_PAD_SD2_DAT0__SD2_DATA0     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  86         MX6_PAD_SD2_DAT1__SD2_DATA1     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  87         MX6_PAD_SD2_DAT2__SD2_DATA2     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  88         MX6_PAD_SD2_DAT3__SD2_DATA3     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  89         MX6_PAD_NANDF_D4__SD2_DATA4     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  90         MX6_PAD_NANDF_D5__SD2_DATA5     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  91         MX6_PAD_NANDF_D6__SD2_DATA6     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  92         MX6_PAD_NANDF_D7__SD2_DATA7     | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  93         MX6_PAD_NANDF_D2__GPIO2_IO02    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
  94 };
  95
  96 iomux_v3_cfg_t const usdhc3_pads[] = {
  97         MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  98         MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  99         MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 100         MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 101         MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 102         MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 103         MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 104         MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 105         MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 106         MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 107         MX6_PAD_NANDF_D0__GPIO2_IO00    | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 108 };
 109
 110 iomux_v3_cfg_t const usdhc4_pads[] = {
 111         MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 112         MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 113         MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 114         MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 115         MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 116         MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 117         MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 118         MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 119         MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 120         MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 121 };
 122
 123 static void setup_iomux_uart(void)
 124 {
 125         imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 126 }
 127
 128 #ifdef CONFIG_FSL_ESDHC
 129 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 130         {USDHC2_BASE_ADDR},
 131         {USDHC3_BASE_ADDR},
 132         {USDHC4_BASE_ADDR},
 133 };
 134
 135 #define USDHC2_CD_GPIO  IMX_GPIO_NR(2, 2)
 136 #define USDHC3_CD_GPIO  IMX_GPIO_NR(2, 0)
 137
 138 int board_mmc_getcd(struct mmc *mmc)
 139 {
 140         struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 141         int ret = 0;
 142
 143         switch (cfg->esdhc_base) {
 144         case USDHC2_BASE_ADDR:
 145                 ret = !gpio_get_value(USDHC2_CD_GPIO);
 146                 break;
 147         case USDHC3_BASE_ADDR:
 148                 ret = !gpio_get_value(USDHC3_CD_GPIO);
 149                 break;
 150         case USDHC4_BASE_ADDR:
 151                 ret = 1; /* eMMC/uSDHC4 is always present */
 152                 break;
 153         }
 154
 155         return ret;
 156 }
 157
 158 int board_mmc_init(bd_t *bis)
 159 {
 160         s32 status = 0;
 161         int i;
 162
 163         /*
 164          * According to the board_mmc_init() the following map is done:
 165          * (U-boot device node)    (Physical Port)
 166          * mmc0                    SD2
 167          * mmc1                    SD3
 168          * mmc2                    eMMC
 169          */
 170         for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 171                 switch (i) {
 172                 case 0:
 173                         imx_iomux_v3_setup_multiple_pads(
 174                                 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
 175                         gpio_direction_input(USDHC2_CD_GPIO);
 176                         usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 177                         break;
 178                 case 1:
 179                         imx_iomux_v3_setup_multiple_pads(
 180                                 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 181                         gpio_direction_input(USDHC3_CD_GPIO);
 182                         usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 183                         break;
 184                 case 2:
 185                         imx_iomux_v3_setup_multiple_pads(
 186                                 usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 187                         usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 188                         break;
 189                 default:
 190                         printf("Warning: you configured more USDHC controllers"
 191                                "(%d) then supported by the board (%d)\n",
 192                                i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 193                         return status;
 194                 }
 195
 196                 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 197         }
 198
 199         return status;
 200 }
 201 #endif
 202
 203 int mx6_rgmii_rework(struct phy_device *phydev)
 204 {
 205         unsigned short val;
 206
 207         /* To enable AR8031 ouput a 125MHz clk from CLK_25M */
 208         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
 209         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
 210         phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
 211
 212         val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
 213         val &= 0xffe3;
 214         val |= 0x18;
 215         phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
 216
 217         /* introduce tx clock delay */
 218         phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
 219         val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
 220         val |= 0x0100;
 221         phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
 222
 223         return 0;
 224 }
 225
 226 int board_phy_config(struct phy_device *phydev)
 227 {
 228         mx6_rgmii_rework(phydev);
 229
 230         if (phydev->drv->config)
 231                 phydev->drv->config(phydev);
 232
 233         return 0;
 234 }
 235
 236 #if defined(CONFIG_VIDEO_IPUV3)
 237 struct display_info_t {
 238         int     bus;
 239         int     addr;
 240         int     pixfmt;
 241         int     (*detect)(struct display_info_t const *dev);
 242         void    (*enable)(struct display_info_t const *dev);
 243         struct  fb_videomode mode;
 244 };
 245
 246 static int detect_hdmi(struct display_info_t const *dev)
 247 {
 248         struct hdmi_regs *hdmi  = (struct hdmi_regs *)HDMI_ARB_BASE_ADDR;
 249         return readb(&hdmi->phy_stat0) & HDMI_DVI_STAT;
 250 }
 251
 252
 253 static void disable_lvds(struct display_info_t const *dev)
 254 {
 255         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 256
 257         int reg = readl(&iomux->gpr[2]);
 258
 259         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
 260                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
 261
 262         writel(reg, &iomux->gpr[2]);
 263 }
 264
 265 static void do_enable_hdmi(struct display_info_t const *dev)
 266 {
 267         disable_lvds(dev);
 268         imx_enable_hdmi_phy();
 269 }
 270
 271 static void enable_lvds(struct display_info_t const *dev)
 272 {
 273         struct iomuxc *iomux = (struct iomuxc *)
 274                                 IOMUXC_BASE_ADDR;
 275         u32 reg = readl(&iomux->gpr[2]);
 276         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT |
 277                IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT;
 278         writel(reg, &iomux->gpr[2]);
 279 }
 280
 281 static struct display_info_t const displays[] = {{
 282         .bus    = -1,
 283         .addr   = 0,
 284         .pixfmt = IPU_PIX_FMT_LVDS666,
 285         .detect = NULL,
 286         .enable = enable_lvds,
 287         .mode   = {
 288                 .name           = "Hannstar-XGA",
 289                 .refresh        = 60,
 290                 .xres           = 1024,
 291                 .yres           = 768,
 292                 .pixclock       = 15385,
 293                 .left_margin    = 220,
 294                 .right_margin   = 40,
 295                 .upper_margin   = 21,
 296                 .lower_margin   = 7,
 297                 .hsync_len      = 60,
 298                 .vsync_len      = 10,
 299                 .sync           = FB_SYNC_EXT,
 300                 .vmode          = FB_VMODE_NONINTERLACED
 301 } }, {
 302         .bus    = -1,
 303         .addr   = 0,
 304         .pixfmt = IPU_PIX_FMT_RGB24,
 305         .detect = detect_hdmi,
 306         .enable = do_enable_hdmi,
 307         .mode   = {
 308                 .name           = "HDMI",
 309                 .refresh        = 60,
 310                 .xres           = 1024,
 311                 .yres           = 768,
 312                 .pixclock       = 15385,
 313                 .left_margin    = 220,
 314                 .right_margin   = 40,
 315                 .upper_margin   = 21,
 316                 .lower_margin   = 7,
 317                 .hsync_len      = 60,
 318                 .vsync_len      = 10,
 319                 .sync           = FB_SYNC_EXT,
 320                 .vmode          = FB_VMODE_NONINTERLACED
 321 } } };
 322
 323 int board_video_skip(void)
 324 {
 325         int i;
 326         int ret;
 327         char const *panel = getenv("panel");
 328         if (!panel) {
 329                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 330                         struct display_info_t const *dev = displays+i;
 331                         if (dev->detect && dev->detect(dev)) {
 332                                 panel = dev->mode.name;
 333                                 printf("auto-detected panel %s\n", panel);
 334                                 break;
 335                         }
 336                 }
 337                 if (!panel) {
 338                         panel = displays[0].mode.name;
 339                         printf("No panel detected: default to %s\n", panel);
 340                         i = 0;
 341                 }
 342         } else {
 343                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
 344                         if (!strcmp(panel, displays[i].mode.name))
 345                                 break;
 346                 }
 347         }
 348         if (i < ARRAY_SIZE(displays)) {
 349                 ret = ipuv3_fb_init(&displays[i].mode, 0,
 350                                     displays[i].pixfmt);
 351                 if (!ret) {
 352                         displays[i].enable(displays+i);
 353                         printf("Display: %s (%ux%u)\n",
 354                                displays[i].mode.name,
 355                                displays[i].mode.xres,
 356                                displays[i].mode.yres);
 357                 } else
 358                         printf("LCD %s cannot be configured: %d\n",
 359                                displays[i].mode.name, ret);
 360         } else {
 361                 printf("unsupported panel %s\n", panel);
 362                 return -EINVAL;
 363         }
 364
 365         return 0;
 366 }
 367
 368 static void setup_display(void)
 369 {
 370         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 371         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 372         int reg;
 373
 374         enable_ipu_clock();
 375         imx_setup_hdmi();
 376
 377         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
 378         reg = __raw_readl(&mxc_ccm->CCGR3);
 379         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
 380         writel(reg, &mxc_ccm->CCGR3);
 381
 382         /* set LDB0, LDB1 clk select to 011/011 */
 383         reg = readl(&mxc_ccm->cs2cdr);
 384         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 385                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 386         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 387               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 388         writel(reg, &mxc_ccm->cs2cdr);
 389
 390         reg = readl(&mxc_ccm->cscmr2);
 391         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
 392         writel(reg, &mxc_ccm->cscmr2);
 393
 394         reg = readl(&mxc_ccm->chsccdr);
 395         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 396                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 397         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 398                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
 399         writel(reg, &mxc_ccm->chsccdr);
 400
 401         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 402              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
 403              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 404              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 405              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 406              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 407              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 408              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
 409              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
 410         writel(reg, &iomux->gpr[2]);
 411
 412         reg = readl(&iomux->gpr[3]);
 413         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
 414                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
 415             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 416                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
 417         writel(reg, &iomux->gpr[3]);
 418 }
 419 #endif /* CONFIG_VIDEO_IPUV3 */
 420
 421 /*
 422  * Do not overwrite the console
 423  * Use always serial for U-Boot console
 424  */
 425 int overwrite_console(void)
 426 {
 427         return 1;
 428 }
 429
 430 int board_eth_init(bd_t *bis)
 431 {
 432         int ret;
 433
 434         setup_iomux_enet();
 435
 436         ret = cpu_eth_init(bis);
 437         if (ret)
 438                 printf("FEC MXC: %s:failed\n", __func__);
 439
 440         return ret;
 441 }
 442
 443 int board_early_init_f(void)
 444 {
 445         setup_iomux_uart();
 446 #if defined(CONFIG_VIDEO_IPUV3)
 447         setup_display();
 448 #endif
 449
 450         return 0;
 451 }
 452
 453 int board_init(void)
 454 {
 455         /* address of boot parameters */
 456         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 457
 458         return 0;
 459 }
 460
 461 #ifdef CONFIG_CMD_BMODE
 462 static const struct boot_mode board_boot_modes[] = {
 463         /* 4 bit bus width */
 464         {"sd2",  MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 465         {"sd3",  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 466         /* 8 bit bus width */
 467         {"emmc", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00)},
 468         {NULL,   0},
 469 };
 470 #endif
 471
 472 int board_late_init(void)
 473 {
 474 #ifdef CONFIG_CMD_BMODE
 475         add_board_boot_modes(board_boot_modes);
 476 #endif
 477
 478         return 0;
 479 }
 480
 481 int checkboard(void)
 482 {
 483         puts("Board: MX6-SabreSD\n");
 484         return 0;
 485 }