board/freescale/p1022ds/ddr.c

   1 /*
   2  * Copyright 2010 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the Free
   8  * Software Foundation; either version 2 of the License, or (at your option)
   9  * any later version.
  10  */
  11
  12 #include <common.h>
  13
  14 #include <asm/fsl_ddr_sdram.h>
  15 #include <asm/fsl_ddr_dimm_params.h>
  16
  17 struct board_specific_parameters {
  18         u32 n_ranks;
  19         u32 datarate_mhz_high;
  20         u32 clk_adjust;         /* Range: 0-8 */
  21         u32 cpo;                /* Range: 2-31 */
  22         u32 write_data_delay;   /* Range: 0-6 */
  23         u32 force_2T;
  24 };
  25
  26 /*
  27  * This table contains all valid speeds we want to override with board
  28  * specific parameters. datarate_mhz_high values need to be in ascending order
  29  * for each n_ranks group.
  30  */
  31 static const struct board_specific_parameters dimm0[] = {
  32         /*
  33          * memory controller 0
  34          *   num|  hi|  clk| cpo|wrdata|2T
  35          * ranks| mhz|adjst|    | delay|
  36          */
  37         {1,  549,    5,  31,     3, 0},
  38         {1,  850,    5,  31,     5, 0},
  39         {2,  549,    5,  31,     3, 0},
  40         {2,  850,    5,  31,     5, 0},
  41         {}
  42 };
  43
  44 void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
  45                            unsigned int ctrl_num)
  46 {
  47         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  48         unsigned long ddr_freq;
  49         unsigned int i;
  50
  51
  52         if (ctrl_num) {
  53                 printf("Wrong parameter for controller number %d", ctrl_num);
  54                 return;
  55         }
  56         if (!pdimm->n_ranks)
  57                 return;
  58
  59         /* set odt_rd_cfg and odt_wr_cfg. */
  60         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
  61                 popts->cs_local_opts[i].odt_rd_cfg = 0;
  62                 popts->cs_local_opts[i].odt_wr_cfg = 1;
  63         }
  64
  65         pbsp = dimm0;
  66         /*
  67          * Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
  68          * freqency and n_banks specified in board_specific_parameters table.
  69          */
  70         ddr_freq = get_ddr_freq(0) / 1000000;
  71         while (pbsp->datarate_mhz_high) {
  72                 if (pbsp->n_ranks == pdimm->n_ranks) {
  73                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  74                                 popts->clk_adjust = pbsp->clk_adjust;
  75                                 popts->cpo_override = pbsp->cpo;
  76                                 popts->write_data_delay =
  77                                         pbsp->write_data_delay;
  78                                 popts->twoT_en = pbsp->force_2T;
  79                                 goto found;
  80                         }
  81                         pbsp_highest = pbsp;
  82                 }
  83                 pbsp++;
  84         }
  85
  86         if (pbsp_highest) {
  87                 printf("Error: board specific timing not found "
  88                         "for data rate %lu MT/s!\n"
  89                         "Trying to use the highest speed (%u) parameters\n",
  90                         ddr_freq, pbsp_highest->datarate_mhz_high);
  91                 popts->clk_adjust = pbsp->clk_adjust;
  92                 popts->cpo_override = pbsp->cpo;
  93                 popts->write_data_delay = pbsp->write_data_delay;
  94                 popts->twoT_en = pbsp->force_2T;
  95         } else {
  96                 panic("DIMM is not supported by this board");
  97         }
  98
  99 found:
 100         popts->half_strength_driver_enable = 1;
 101
 102         /* Per AN4039, enable ZQ calibration. */
 103         popts->zq_en = 1;
 104
 105         /*
 106          * For wake-up on ARP, we need auto self refresh enabled
 107          */
 108         popts->auto_self_refresh_en = 1;
 109         popts->sr_it = 0xb;
 110 }