board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <asm/fsl_serdes.h>
  34 #include <miiphy.h>
  35 #include <libfdt.h>
  36 #include <fdt_support.h>
  37 #include <tsec.h>
  38 #include <asm/fsl_law.h>
  39 #include <asm/mp.h>
  40 #include <netdev.h>
  41
  42 #include "../common/ngpixis.h"
  43 #include "../common/sgmii_riser.h"
  44
  45 DECLARE_GLOBAL_DATA_PTR;
  46
  47 int checkboard(void)
  48 {
  49         u8 sw;
  50
  51         puts("Board: P2020DS ");
  52 #ifdef CONFIG_PHYS_64BIT
  53         puts("(36-bit addrmap) ");
  54 #endif
  55
  56         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  57                 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  58
  59         sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  60         sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  61
  62         if (sw < 0x8)
  63                 /* The lower two bits are the actual vbank number */
  64                 printf("vBank: %d\n", sw & 3);
  65         else
  66                 puts("Promjet\n");
  67
  68         return 0;
  69 }
  70
  71 #if !defined(CONFIG_DDR_SPD)
  72 /*
  73  * Fixed sdram init -- doesn't use serial presence detect.
  74  */
  75
  76 phys_size_t fixed_sdram(void)
  77 {
  78         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  79         uint d_init;
  80
  81         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  82         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  83         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  84         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  85         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
  86         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
  87         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  88         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
  89         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
  90         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
  91         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
  92         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
  93         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
  94         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
  95         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
  96
  97         if (!strcmp("performance", getenv("perf_mode"))) {
  98                 /* Performance Mode Values */
  99
 100                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 101                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 102                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 103                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 104                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 105
 106                 asm("sync;isync");
 107
 108                 udelay(500);
 109
 110                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 111         } else {
 112                 /* Stable Mode Values */
 113
 114                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 115                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 116                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 117                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 118                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 119
 120                 /* ECC will be assumed in stable mode */
 121                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 122                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 123                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 124
 125                 asm("sync;isync");
 126
 127                 udelay(500);
 128
 129                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 130         }
 131
 132 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 133         d_init = 1;
 134         debug("DDR - 1st controller: memory initializing\n");
 135         /*
 136          * Poll until memory is initialized.
 137          * 512 Meg at 400 might hit this 200 times or so.
 138          */
 139         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 140                 udelay(1000);
 141         debug("DDR: memory initialized\n\n");
 142         asm("sync; isync");
 143         udelay(500);
 144 #endif
 145
 146         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
 147                          CONFIG_SYS_SDRAM_SIZE * 1024 * 1024,
 148                          LAW_TRGT_IF_DDR) < 0) {
 149                 printf("ERROR setting Local Access Windows for DDR\n");
 150                 return 0;
 151         };
 152
 153         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 154 }
 155
 156 #endif
 157
 158 #ifdef CONFIG_PCI
 159 void pci_init_board(void)
 160 {
 161         fsl_pcie_init_board(0);
 162 }
 163 #endif
 164
 165 int board_early_init_r(void)
 166 {
 167         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 168         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 169
 170         /*
 171          * Remap Boot flash + PROMJET region to caching-inhibited
 172          * so that flash can be erased properly.
 173          */
 174
 175         /* Flush d-cache and invalidate i-cache of any FLASH data */
 176         flush_dcache();
 177         invalidate_icache();
 178
 179         /* invalidate existing TLB entry for flash + promjet */
 180         disable_tlb(flash_esel);
 181
 182         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 183                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 184                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 185
 186         return 0;
 187 }
 188
 189 #ifdef CONFIG_TSEC_ENET
 190 int board_eth_init(bd_t *bis)
 191 {
 192         struct tsec_info_struct tsec_info[4];
 193         int num = 0;
 194
 195 #ifdef CONFIG_TSEC1
 196         SET_STD_TSEC_INFO(tsec_info[num], 1);
 197         num++;
 198 #endif
 199 #ifdef CONFIG_TSEC2
 200         SET_STD_TSEC_INFO(tsec_info[num], 2);
 201         if (is_serdes_configured(SGMII_TSEC2)) {
 202                 puts("eTSEC2 is in sgmii mode.\n");
 203                 tsec_info[num].flags |= TSEC_SGMII;
 204         }
 205         num++;
 206 #endif
 207 #ifdef CONFIG_TSEC3
 208         SET_STD_TSEC_INFO(tsec_info[num], 3);
 209         if (is_serdes_configured(SGMII_TSEC3)) {
 210                 puts("eTSEC3 is in sgmii mode.\n");
 211                 tsec_info[num].flags |= TSEC_SGMII;
 212 }
 213         num++;
 214 #endif
 215
 216         if (!num) {
 217                 printf("No TSECs initialized\n");
 218
 219                 return 0;
 220         }
 221
 222 #ifdef CONFIG_FSL_SGMII_RISER
 223         fsl_sgmii_riser_init(tsec_info, num);
 224 #endif
 225
 226         tsec_eth_init(bis, tsec_info, num);
 227
 228         return pci_eth_init(bis);
 229 }
 230 #endif
 231
 232 #if defined(CONFIG_OF_BOARD_SETUP)
 233 void ft_board_setup(void *blob, bd_t *bd)
 234 {
 235         phys_addr_t base;
 236         phys_size_t size;
 237
 238         ft_cpu_setup(blob, bd);
 239
 240         base = getenv_bootm_low();
 241         size = getenv_bootm_size();
 242
 243         fdt_fixup_memory(blob, (u64)base, (u64)size);
 244
 245         FT_FSL_PCI_SETUP;
 246
 247 #ifdef CONFIG_FSL_SGMII_RISER
 248         fsl_sgmii_riser_fdt_fixup(blob);
 249 #endif
 250 }
 251 #endif
 252
 253 #ifdef CONFIG_MP
 254 void board_lmb_reserve(struct lmb *lmb)
 255 {
 256         cpu_mp_lmb_reserve(lmb);
 257 }
 258 #endif