board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2010 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37 #include <asm/fsl_law.h>
  38 #include <asm/mp.h>
  39 #include <netdev.h>
  40
  41 #include "../common/ngpixis.h"
  42 #include "../common/sgmii_riser.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 phys_size_t fixed_sdram(void);
  47
  48 int checkboard(void)
  49 {
  50         u8 sw;
  51
  52         puts("Board: P2020DS ");
  53 #ifdef CONFIG_PHYS_64BIT
  54         puts("(36-bit addrmap) ");
  55 #endif
  56
  57         printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
  58                 in_8(&pixis->id), in_8(&pixis->arch), in_8(&pixis->scver));
  59
  60         sw = in_8(&PIXIS_SW(PIXIS_LBMAP_SWITCH));
  61         sw = (sw & PIXIS_LBMAP_MASK) >> PIXIS_LBMAP_SHIFT;
  62
  63         if (sw < 0x8)
  64                 /* The lower two bits are the actual vbank number */
  65                 printf("vBank: %d\n", sw & 3);
  66         else
  67                 puts("Promjet\n");
  68
  69         return 0;
  70 }
  71
  72 phys_size_t initdram(int board_type)
  73 {
  74         phys_size_t dram_size = 0;
  75
  76         puts("Initializing....");
  77
  78 #ifdef CONFIG_SPD_EEPROM
  79         dram_size = fsl_ddr_sdram();
  80 #else
  81         dram_size = fixed_sdram();
  82
  83         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  84                          dram_size,
  85                          LAW_TRGT_IF_DDR) < 0) {
  86                 printf("ERROR setting Local Access Windows for DDR\n");
  87                 return 0;
  88         };
  89 #endif
  90         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  91         dram_size *= 0x100000;
  92
  93         puts("    DDR: ");
  94         return dram_size;
  95 }
  96
  97 #if !defined(CONFIG_SPD_EEPROM)
  98 /*
  99  * Fixed sdram init -- doesn't use serial presence detect.
 100  */
 101
 102 phys_size_t fixed_sdram(void)
 103 {
 104         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
 105         uint d_init;
 106
 107         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 108         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
 109         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 110         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 111         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 112         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
 113         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 114         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 115         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 116         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 117         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
 118         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
 119         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
 120         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
 121         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
 122
 123         if (!strcmp("performance", getenv("perf_mode"))) {
 124                 /* Performance Mode Values */
 125
 126                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 127                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 128                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 129                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 130                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 131
 132                 asm("sync;isync");
 133
 134                 udelay(500);
 135
 136                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 137         } else {
 138                 /* Stable Mode Values */
 139
 140                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 141                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 142                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 143                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 144                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 145
 146                 /* ECC will be assumed in stable mode */
 147                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 148                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 149                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 150
 151                 asm("sync;isync");
 152
 153                 udelay(500);
 154
 155                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 156         }
 157
 158 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 159         d_init = 1;
 160         debug("DDR - 1st controller: memory initializing\n");
 161         /*
 162          * Poll until memory is initialized.
 163          * 512 Meg at 400 might hit this 200 times or so.
 164          */
 165         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 166                 udelay(1000);
 167         debug("DDR: memory initialized\n\n");
 168         asm("sync; isync");
 169         udelay(500);
 170 #endif
 171
 172         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 173 }
 174
 175 #endif
 176
 177 #ifdef CONFIG_PCIE1
 178 static struct pci_controller pcie1_hose;
 179 #endif
 180
 181 #ifdef CONFIG_PCIE2
 182 static struct pci_controller pcie2_hose;
 183 #endif
 184
 185 #ifdef CONFIG_PCIE3
 186 static struct pci_controller pcie3_hose;
 187 #endif
 188
 189 #ifdef CONFIG_PCI
 190 void pci_init_board(void)
 191 {
 192         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 193         struct fsl_pci_info pci_info[3];
 194         u32 devdisr, pordevsr, io_sel;
 195         int first_free_busno = 0;
 196         int num = 0;
 197
 198         int pcie_ep, pcie_configured;
 199
 200         devdisr = in_be32(&gur->devdisr);
 201         pordevsr = in_be32(&gur->pordevsr);
 202         io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 203
 204         debug ("   pci_init_board: devdisr=%x, io_sel=%x\n", devdisr, io_sel);
 205
 206         if (!(pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 207                 printf("    eTSEC2 is in sgmii mode.\n");
 208         if (!(pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 209                 printf("    eTSEC3 is in sgmii mode.\n");
 210
 211         puts("\n");
 212 #ifdef CONFIG_PCIE2
 213         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_2, io_sel);
 214
 215         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
 216                 SET_STD_PCIE_INFO(pci_info[num], 2);
 217                 pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs);
 218                 printf("    PCIE2 connected to ULI as %s (base addr %lx)\n",
 219                                 pcie_ep ? "Endpoint" : "Root Complex",
 220                                 pci_info[num].regs);
 221                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 222                                         &pcie2_hose, first_free_busno);
 223
 224                 /*
 225                  * The workaround doesn't work on p2020 because the location
 226                  * we try and read isn't valid on p2020, fix this later
 227                  */
 228 #if 0
 229                 /*
 230                  * Activate ULI1575 legacy chip by performing a fake
 231                  * memory access.  Needed to make ULI RTC work.
 232                  * Device 1d has the first on-board memory BAR.
 233                  */
 234
 235                 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
 236                                 PCI_BASE_ADDRESS_1, &temp32);
 237                 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 238                         void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 239                                                         temp32, 4, 0);
 240                         debug(" uli1575 read to %p\n", p);
 241                         in_be32(p);
 242                 }
 243 #endif
 244         } else {
 245                 printf("    PCIE2: disabled\n");
 246         }
 247         puts("\n");
 248 #else
 249         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */
 250 #endif
 251
 252 #ifdef CONFIG_PCIE3
 253         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_3, io_sel);
 254
 255         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
 256                 SET_STD_PCIE_INFO(pci_info[num], 3);
 257                 pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs);
 258                 printf("    PCIE3 connected to Slot 1 as %s (base addr %lx)\n",
 259                                 pcie_ep ? "Endpoint" : "Root Complex",
 260                                 pci_info[num].regs);
 261                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 262                                         &pcie3_hose, first_free_busno);
 263         } else {
 264                 printf("    PCIE3: disabled\n");
 265         }
 266         puts("\n");
 267 #else
 268         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */
 269 #endif
 270
 271 #ifdef CONFIG_PCIE1
 272         pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
 273
 274         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
 275                 SET_STD_PCIE_INFO(pci_info[num], 1);
 276                 pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs);
 277                 printf("    PCIE1 connected to Slot 2 as %s (base addr %lx)\n",
 278                                 pcie_ep ? "Endpoint" : "Root Complex",
 279                                 pci_info[num].regs);
 280                 first_free_busno = fsl_pci_init_port(&pci_info[num++],
 281                                         &pcie1_hose, first_free_busno);
 282         } else {
 283                 printf("    PCIE1: disabled\n");
 284         }
 285         puts("\n");
 286 #else
 287         setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */
 288 #endif
 289 }
 290 #endif
 291
 292 int board_early_init_r(void)
 293 {
 294         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 295         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 296
 297         /*
 298          * Remap Boot flash + PROMJET region to caching-inhibited
 299          * so that flash can be erased properly.
 300          */
 301
 302         /* Flush d-cache and invalidate i-cache of any FLASH data */
 303         flush_dcache();
 304         invalidate_icache();
 305
 306         /* invalidate existing TLB entry for flash + promjet */
 307         disable_tlb(flash_esel);
 308
 309         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 310                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 311                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 312
 313         return 0;
 314 }
 315
 316 #ifdef CONFIG_TSEC_ENET
 317 int board_eth_init(bd_t *bis)
 318 {
 319         struct tsec_info_struct tsec_info[4];
 320         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 321         int num = 0;
 322
 323 #ifdef CONFIG_TSEC1
 324         SET_STD_TSEC_INFO(tsec_info[num], 1);
 325         num++;
 326 #endif
 327 #ifdef CONFIG_TSEC2
 328         SET_STD_TSEC_INFO(tsec_info[num], 2);
 329         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 330                 tsec_info[num].flags |= TSEC_SGMII;
 331         num++;
 332 #endif
 333 #ifdef CONFIG_TSEC3
 334         SET_STD_TSEC_INFO(tsec_info[num], 3);
 335         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 336                 tsec_info[num].flags |= TSEC_SGMII;
 337         num++;
 338 #endif
 339
 340         if (!num) {
 341                 printf("No TSECs initialized\n");
 342
 343                 return 0;
 344         }
 345
 346 #ifdef CONFIG_FSL_SGMII_RISER
 347         fsl_sgmii_riser_init(tsec_info, num);
 348 #endif
 349
 350         tsec_eth_init(bis, tsec_info, num);
 351
 352         return pci_eth_init(bis);
 353 }
 354 #endif
 355
 356 #if defined(CONFIG_OF_BOARD_SETUP)
 357 void ft_board_setup(void *blob, bd_t *bd)
 358 {
 359         phys_addr_t base;
 360         phys_size_t size;
 361
 362         ft_cpu_setup(blob, bd);
 363
 364         base = getenv_bootm_low();
 365         size = getenv_bootm_size();
 366
 367         fdt_fixup_memory(blob, (u64)base, (u64)size);
 368
 369         FT_FSL_PCI_SETUP;
 370
 371 #ifdef CONFIG_FSL_SGMII_RISER
 372         fsl_sgmii_riser_fdt_fixup(blob);
 373 #endif
 374 }
 375 #endif
 376
 377 #ifdef CONFIG_MP
 378 void board_lmb_reserve(struct lmb *lmb)
 379 {
 380         cpu_mp_lmb_reserve(lmb);
 381 }
 382 #endif