board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37 #include <asm/fsl_law.h>
  38 #include <asm/mp.h>
  39 #include <netdev.h>
  40
  41 #include "../common/pixis.h"
  42 #include "../common/sgmii_riser.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 phys_size_t fixed_sdram(void);
  47
  48 int checkboard(void)
  49 {
  50         puts("Board: P2020DS ");
  51 #ifdef CONFIG_PHYS_64BIT
  52         puts("(36-bit addrmap) ");
  53 #endif
  54         printf("Sys ID: 0x%02x, "
  55                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
  56                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  57                 in8(PIXIS_BASE + PIXIS_PVER));
  58         return 0;
  59 }
  60
  61 phys_size_t initdram(int board_type)
  62 {
  63         phys_size_t dram_size = 0;
  64
  65         puts("Initializing....");
  66
  67 #ifdef CONFIG_SPD_EEPROM
  68         dram_size = fsl_ddr_sdram();
  69 #else
  70         dram_size = fixed_sdram();
  71
  72         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  73                          dram_size,
  74                          LAW_TRGT_IF_DDR) < 0) {
  75                 printf("ERROR setting Local Access Windows for DDR\n");
  76                 return 0;
  77         };
  78 #endif
  79         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  80         dram_size *= 0x100000;
  81
  82         puts("    DDR: ");
  83         return dram_size;
  84 }
  85
  86 #if !defined(CONFIG_SPD_EEPROM)
  87 /*
  88  * Fixed sdram init -- doesn't use serial presence detect.
  89  */
  90
  91 phys_size_t fixed_sdram(void)
  92 {
  93         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  94         uint d_init;
  95
  96         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  97         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  98         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  99         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
 100         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 101         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
 102         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 103         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 104         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 105         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 106         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
 107         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
 108         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
 109         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
 110         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
 111
 112         if (!strcmp("performance", getenv("perf_mode"))) {
 113                 /* Performance Mode Values */
 114
 115                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 116                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 117                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 118                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 119                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 120
 121                 asm("sync;isync");
 122
 123                 udelay(500);
 124
 125                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 126         } else {
 127                 /* Stable Mode Values */
 128
 129                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 130                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 131                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 132                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 133                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 134
 135                 /* ECC will be assumed in stable mode */
 136                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 137                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 138                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 139
 140                 asm("sync;isync");
 141
 142                 udelay(500);
 143
 144                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 145         }
 146
 147 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 148         d_init = 1;
 149         debug("DDR - 1st controller: memory initializing\n");
 150         /*
 151          * Poll until memory is initialized.
 152          * 512 Meg at 400 might hit this 200 times or so.
 153          */
 154         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 155                 udelay(1000);
 156         debug("DDR: memory initialized\n\n");
 157         asm("sync; isync");
 158         udelay(500);
 159 #endif
 160
 161         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 162 }
 163
 164 #endif
 165
 166 #ifdef CONFIG_PCIE1
 167 static struct pci_controller pcie1_hose;
 168 #endif
 169
 170 #ifdef CONFIG_PCIE2
 171 static struct pci_controller pcie2_hose;
 172 #endif
 173
 174 #ifdef CONFIG_PCIE3
 175 static struct pci_controller pcie3_hose;
 176 #endif
 177
 178 int first_free_busno = 0;
 179
 180 #ifdef CONFIG_PCI
 181 void pci_init_board(void)
 182 {
 183         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 184         uint devdisr = gur->devdisr;
 185         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 186         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 187
 188         volatile ccsr_fsl_pci_t *pci;
 189         struct pci_controller *hose;
 190         int pcie_ep, pcie_configured;
 191         struct pci_region *r;
 192 /*              u32 temp32; */
 193
 194         debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 195                         devdisr, io_sel, host_agent);
 196
 197         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 198                 printf("    eTSEC2 is in sgmii mode.\n");
 199         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 200                 printf("    eTSEC3 is in sgmii mode.\n");
 201
 202 #ifdef CONFIG_PCIE2
 203         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 204         hose = &pcie2_hose;
 205         pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 206                   (host_agent == 6) || (host_agent == 0);
 207         pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
 208         r = hose->regions;
 209
 210         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
 211                 printf("\n    PCIE2 connected to ULI as %s (base addr %x)",
 212                                 pcie_ep ? "End Point" : "Root Complex",
 213                                 (uint)pci);
 214                 if (pci->pme_msg_det) {
 215                         pci->pme_msg_det = 0xffffffff;
 216                         debug(" with errors.  Clearing.  Now 0x%08x",
 217                                 pci->pme_msg_det);
 218                 }
 219                 printf("\n");
 220
 221                 /* inbound */
 222                 r += fsl_pci_setup_inbound_windows(r);
 223
 224                 /* outbound memory */
 225                 pci_set_region(r++,
 226                                 CONFIG_SYS_PCIE2_MEM_BUS,
 227                                 CONFIG_SYS_PCIE2_MEM_PHYS,
 228                                 CONFIG_SYS_PCIE2_MEM_SIZE,
 229                                 PCI_REGION_MEM);
 230
 231                 /* outbound io */
 232                 pci_set_region(r++,
 233                                 CONFIG_SYS_PCIE2_IO_BUS,
 234                                 CONFIG_SYS_PCIE2_IO_PHYS,
 235                                 CONFIG_SYS_PCIE2_IO_SIZE,
 236                                 PCI_REGION_IO);
 237
 238                 hose->region_count = r - hose->regions;
 239                 hose->first_busno = first_free_busno;
 240                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 241                                   (int)&pci->cfg_data);
 242
 243                 fsl_pci_init(hose);
 244                 first_free_busno = hose->last_busno+1;
 245                 printf("    PCIE2 on bus %02x - %02x\n",
 246                         hose->first_busno, hose->last_busno);
 247
 248                 /*
 249                  * The workaround doesn't work on p2020 because the location
 250                  * we try and read isn't valid on p2020, fix this later
 251                  */
 252 #if 0
 253                 /*
 254                  * Activate ULI1575 legacy chip by performing a fake
 255                  * memory access.  Needed to make ULI RTC work.
 256                  * Device 1d has the first on-board memory BAR.
 257                  */
 258
 259                 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
 260                                 PCI_BASE_ADDRESS_1, &temp32);
 261                 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 262                         void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 263                                                         temp32, 4, 0);
 264                         debug(" uli1575 read to %p\n", p);
 265                         in_be32(p);
 266                 }
 267 #endif
 268         } else {
 269                 printf("    PCIE2: disabled\n");
 270         }
 271 #else
 272         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 273 #endif
 274
 275 #ifdef CONFIG_PCIE3
 276         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 277         hose = &pcie3_hose;
 278         pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 279                 (host_agent == 5) || (host_agent == 6);
 280         pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
 281         r = hose->regions;
 282
 283         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
 284                 printf("\n    PCIE3 connected to Slot 1 as %s (base addr %x)",
 285                                 pcie_ep ? "End Point" : "Root Complex",
 286                                 (uint)pci);
 287                 if (pci->pme_msg_det) {
 288                         pci->pme_msg_det = 0xffffffff;
 289                         debug(" with errors.  Clearing.  Now 0x%08x",
 290                                 pci->pme_msg_det);
 291                 }
 292                 printf("\n");
 293
 294                 /* inbound */
 295                 r += fsl_pci_setup_inbound_windows(r);
 296
 297                 /* outbound memory */
 298                 pci_set_region(r++,
 299                                 CONFIG_SYS_PCIE3_MEM_BUS,
 300                                 CONFIG_SYS_PCIE3_MEM_PHYS,
 301                                 CONFIG_SYS_PCIE3_MEM_SIZE,
 302                                 PCI_REGION_MEM);
 303
 304                 /* outbound io */
 305                 pci_set_region(r++,
 306                                 CONFIG_SYS_PCIE3_IO_BUS,
 307                                 CONFIG_SYS_PCIE3_IO_PHYS,
 308                                 CONFIG_SYS_PCIE3_IO_SIZE,
 309                                 PCI_REGION_IO);
 310
 311                 hose->region_count = r - hose->regions;
 312                 hose->first_busno = first_free_busno;
 313                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 314                                   (int)&pci->cfg_data);
 315
 316                 fsl_pci_init(hose);
 317
 318                 first_free_busno = hose->last_busno+1;
 319                 printf("    PCIE3 on bus %02x - %02x\n",
 320                                 hose->first_busno, hose->last_busno);
 321
 322         } else {
 323                 printf("    PCIE3: disabled\n");
 324         }
 325 #else
 326         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 327 #endif
 328
 329 #ifdef CONFIG_PCIE1
 330         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 331         hose = &pcie1_hose;
 332         pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
 333         pcie_configured  = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
 334         r = hose->regions;
 335
 336         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
 337                 printf("\n    PCIE1 connected to Slot 2 as %s (base addr %x)",
 338                                 pcie_ep ? "End Point" : "Root Complex",
 339                                 (uint)pci);
 340                 if (pci->pme_msg_det) {
 341                         pci->pme_msg_det = 0xffffffff;
 342                         debug(" with errors.  Clearing.  Now 0x%08x",
 343                                 pci->pme_msg_det);
 344                 }
 345                 printf("\n");
 346
 347                 /* inbound */
 348                 r += fsl_pci_setup_inbound_windows(r);
 349
 350                 /* outbound memory */
 351                 pci_set_region(r++,
 352                                 CONFIG_SYS_PCIE1_MEM_BUS,
 353                                 CONFIG_SYS_PCIE1_MEM_PHYS,
 354                                 CONFIG_SYS_PCIE1_MEM_SIZE,
 355                                 PCI_REGION_MEM);
 356
 357                 /* outbound io */
 358                 pci_set_region(r++,
 359                                 CONFIG_SYS_PCIE1_IO_BUS,
 360                                 CONFIG_SYS_PCIE1_IO_PHYS,
 361                                 CONFIG_SYS_PCIE1_IO_SIZE,
 362                                 PCI_REGION_IO);
 363
 364                 hose->region_count = r - hose->regions;
 365                 hose->first_busno = first_free_busno;
 366
 367                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 368                                   (int)&pci->cfg_data);
 369
 370                 fsl_pci_init(hose);
 371
 372                 first_free_busno = hose->last_busno+1;
 373                 printf("    PCIE1 on bus %02x - %02x\n",
 374                         hose->first_busno, hose->last_busno);
 375
 376         } else {
 377                 printf("    PCIE1: disabled\n");
 378         }
 379 #else
 380         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 381 #endif
 382 }
 383 #endif
 384
 385 int board_early_init_r(void)
 386 {
 387         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 388         const u8 flash_esel = 2;
 389
 390         /*
 391          * Remap Boot flash + PROMJET region to caching-inhibited
 392          * so that flash can be erased properly.
 393          */
 394
 395         /* Flush d-cache and invalidate i-cache of any FLASH data */
 396         flush_dcache();
 397         invalidate_icache();
 398
 399         /* invalidate existing TLB entry for flash + promjet */
 400         disable_tlb(flash_esel);
 401
 402         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 403                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 404                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 405
 406         return 0;
 407 }
 408
 409 #ifdef CONFIG_GET_CLK_FROM_ICS307
 410 /* decode S[0-2] to Output Divider (OD) */
 411 static unsigned char ics307_S_to_OD[] = {
 412         10, 2, 8, 4, 5, 7, 3, 6
 413 };
 414
 415 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 416  * the control bytes being programmed into it. */
 417 /* XXX: This function should probably go into a common library */
 418 static unsigned long
 419 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
 420 {
 421         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 422         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 423         unsigned long RDW = cw2 & 0x7F;
 424         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 425         unsigned long freq;
 426
 427         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 428
 429         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 430          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 431          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 432          *
 433          * R6:R0 = Reference Divider Word (RDW)
 434          * V8:V0 = VCO Divider Word (VDW)
 435          * S2:S0 = Output Divider Select (OD)
 436          * F1:F0 = Function of CLK2 Output
 437          * TTL = duty cycle
 438          * C1:C0 = internal load capacitance for cyrstal
 439          */
 440
 441         /* Adding 1 to get a "nicely" rounded number, but this needs
 442          * more tweaking to get a "properly" rounded number. */
 443
 444         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 445
 446         debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
 447                         freq);
 448         return freq;
 449 }
 450
 451 unsigned long get_board_sys_clk(ulong dummy)
 452 {
 453         return gd->bus_clk;
 454 }
 455
 456 unsigned long get_board_ddr_clk(ulong dummy)
 457 {
 458         return gd->mem_clk;
 459 }
 460
 461 unsigned long
 462 calculate_board_sys_clk(ulong dummy)
 463 {
 464         ulong val;
 465         val = ics307_clk_freq(
 466             in8(PIXIS_BASE + PIXIS_VSYSCLK0),
 467             in8(PIXIS_BASE + PIXIS_VSYSCLK1),
 468             in8(PIXIS_BASE + PIXIS_VSYSCLK2));
 469         debug("sysclk val = %lu\n", val);
 470         return val;
 471 }
 472
 473 unsigned long
 474 calculate_board_ddr_clk(ulong dummy)
 475 {
 476         ulong val;
 477         val = ics307_clk_freq(
 478             in8(PIXIS_BASE + PIXIS_VDDRCLK0),
 479             in8(PIXIS_BASE + PIXIS_VDDRCLK1),
 480             in8(PIXIS_BASE + PIXIS_VDDRCLK2));
 481         debug("ddrclk val = %lu\n", val);
 482         return val;
 483 }
 484 #else
 485 unsigned long get_board_sys_clk(ulong dummy)
 486 {
 487         u8 i;
 488         ulong val = 0;
 489
 490         i = in8(PIXIS_BASE + PIXIS_SPD);
 491         i &= 0x07;
 492
 493         switch (i) {
 494                 case 0:
 495                         val = 33333333;
 496                         break;
 497                 case 1:
 498                         val = 40000000;
 499                         break;
 500                 case 2:
 501                         val = 50000000;
 502                         break;
 503                 case 3:
 504                         val = 66666666;
 505                         break;
 506                 case 4:
 507                         val = 83333333;
 508                         break;
 509                 case 5:
 510                         val = 100000000;
 511                         break;
 512                 case 6:
 513                         val = 133333333;
 514                         break;
 515                 case 7:
 516                         val = 166666666;
 517                         break;
 518         }
 519
 520         return val;
 521 }
 522
 523 unsigned long get_board_ddr_clk(ulong dummy)
 524 {
 525         u8 i;
 526         ulong val = 0;
 527
 528         i = in8(PIXIS_BASE + PIXIS_SPD);
 529         i &= 0x38;
 530         i >>= 3;
 531
 532         switch (i) {
 533                 case 0:
 534                         val = 33333333;
 535                         break;
 536                 case 1:
 537                         val = 40000000;
 538                         break;
 539                 case 2:
 540                         val = 50000000;
 541                         break;
 542                 case 3:
 543                         val = 66666666;
 544                         break;
 545                 case 4:
 546                         val = 83333333;
 547                         break;
 548                 case 5:
 549                         val = 100000000;
 550                         break;
 551                 case 6:
 552                         val = 133333333;
 553                         break;
 554                 case 7:
 555                         val = 166666666;
 556                         break;
 557         }
 558         return val;
 559 }
 560 #endif
 561
 562 #ifdef CONFIG_TSEC_ENET
 563 int board_eth_init(bd_t *bis)
 564 {
 565         struct tsec_info_struct tsec_info[4];
 566         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 567         int num = 0;
 568
 569 #ifdef CONFIG_TSEC1
 570         SET_STD_TSEC_INFO(tsec_info[num], 1);
 571         num++;
 572 #endif
 573 #ifdef CONFIG_TSEC2
 574         SET_STD_TSEC_INFO(tsec_info[num], 2);
 575         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 576                 tsec_info[num].flags |= TSEC_SGMII;
 577         num++;
 578 #endif
 579 #ifdef CONFIG_TSEC3
 580         SET_STD_TSEC_INFO(tsec_info[num], 3);
 581         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 582                 tsec_info[num].flags |= TSEC_SGMII;
 583         num++;
 584 #endif
 585
 586         if (!num) {
 587                 printf("No TSECs initialized\n");
 588
 589                 return 0;
 590         }
 591
 592 #ifdef CONFIG_FSL_SGMII_RISER
 593         fsl_sgmii_riser_init(tsec_info, num);
 594 #endif
 595
 596         tsec_eth_init(bis, tsec_info, num);
 597
 598         return pci_eth_init(bis);
 599 }
 600 #endif
 601
 602 #if defined(CONFIG_OF_BOARD_SETUP)
 603 void ft_board_setup(void *blob, bd_t *bd)
 604 {
 605         phys_addr_t base;
 606         phys_size_t size;
 607
 608         ft_cpu_setup(blob, bd);
 609
 610         base = getenv_bootm_low();
 611         size = getenv_bootm_size();
 612
 613         fdt_fixup_memory(blob, (u64)base, (u64)size);
 614
 615 #ifdef CONFIG_PCIE3
 616         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 617 #endif
 618 #ifdef CONFIG_PCIE2
 619         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 620 #endif
 621 #ifdef CONFIG_PCIE1
 622         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 623 #endif
 624 #ifdef CONFIG_FSL_SGMII_RISER
 625         fsl_sgmii_riser_fdt_fixup(blob);
 626 #endif
 627 }
 628 #endif
 629
 630 #ifdef CONFIG_MP
 631 void board_lmb_reserve(struct lmb *lmb)
 632 {
 633         cpu_mp_lmb_reserve(lmb);
 634 }
 635 #endif