board/freescale/p2020ds/p2020ds.c

   1 /*
   2  * Copyright 2007-2009 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36 #include <tsec.h>
  37 #include <asm/fsl_law.h>
  38 #include <asm/mp.h>
  39
  40 #include "../common/pixis.h"
  41 #include "../common/sgmii_riser.h"
  42
  43 DECLARE_GLOBAL_DATA_PTR;
  44
  45 phys_size_t fixed_sdram(void);
  46
  47 int checkboard(void)
  48 {
  49         puts("Board: P2020DS ");
  50 #ifdef CONFIG_PHYS_64BIT
  51         puts("(36-bit addrmap) ");
  52 #endif
  53         printf("Sys ID: 0x%02x, "
  54                 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x\n",
  55                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  56                 in8(PIXIS_BASE + PIXIS_PVER));
  57         return 0;
  58 }
  59
  60 phys_size_t initdram(int board_type)
  61 {
  62         phys_size_t dram_size = 0;
  63
  64         puts("Initializing....");
  65
  66 #ifdef CONFIG_SPD_EEPROM
  67         dram_size = fsl_ddr_sdram();
  68 #else
  69         dram_size = fixed_sdram();
  70
  71         if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
  72                          dram_size,
  73                          LAW_TRGT_IF_DDR) < 0) {
  74                 printf("ERROR setting Local Access Windows for DDR\n");
  75                 return 0;
  76         };
  77 #endif
  78         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  79         dram_size *= 0x100000;
  80
  81         puts("    DDR: ");
  82         return dram_size;
  83 }
  84
  85 #if !defined(CONFIG_SPD_EEPROM)
  86 /*
  87  * Fixed sdram init -- doesn't use serial presence detect.
  88  */
  89
  90 phys_size_t fixed_sdram(void)
  91 {
  92         volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
  93         uint d_init;
  94
  95         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  96         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  97         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  98         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  99         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 100         ddr->sdram_md_cntl = CONFIG_SYS_DDR_MODE_CTRL;
 101         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 102         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 103         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 104         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 105         ddr->ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CNTL;
 106         ddr->ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CNTL;
 107         ddr->ddr_cdr1 = CONFIG_SYS_DDR_CDR1;
 108         ddr->timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4;
 109         ddr->timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5;
 110
 111         if (!strcmp("performance", getenv("perf_mode"))) {
 112                 /* Performance Mode Values */
 113
 114                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG_PERF;
 115                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS_PERF;
 116                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS_PERF;
 117                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_PERF;
 118                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2_PERF;
 119
 120                 asm("sync;isync");
 121
 122                 udelay(500);
 123
 124                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL_PERF;
 125         } else {
 126                 /* Stable Mode Values */
 127
 128                 ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
 129                 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 130                 ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
 131                 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 132                 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 133
 134                 /* ECC will be assumed in stable mode */
 135                 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 136                 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 137                 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 138
 139                 asm("sync;isync");
 140
 141                 udelay(500);
 142
 143                 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 144         }
 145
 146 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 147         d_init = 1;
 148         debug("DDR - 1st controller: memory initializing\n");
 149         /*
 150          * Poll until memory is initialized.
 151          * 512 Meg at 400 might hit this 200 times or so.
 152          */
 153         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
 154                 udelay(1000);
 155         debug("DDR: memory initialized\n\n");
 156         asm("sync; isync");
 157         udelay(500);
 158 #endif
 159
 160         return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 161 }
 162
 163 #endif
 164
 165 #ifdef CONFIG_PCIE1
 166 static struct pci_controller pcie1_hose;
 167 #endif
 168
 169 #ifdef CONFIG_PCIE2
 170 static struct pci_controller pcie2_hose;
 171 #endif
 172
 173 #ifdef CONFIG_PCIE3
 174 static struct pci_controller pcie3_hose;
 175 #endif
 176
 177 int first_free_busno = 0;
 178
 179 #ifdef CONFIG_PCI
 180 void pci_init_board(void)
 181 {
 182         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 183         uint devdisr = gur->devdisr;
 184         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 185         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 186
 187         volatile ccsr_fsl_pci_t *pci;
 188         struct pci_controller *hose;
 189         int pcie_ep, pcie_configured;
 190         struct pci_region *r;
 191 /*              u32 temp32; */
 192
 193         debug("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 194                         devdisr, io_sel, host_agent);
 195
 196         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 197                 printf("    eTSEC2 is in sgmii mode.\n");
 198         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 199                 printf("    eTSEC3 is in sgmii mode.\n");
 200
 201 #ifdef CONFIG_PCIE2
 202         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 203         hose = &pcie2_hose;
 204         pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 205                   (host_agent == 6) || (host_agent == 0);
 206         pcie_configured = (io_sel == 0x2) || (io_sel == 0xe);
 207         r = hose->regions;
 208
 209         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)) {
 210                 printf("\n    PCIE2 connected to ULI as %s (base addr %x)",
 211                                 pcie_ep ? "End Point" : "Root Complex",
 212                                 (uint)pci);
 213                 if (pci->pme_msg_det) {
 214                         pci->pme_msg_det = 0xffffffff;
 215                         debug(" with errors.  Clearing.  Now 0x%08x",
 216                                 pci->pme_msg_det);
 217                 }
 218                 printf("\n");
 219
 220                 /* inbound */
 221                 r += fsl_pci_setup_inbound_windows(r);
 222
 223                 /* outbound memory */
 224                 pci_set_region(r++,
 225                                 CONFIG_SYS_PCIE2_MEM_BUS,
 226                                 CONFIG_SYS_PCIE2_MEM_PHYS,
 227                                 CONFIG_SYS_PCIE2_MEM_SIZE,
 228                                 PCI_REGION_MEM);
 229
 230                 /* outbound io */
 231                 pci_set_region(r++,
 232                                 CONFIG_SYS_PCIE2_IO_BUS,
 233                                 CONFIG_SYS_PCIE2_IO_PHYS,
 234                                 CONFIG_SYS_PCIE2_IO_SIZE,
 235                                 PCI_REGION_IO);
 236
 237                 hose->region_count = r - hose->regions;
 238                 hose->first_busno = first_free_busno;
 239                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 240                                   (int)&pci->cfg_data);
 241
 242                 fsl_pci_init(hose);
 243                 first_free_busno = hose->last_busno+1;
 244                 printf("    PCIE2 on bus %02x - %02x\n",
 245                         hose->first_busno, hose->last_busno);
 246
 247                 /*
 248                  * The workaround doesn't work on p2020 because the location
 249                  * we try and read isn't valid on p2020, fix this later
 250                  */
 251 #if 0
 252                 /*
 253                  * Activate ULI1575 legacy chip by performing a fake
 254                  * memory access.  Needed to make ULI RTC work.
 255                  * Device 1d has the first on-board memory BAR.
 256                  */
 257
 258                 pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0),
 259                                 PCI_BASE_ADDRESS_1, &temp32);
 260                 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
 261                         void *p = pci_mem_to_virt(PCI_BDF(2, 0x1d, 0),
 262                                                         temp32, 4, 0);
 263                         debug(" uli1575 read to %p\n", p);
 264                         in_be32(p);
 265                 }
 266 #endif
 267         } else {
 268                 printf("    PCIE2: disabled\n");
 269         }
 270 #else
 271         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 272 #endif
 273
 274 #ifdef CONFIG_PCIE3
 275         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 276         hose = &pcie3_hose;
 277         pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 278                 (host_agent == 5) || (host_agent == 6);
 279         pcie_configured = (io_sel == 0x2) || (io_sel == 0x4);
 280         r = hose->regions;
 281
 282         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)) {
 283                 printf("\n    PCIE3 connected to Slot 1 as %s (base addr %x)",
 284                                 pcie_ep ? "End Point" : "Root Complex",
 285                                 (uint)pci);
 286                 if (pci->pme_msg_det) {
 287                         pci->pme_msg_det = 0xffffffff;
 288                         debug(" with errors.  Clearing.  Now 0x%08x",
 289                                 pci->pme_msg_det);
 290                 }
 291                 printf("\n");
 292
 293                 /* inbound */
 294                 r += fsl_pci_setup_inbound_windows(r);
 295
 296                 /* outbound memory */
 297                 pci_set_region(r++,
 298                                 CONFIG_SYS_PCIE3_MEM_BUS,
 299                                 CONFIG_SYS_PCIE3_MEM_PHYS,
 300                                 CONFIG_SYS_PCIE3_MEM_SIZE,
 301                                 PCI_REGION_MEM);
 302
 303                 /* outbound io */
 304                 pci_set_region(r++,
 305                                 CONFIG_SYS_PCIE3_IO_BUS,
 306                                 CONFIG_SYS_PCIE3_IO_PHYS,
 307                                 CONFIG_SYS_PCIE3_IO_SIZE,
 308                                 PCI_REGION_IO);
 309
 310                 hose->region_count = r - hose->regions;
 311                 hose->first_busno = first_free_busno;
 312                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 313                                   (int)&pci->cfg_data);
 314
 315                 fsl_pci_init(hose);
 316
 317                 first_free_busno = hose->last_busno+1;
 318                 printf("    PCIE3 on bus %02x - %02x\n",
 319                                 hose->first_busno, hose->last_busno);
 320
 321         } else {
 322                 printf("    PCIE3: disabled\n");
 323         }
 324 #else
 325         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 326 #endif
 327
 328 #ifdef CONFIG_PCIE1
 329         pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 330         hose = &pcie1_hose;
 331         pcie_ep = (host_agent <= 1) || (host_agent == 4) || (host_agent == 5);
 332         pcie_configured  = (io_sel & 6) || (io_sel == 0xE) || (io_sel == 0xF);
 333         r = hose->regions;
 334
 335         if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)) {
 336                 printf("\n    PCIE1 connected to Slot 2 as %s (base addr %x)",
 337                                 pcie_ep ? "End Point" : "Root Complex",
 338                                 (uint)pci);
 339                 if (pci->pme_msg_det) {
 340                         pci->pme_msg_det = 0xffffffff;
 341                         debug(" with errors.  Clearing.  Now 0x%08x",
 342                                 pci->pme_msg_det);
 343                 }
 344                 printf("\n");
 345
 346                 /* inbound */
 347                 r += fsl_pci_setup_inbound_windows(r);
 348
 349                 /* outbound memory */
 350                 pci_set_region(r++,
 351                                 CONFIG_SYS_PCIE1_MEM_BUS,
 352                                 CONFIG_SYS_PCIE1_MEM_PHYS,
 353                                 CONFIG_SYS_PCIE1_MEM_SIZE,
 354                                 PCI_REGION_MEM);
 355
 356                 /* outbound io */
 357                 pci_set_region(r++,
 358                                 CONFIG_SYS_PCIE1_IO_BUS,
 359                                 CONFIG_SYS_PCIE1_IO_PHYS,
 360                                 CONFIG_SYS_PCIE1_IO_SIZE,
 361                                 PCI_REGION_IO);
 362
 363                 hose->region_count = r - hose->regions;
 364                 hose->first_busno = first_free_busno;
 365
 366                 pci_setup_indirect(hose, (int)&pci->cfg_addr,
 367                                   (int)&pci->cfg_data);
 368
 369                 fsl_pci_init(hose);
 370
 371                 first_free_busno = hose->last_busno+1;
 372                 printf("    PCIE1 on bus %02x - %02x\n",
 373                         hose->first_busno, hose->last_busno);
 374
 375         } else {
 376                 printf("    PCIE1: disabled\n");
 377         }
 378 #else
 379         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 380 #endif
 381 }
 382 #endif
 383
 384 int board_early_init_r(void)
 385 {
 386         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 387         const u8 flash_esel = 2;
 388
 389         /*
 390          * Remap Boot flash + PROMJET region to caching-inhibited
 391          * so that flash can be erased properly.
 392          */
 393
 394         /* Flush d-cache and invalidate i-cache of any FLASH data */
 395         flush_dcache();
 396         invalidate_icache();
 397
 398         /* invalidate existing TLB entry for flash + promjet */
 399         disable_tlb(flash_esel);
 400
 401         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 402                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 403                         0, flash_esel, BOOKE_PAGESZ_256M, 1);
 404
 405         return 0;
 406 }
 407
 408 #ifdef CONFIG_GET_CLK_FROM_ICS307
 409 /* decode S[0-2] to Output Divider (OD) */
 410 static unsigned char ics307_S_to_OD[] = {
 411         10, 2, 8, 4, 5, 7, 3, 6
 412 };
 413
 414 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 415  * the control bytes being programmed into it. */
 416 /* XXX: This function should probably go into a common library */
 417 static unsigned long
 418 ics307_clk_freq(unsigned char cw0, unsigned char cw1, unsigned char cw2)
 419 {
 420         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 421         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 422         unsigned long RDW = cw2 & 0x7F;
 423         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 424         unsigned long freq;
 425
 426         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 427
 428         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 429          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 430          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 431          *
 432          * R6:R0 = Reference Divider Word (RDW)
 433          * V8:V0 = VCO Divider Word (VDW)
 434          * S2:S0 = Output Divider Select (OD)
 435          * F1:F0 = Function of CLK2 Output
 436          * TTL = duty cycle
 437          * C1:C0 = internal load capacitance for cyrstal
 438          */
 439
 440         /* Adding 1 to get a "nicely" rounded number, but this needs
 441          * more tweaking to get a "properly" rounded number. */
 442
 443         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 444
 445         debug("ICS307: CW[0-2]: %02X %02X %02X => %lu Hz\n", cw0, cw1, cw2,
 446                         freq);
 447         return freq;
 448 }
 449
 450 unsigned long get_board_sys_clk(ulong dummy)
 451 {
 452         return gd->bus_clk;
 453 }
 454
 455 unsigned long get_board_ddr_clk(ulong dummy)
 456 {
 457         return gd->mem_clk;
 458 }
 459
 460 unsigned long
 461 calculate_board_sys_clk(ulong dummy)
 462 {
 463         ulong val;
 464         val = ics307_clk_freq(
 465             in8(PIXIS_BASE + PIXIS_VSYSCLK0),
 466             in8(PIXIS_BASE + PIXIS_VSYSCLK1),
 467             in8(PIXIS_BASE + PIXIS_VSYSCLK2));
 468         debug("sysclk val = %lu\n", val);
 469         return val;
 470 }
 471
 472 unsigned long
 473 calculate_board_ddr_clk(ulong dummy)
 474 {
 475         ulong val;
 476         val = ics307_clk_freq(
 477             in8(PIXIS_BASE + PIXIS_VDDRCLK0),
 478             in8(PIXIS_BASE + PIXIS_VDDRCLK1),
 479             in8(PIXIS_BASE + PIXIS_VDDRCLK2));
 480         debug("ddrclk val = %lu\n", val);
 481         return val;
 482 }
 483 #else
 484 unsigned long get_board_sys_clk(ulong dummy)
 485 {
 486         u8 i;
 487         ulong val = 0;
 488
 489         i = in8(PIXIS_BASE + PIXIS_SPD);
 490         i &= 0x07;
 491
 492         switch (i) {
 493                 case 0:
 494                         val = 33333333;
 495                         break;
 496                 case 1:
 497                         val = 40000000;
 498                         break;
 499                 case 2:
 500                         val = 50000000;
 501                         break;
 502                 case 3:
 503                         val = 66666666;
 504                         break;
 505                 case 4:
 506                         val = 83333333;
 507                         break;
 508                 case 5:
 509                         val = 100000000;
 510                         break;
 511                 case 6:
 512                         val = 133333333;
 513                         break;
 514                 case 7:
 515                         val = 166666666;
 516                         break;
 517         }
 518
 519         return val;
 520 }
 521
 522 unsigned long get_board_ddr_clk(ulong dummy)
 523 {
 524         u8 i;
 525         ulong val = 0;
 526
 527         i = in8(PIXIS_BASE + PIXIS_SPD);
 528         i &= 0x38;
 529         i >>= 3;
 530
 531         switch (i) {
 532                 case 0:
 533                         val = 33333333;
 534                         break;
 535                 case 1:
 536                         val = 40000000;
 537                         break;
 538                 case 2:
 539                         val = 50000000;
 540                         break;
 541                 case 3:
 542                         val = 66666666;
 543                         break;
 544                 case 4:
 545                         val = 83333333;
 546                         break;
 547                 case 5:
 548                         val = 100000000;
 549                         break;
 550                 case 6:
 551                         val = 133333333;
 552                         break;
 553                 case 7:
 554                         val = 166666666;
 555                         break;
 556         }
 557         return val;
 558 }
 559 #endif
 560
 561 #ifdef CONFIG_TSEC_ENET
 562 int board_eth_init(bd_t *bis)
 563 {
 564         struct tsec_info_struct tsec_info[4];
 565         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 566         int num = 0;
 567
 568 #ifdef CONFIG_TSEC1
 569         SET_STD_TSEC_INFO(tsec_info[num], 1);
 570         num++;
 571 #endif
 572 #ifdef CONFIG_TSEC2
 573         SET_STD_TSEC_INFO(tsec_info[num], 2);
 574         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 575                 tsec_info[num].flags |= TSEC_SGMII;
 576         num++;
 577 #endif
 578 #ifdef CONFIG_TSEC3
 579         SET_STD_TSEC_INFO(tsec_info[num], 3);
 580         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 581                 tsec_info[num].flags |= TSEC_SGMII;
 582         num++;
 583 #endif
 584
 585         if (!num) {
 586                 printf("No TSECs initialized\n");
 587
 588                 return 0;
 589         }
 590
 591 #ifdef CONFIG_FSL_SGMII_RISER
 592         fsl_sgmii_riser_init(tsec_info, num);
 593 #endif
 594
 595         tsec_eth_init(bis, tsec_info, num);
 596
 597         return 0;
 598 }
 599 #endif
 600
 601 #if defined(CONFIG_OF_BOARD_SETUP)
 602 void ft_board_setup(void *blob, bd_t *bd)
 603 {
 604         phys_addr_t base;
 605         phys_size_t size;
 606
 607         ft_cpu_setup(blob, bd);
 608
 609         base = getenv_bootm_low();
 610         size = getenv_bootm_size();
 611
 612         fdt_fixup_memory(blob, (u64)base, (u64)size);
 613
 614 #ifdef CONFIG_PCIE3
 615         ft_fsl_pci_setup(blob, "pci0", &pcie3_hose);
 616 #endif
 617 #ifdef CONFIG_PCIE2
 618         ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
 619 #endif
 620 #ifdef CONFIG_PCIE1
 621         ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
 622 #endif
 623 #ifdef CONFIG_FSL_SGMII_RISER
 624         fsl_sgmii_riser_fdt_fixup(blob);
 625 #endif
 626 }
 627 #endif
 628
 629 #ifdef CONFIG_MP
 630 void board_lmb_reserve(struct lmb *lmb)
 631 {
 632         cpu_mp_lmb_reserve(lmb);
 633 }
 634 #endif