board/freescale/t102xqds/eth_t102xqds.c

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * Shengzhou Liu <Shengzhou.Liu@freescale.com>
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <command.h>
  11 #include <netdev.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <malloc.h>
  20 #include <fm_eth.h>
  21 #include <fsl_mdio.h>
  22 #include <miiphy.h>
  23 #include <phy.h>
  24 #include <asm/fsl_dtsec.h>
  25 #include <asm/fsl_serdes.h>
  26 #include "../common/qixis.h"
  27 #include "../common/fman.h"
  28 #include "t102xqds_qixis.h"
  29
  30 #define EMI_NONE        0xFFFFFFFF
  31 #define EMI1_RGMII1     0
  32 #define EMI1_RGMII2     1
  33 #define EMI1_SLOT1      2
  34 #define EMI1_SLOT2      3
  35 #define EMI1_SLOT3      4
  36 #define EMI1_SLOT4      5
  37 #define EMI1_SLOT5      6
  38 #define EMI2            7
  39
  40 static int mdio_mux[NUM_FM_PORTS];
  41
  42 static const char * const mdio_names[] = {
  43         "T1024QDS_MDIO_RGMII1",
  44         "T1024QDS_MDIO_RGMII2",
  45         "T1024QDS_MDIO_SLOT1",
  46         "T1024QDS_MDIO_SLOT2",
  47         "T1024QDS_MDIO_SLOT3",
  48         "T1024QDS_MDIO_SLOT4",
  49         "T1024QDS_MDIO_SLOT5",
  50         "T1024QDS_MDIO_10GC",
  51         "NULL",
  52 };
  53
  54 /* Map SerDes1 4 lanes to default slot, will be initialized dynamically */
  55 static u8 lane_to_slot[] = {2, 3, 4, 5};
  56
  57 static const char *t1024qds_mdio_name_for_muxval(u8 muxval)
  58 {
  59         return mdio_names[muxval];
  60 }
  61
  62 struct mii_dev *mii_dev_for_muxval(u8 muxval)
  63 {
  64         struct mii_dev *bus;
  65         const char *name;
  66
  67         if (muxval > EMI2)
  68                 return NULL;
  69
  70         name = t1024qds_mdio_name_for_muxval(muxval);
  71
  72         if (!name) {
  73                 printf("No bus for muxval %x\n", muxval);
  74                 return NULL;
  75         }
  76
  77         bus = miiphy_get_dev_by_name(name);
  78
  79         if (!bus) {
  80                 printf("No bus by name %s\n", name);
  81                 return NULL;
  82         }
  83
  84         return bus;
  85 }
  86
  87 struct t1024qds_mdio {
  88         u8 muxval;
  89         struct mii_dev *realbus;
  90 };
  91
  92 static void t1024qds_mux_mdio(u8 muxval)
  93 {
  94         u8 brdcfg4;
  95
  96         if (muxval < 7) {
  97                 brdcfg4 = QIXIS_READ(brdcfg[4]);
  98                 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
  99                 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
 100                 QIXIS_WRITE(brdcfg[4], brdcfg4);
 101         }
 102 }
 103
 104 static int t1024qds_mdio_read(struct mii_dev *bus, int addr, int devad,
 105                               int regnum)
 106 {
 107         struct t1024qds_mdio *priv = bus->priv;
 108
 109         t1024qds_mux_mdio(priv->muxval);
 110
 111         return priv->realbus->read(priv->realbus, addr, devad, regnum);
 112 }
 113
 114 static int t1024qds_mdio_write(struct mii_dev *bus, int addr, int devad,
 115                                int regnum, u16 value)
 116 {
 117         struct t1024qds_mdio *priv = bus->priv;
 118
 119         t1024qds_mux_mdio(priv->muxval);
 120
 121         return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
 122 }
 123
 124 static int t1024qds_mdio_reset(struct mii_dev *bus)
 125 {
 126         struct t1024qds_mdio *priv = bus->priv;
 127
 128         return priv->realbus->reset(priv->realbus);
 129 }
 130
 131 static int t1024qds_mdio_init(char *realbusname, u8 muxval)
 132 {
 133         struct t1024qds_mdio *pmdio;
 134         struct mii_dev *bus = mdio_alloc();
 135
 136         if (!bus) {
 137                 printf("Failed to allocate t1024qds MDIO bus\n");
 138                 return -1;
 139         }
 140
 141         pmdio = malloc(sizeof(*pmdio));
 142         if (!pmdio) {
 143                 printf("Failed to allocate t1024qds private data\n");
 144                 free(bus);
 145                 return -1;
 146         }
 147
 148         bus->read = t1024qds_mdio_read;
 149         bus->write = t1024qds_mdio_write;
 150         bus->reset = t1024qds_mdio_reset;
 151         sprintf(bus->name, t1024qds_mdio_name_for_muxval(muxval));
 152
 153         pmdio->realbus = miiphy_get_dev_by_name(realbusname);
 154
 155         if (!pmdio->realbus) {
 156                 printf("No bus with name %s\n", realbusname);
 157                 free(bus);
 158                 free(pmdio);
 159                 return -1;
 160         }
 161
 162         pmdio->muxval = muxval;
 163         bus->priv = pmdio;
 164         return mdio_register(bus);
 165 }
 166
 167 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
 168                               enum fm_port port, int offset)
 169 {
 170         struct fixed_link f_link;
 171
 172         if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_RGMII) {
 173                 if (port == FM1_DTSEC3) {
 174                         fdt_set_phy_handle(fdt, compat, addr, "rgmii_phy2");
 175                         fdt_setprop(fdt, offset, "phy-connection-type",
 176                                     "rgmii", 5);
 177                         fdt_status_okay_by_alias(fdt, "emi1_rgmii1");
 178                 }
 179         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
 180                 if (port == FM1_DTSEC1) {
 181                         fdt_set_phy_handle(fdt, compat, addr,
 182                                            "sgmii_vsc8234_phy_s5");
 183                 } else if (port == FM1_DTSEC2) {
 184                         fdt_set_phy_handle(fdt, compat, addr,
 185                                            "sgmii_vsc8234_phy_s4");
 186                 }
 187         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
 188                 if (port == FM1_DTSEC3) {
 189                         fdt_set_phy_handle(fdt, compat, addr,
 190                                            "sgmii_aqr105_phy_s3");
 191                 }
 192         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
 193                 switch (port) {
 194                 case FM1_DTSEC1:
 195                         fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p1");
 196                         break;
 197                 case FM1_DTSEC2:
 198                         fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p2");
 199                         break;
 200                 case FM1_DTSEC3:
 201                         fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p3");
 202                         break;
 203                 case FM1_DTSEC4:
 204                         fdt_set_phy_handle(fdt, compat, addr, "qsgmii_phy_p4");
 205                         break;
 206                 default:
 207                         break;
 208                 }
 209                 fdt_delprop(fdt, offset, "phy-connection-type");
 210                 fdt_setprop(fdt, offset, "phy-connection-type", "qsgmii", 6);
 211                 fdt_status_okay_by_alias(fdt, "emi1_slot2");
 212         } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
 213                 /* XFI interface */
 214                 f_link.phy_id = port;
 215                 f_link.duplex = 1;
 216                 f_link.link_speed = 10000;
 217                 f_link.pause = 0;
 218                 f_link.asym_pause = 0;
 219                 /* no PHY for XFI */
 220                 fdt_delprop(fdt, offset, "phy-handle");
 221                 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
 222                 fdt_setprop(fdt, offset, "phy-connection-type", "xgmii", 5);
 223         }
 224 }
 225
 226 void fdt_fixup_board_enet(void *fdt)
 227 {
 228 }
 229
 230 /*
 231  * This function reads RCW to check if Serdes1{A:D} is configured
 232  * to slot 1/2/3/4/5 and update the lane_to_slot[] array accordingly
 233  */
 234 static void initialize_lane_to_slot(void)
 235 {
 236         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 237         u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
 238                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 239
 240         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 241
 242         switch (srds_s1) {
 243         case 0x46:
 244         case 0x47:
 245                 lane_to_slot[1] = 2;
 246                 break;
 247         default:
 248                 break;
 249         }
 250 }
 251
 252 int board_eth_init(bd_t *bis)
 253 {
 254 #if defined(CONFIG_FMAN_ENET)
 255         int i, idx, lane, slot, interface;
 256         struct memac_mdio_info dtsec_mdio_info;
 257         struct memac_mdio_info tgec_mdio_info;
 258         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 259         u32 srds_s1;
 260
 261         srds_s1 = in_be32(&gur->rcwsr[4]) &
 262                                         FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
 263         srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
 264
 265         initialize_lane_to_slot();
 266
 267         /* Initialize the mdio_mux array so we can recognize empty elements */
 268         for (i = 0; i < NUM_FM_PORTS; i++)
 269                 mdio_mux[i] = EMI_NONE;
 270
 271         dtsec_mdio_info.regs =
 272                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
 273
 274         dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
 275
 276         /* Register the 1G MDIO bus */
 277         fm_memac_mdio_init(bis, &dtsec_mdio_info);
 278
 279         tgec_mdio_info.regs =
 280                 (struct memac_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR;
 281         tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME;
 282
 283         /* Register the 10G MDIO bus */
 284         fm_memac_mdio_init(bis, &tgec_mdio_info);
 285
 286         /* Register the muxing front-ends to the MDIO buses */
 287         t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
 288         t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
 289         t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
 290         t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
 291         t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT3);
 292         t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
 293         t1024qds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT5);
 294         t1024qds_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, EMI2);
 295
 296         /* Set the two on-board RGMII PHY address */
 297         fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
 298         fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
 299
 300         switch (srds_s1) {
 301         case 0xd5:
 302         case 0xd6:
 303                 /* QSGMII in Slot2 */
 304                 fm_info_set_phy_address(FM1_DTSEC1, 0x8);
 305                 fm_info_set_phy_address(FM1_DTSEC2, 0x9);
 306                 fm_info_set_phy_address(FM1_DTSEC3, 0xa);
 307                 fm_info_set_phy_address(FM1_DTSEC4, 0xb);
 308                 break;
 309         case 0x95:
 310         case 0x99:
 311                 /*
 312                  * XFI does not need a PHY to work, but to avoid U-boot use
 313                  * default PHY address which is zero to a MAC when it found
 314                  * a MAC has no PHY address, we give a PHY address to XFI
 315                  * MAC, and should not use a real XAUI PHY address, since
 316                  * MDIO can access it successfully, and then MDIO thinks the
 317                  * XAUI card is used for the XFI MAC, which will cause error.
 318                  */
 319                 fm_info_set_phy_address(FM1_10GEC1, 4);
 320                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 321                 break;
 322         case 0x6f:
 323                 /* SGMII in Slot3, Slot4, Slot5 */
 324                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
 325                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
 326                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
 327                 break;
 328         case 0x7f:
 329                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_AQ_PHY_ADDR_S5);
 330                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_AQ_PHY_ADDR_S4);
 331                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
 332                 break;
 333         case 0x47:
 334                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 335                 break;
 336         case 0x77:
 337                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 338                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_AQ_PHY_ADDR_S3);
 339                 break;
 340         case 0x5a:
 341                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 342                 break;
 343         case 0x6a:
 344                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 345                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
 346                 break;
 347         case 0x5b:
 348                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 349                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 350                 break;
 351         case 0x6b:
 352                 fm_info_set_phy_address(FM1_DTSEC1, SGMII_CARD_PORT1_PHY_ADDR);
 353                 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
 354                 fm_info_set_phy_address(FM1_DTSEC3, SGMII_CARD_PORT1_PHY_ADDR);
 355                 break;
 356         default:
 357                 break;
 358         }
 359
 360         for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
 361                 idx = i - FM1_DTSEC1;
 362                 interface = fm_info_get_enet_if(i);
 363                 switch (interface) {
 364                 case PHY_INTERFACE_MODE_SGMII:
 365                 case PHY_INTERFACE_MODE_SGMII_2500:
 366                 case PHY_INTERFACE_MODE_QSGMII:
 367                         if (interface == PHY_INTERFACE_MODE_SGMII) {
 368                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 369                                                 SGMII_FM1_DTSEC1 + idx);
 370                         } else if (interface == PHY_INTERFACE_MODE_SGMII_2500) {
 371                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 372                                                 SGMII_2500_FM1_DTSEC1 + idx);
 373                         } else {
 374                                 lane = serdes_get_first_lane(FSL_SRDS_1,
 375                                                 QSGMII_FM1_A);
 376                         }
 377
 378                         if (lane < 0)
 379                                 break;
 380
 381                         slot = lane_to_slot[lane];
 382                         debug("FM1@DTSEC%u expects SGMII in slot %u\n",
 383                               idx + 1, slot);
 384                         if (QIXIS_READ(present2) & (1 << (slot - 1)))
 385                                 fm_disable_port(i);
 386
 387                         switch (slot) {
 388                         case 2:
 389                                 mdio_mux[i] = EMI1_SLOT2;
 390                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 391                                                  mdio_mux[i]));
 392                                 break;
 393                         case 3:
 394                                 mdio_mux[i] = EMI1_SLOT3;
 395                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 396                                                  mdio_mux[i]));
 397                                 break;
 398                         case 4:
 399                                 mdio_mux[i] = EMI1_SLOT4;
 400                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 401                                                  mdio_mux[i]));
 402                                 break;
 403                         case 5:
 404                                 mdio_mux[i] = EMI1_SLOT5;
 405                                 fm_info_set_mdio(i, mii_dev_for_muxval(
 406                                                  mdio_mux[i]));
 407                                 break;
 408                         }
 409                         break;
 410                 case PHY_INTERFACE_MODE_RGMII:
 411                         if (i == FM1_DTSEC3)
 412                                 mdio_mux[i] = EMI1_RGMII2;
 413                         else if (i == FM1_DTSEC4)
 414                                 mdio_mux[i] = EMI1_RGMII1;
 415                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 416                         break;
 417                 default:
 418                         break;
 419                 }
 420         }
 421
 422         for (i = FM1_10GEC1; i < FM1_10GEC1 + CONFIG_SYS_NUM_FM1_10GEC; i++) {
 423                 idx = i - FM1_10GEC1;
 424                 switch (fm_info_get_enet_if(i)) {
 425                 case PHY_INTERFACE_MODE_XGMII:
 426                         lane = serdes_get_first_lane(FSL_SRDS_1,
 427                                                      XFI_FM1_MAC1 + idx);
 428                         if (lane < 0)
 429                                 break;
 430                         mdio_mux[i] = EMI2;
 431                         fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
 432                         break;
 433                 default:
 434                         break;
 435                 }
 436         }
 437
 438         cpu_eth_init(bis);
 439 #endif /* CONFIG_FMAN_ENET */
 440
 441         return pci_eth_init(bis);
 442 }