board/freescale/t2080qds/t2080qds.c

   1 /*
   2  * Copyright 2009-2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <command.h>
   9 #include <i2c.h>
  10 #include <netdev.h>
  11 #include <linux/compiler.h>
  12 #include <asm/mmu.h>
  13 #include <asm/processor.h>
  14 #include <asm/immap_85xx.h>
  15 #include <asm/fsl_law.h>
  16 #include <asm/fsl_serdes.h>
  17 #include <asm/fsl_portals.h>
  18 #include <asm/fsl_liodn.h>
  19 #include <fm_eth.h>
  20
  21 #include "../common/qixis.h"
  22 #include "../common/vsc3316_3308.h"
  23 #include "t2080qds.h"
  24 #include "t2080qds_qixis.h"
  25
  26 DECLARE_GLOBAL_DATA_PTR;
  27
  28 int checkboard(void)
  29 {
  30         char buf[64];
  31         u8 sw;
  32         struct cpu_type *cpu = gd->arch.cpu;
  33         static const char *freq[4] = {
  34                 "100.00MHZ(from 8T49N222A)", "125.00MHz",
  35                 "156.25MHZ", "100.00MHz"
  36         };
  37
  38         printf("Board: %sQDS, ", cpu->name);
  39         sw = QIXIS_READ(arch);
  40         printf("Sys ID: 0x%02x, Board Arch: V%d, ", QIXIS_READ(id), sw >> 4);
  41         printf("Board Version: %c, boot from ", (sw & 0xf) + 'A' - 1);
  42
  43 #ifdef CONFIG_SDCARD
  44         puts("SD/MMC\n");
  45 #elif CONFIG_SPIFLASH
  46         puts("SPI\n");
  47 #else
  48         sw = QIXIS_READ(brdcfg[0]);
  49         sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
  50
  51         if (sw < 0x8)
  52                 printf("vBank%d\n", sw);
  53         else if (sw == 0x8)
  54                 puts("Promjet\n");
  55         else if (sw == 0x9)
  56                 puts("NAND\n");
  57         else
  58                 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
  59 #endif
  60
  61         printf("FPGA: v%d (%s), build %d", (int)QIXIS_READ(scver),
  62                qixis_read_tag(buf), (int)qixis_read_minor());
  63         /* the timestamp string contains "\n" at the end */
  64         printf(" on %s", qixis_read_time(buf));
  65
  66         puts("SERDES Reference Clocks:\n");
  67         sw = QIXIS_READ(brdcfg[2]);
  68         printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[sw >> 6],
  69                freq[(sw >> 4) & 0x3]);
  70         printf("SD2_CLK1=%s, SD2_CLK2=%s\n", freq[(sw & 0xf) >> 2],
  71                freq[sw & 0x3]);
  72
  73         return 0;
  74 }
  75
  76 int select_i2c_ch_pca9547(u8 ch)
  77 {
  78         int ret;
  79
  80         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  81         if (ret) {
  82                 puts("PCA: failed to select proper channel\n");
  83                 return ret;
  84         }
  85
  86         return 0;
  87 }
  88
  89 int brd_mux_lane_to_slot(void)
  90 {
  91         ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  92         u32 srds_prtcl_s1, srds_prtcl_s2;
  93
  94         srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) &
  95                                 FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
  96         srds_prtcl_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
  97         srds_prtcl_s2 = in_be32(&gur->rcwsr[4]) &
  98                                 FSL_CORENET2_RCWSR4_SRDS2_PRTCL;
  99         srds_prtcl_s2 >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT;
 100
 101         switch (srds_prtcl_s1) {
 102         case 0:
 103                 /* SerDes1 is not enabled */
 104                 break;
 105         case 0x1c:
 106         case 0xa2:
 107                 /* SD1(A:D) => SLOT3 SGMII
 108                  * SD1(G:H) => SLOT1 SGMII
 109                  */
 110                 QIXIS_WRITE(brdcfg[12], 0x1a);
 111                 break;
 112         case 0x94:
 113         case 0x95:
 114                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 115                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 116                  * SD1(E:H) => SLOT1 SGMII@1.25bps
 117                  */
 118         case 0x96:
 119                 /* SD1(A:B) => SLOT3 SGMII@1.25bps
 120                  * SD1(C)   => SFP Module, SGMII@3.125bps
 121                  * SD1(D)   => SFP Module, SGMII@1.25bps
 122                  * SD1(E:H) => SLOT1 PCIe4 x4
 123                  */
 124                 QIXIS_WRITE(brdcfg[12], 0x3a);
 125                 break;
 126         case 0x51:
 127                 /* SD1(A:D) => SLOT3 XAUI
 128                  * SD1(E)   => SLOT1 PCIe4
 129                  * SD1(F:H) => SLOT2 SGMII
 130                  */
 131                 QIXIS_WRITE(brdcfg[12], 0x15);
 132                 break;
 133         case 0x66:
 134         case 0x67:
 135                 /* SD1(A:D) => XFI cage
 136                  * SD1(E:H) => SLOT1 PCIe4
 137                  */
 138                 QIXIS_WRITE(brdcfg[12], 0xfe);
 139                 break;
 140         case 0x6b:
 141                 /* SD1(A:D) => XFI cage
 142                  * SD1(E)   => SLOT1 PCIe4
 143                  * SD1(F:H) => SLOT2 SGMII
 144                  */
 145                 QIXIS_WRITE(brdcfg[12], 0xf1);
 146                 break;
 147         case 0x6c:
 148         case 0x6d:
 149                 /* SD1(A:B) => XFI cage
 150                  * SD1(C:D) => SLOT3 SGMII
 151                  * SD1(E:H) => SLOT1 PCIe4
 152                  */
 153                 QIXIS_WRITE(brdcfg[12], 0xda);
 154                 break;
 155         case 0x6e:
 156                 /* SD1(A:B) => SFP Module, XFI
 157                  * SD1(C:D) => SLOT3 SGMII
 158                  * SD1(E:F) => SLOT1 PCIe4 x2
 159                  * SD1(G:H) => SLOT2 SGMII
 160                  */
 161                 QIXIS_WRITE(brdcfg[12], 0xd9);
 162                 break;
 163         case 0xda:
 164                 /* SD1(A:H) => SLOT3 PCIe3 x8
 165                  */
 166                  QIXIS_WRITE(brdcfg[12], 0x0);
 167                  break;
 168         case 0xc8:
 169                 /* SD1(A)   => SLOT3 PCIe3 x1
 170                  * SD1(B)   => SFP Module, SGMII@1.25bps
 171                  * SD1(C:D) => SFP Module, SGMII@3.125bps
 172                  * SD1(E:F) => SLOT1 PCIe4 x2
 173                  * SD1(G:H) => SLOT2 SGMII
 174                  */
 175                  QIXIS_WRITE(brdcfg[12], 0x79);
 176                  break;
 177         case 0xab:
 178                 /* SD1(A:D) => SLOT3 PCIe3 x4
 179                  * SD1(E:H) => SLOT1 PCIe4 x4
 180                  */
 181                  QIXIS_WRITE(brdcfg[12], 0x1a);
 182                  break;
 183         default:
 184                 printf("WARNING: unsupported for SerDes1 Protocol %d\n",
 185                        srds_prtcl_s1);
 186                 return -1;
 187         }
 188
 189         switch (srds_prtcl_s2) {
 190         case 0:
 191                 /* SerDes2 is not enabled */
 192                 break;
 193         case 0x01:
 194         case 0x02:
 195                 /* SD2(A:H) => SLOT4 PCIe1 */
 196                 QIXIS_WRITE(brdcfg[13], 0x10);
 197                 break;
 198         case 0x15:
 199         case 0x16:
 200                 /*
 201                  * SD2(A:D) => SLOT4 PCIe1
 202                  * SD2(E:F) => SLOT5 PCIe2
 203                  * SD2(G:H) => SATA1,SATA2
 204                  */
 205                 QIXIS_WRITE(brdcfg[13], 0xb0);
 206                 break;
 207         case 0x18:
 208                 /*
 209                  * SD2(A:D) => SLOT4 PCIe1
 210                  * SD2(E:F) => SLOT5 Aurora
 211                  * SD2(G:H) => SATA1,SATA2
 212                  */
 213                 QIXIS_WRITE(brdcfg[13], 0x78);
 214                 break;
 215         case 0x1f:
 216                 /*
 217                  * SD2(A:D) => SLOT4 PCIe1
 218                  * SD2(E:H) => SLOT5 PCIe2
 219                  */
 220                 QIXIS_WRITE(brdcfg[13], 0xa0);
 221                 break;
 222         case 0x29:
 223         case 0x2d:
 224         case 0x2e:
 225                 /*
 226                  * SD2(A:D) => SLOT4 SRIO2
 227                  * SD2(E:H) => SLOT5 SRIO1
 228                  */
 229                 QIXIS_WRITE(brdcfg[13], 0xa0);
 230                 break;
 231         case 0x36:
 232                 /*
 233                  * SD2(A:D) => SLOT4 SRIO2
 234                  * SD2(E:F) => Aurora
 235                  * SD2(G:H) => SATA1,SATA2
 236                  */
 237                 QIXIS_WRITE(brdcfg[13], 0x78);
 238                 break;
 239         default:
 240                 printf("WARNING: unsupported for SerDes2 Protocol %d\n",
 241                        srds_prtcl_s2);
 242                 return -1;
 243         }
 244         return 0;
 245 }
 246
 247 int board_early_init_r(void)
 248 {
 249         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 250         const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
 251
 252         /*
 253          * Remap Boot flash + PROMJET region to caching-inhibited
 254          * so that flash can be erased properly.
 255          */
 256
 257         /* Flush d-cache and invalidate i-cache of any FLASH data */
 258         flush_dcache();
 259         invalidate_icache();
 260
 261         /* invalidate existing TLB entry for flash + promjet */
 262         disable_tlb(flash_esel);
 263
 264         set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
 265                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 266                 0, flash_esel, BOOKE_PAGESZ_256M, 1);
 267
 268         set_liodns();
 269 #ifdef CONFIG_SYS_DPAA_QBMAN
 270         setup_portals();
 271 #endif
 272
 273         /* Disable remote I2C connection to qixis fpga */
 274         QIXIS_WRITE(brdcfg[5], QIXIS_READ(brdcfg[5]) & ~BRDCFG5_IRE);
 275
 276         brd_mux_lane_to_slot();
 277         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 278
 279         return 0;
 280 }
 281
 282 unsigned long get_board_sys_clk(void)
 283 {
 284         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 285 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 286         /* use accurate clock measurement */
 287         int freq = QIXIS_READ(clk_freq[0]) << 8 | QIXIS_READ(clk_freq[1]);
 288         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 289         u32 val;
 290
 291         val =  freq * base;
 292         if (val) {
 293                 debug("SYS Clock measurement is: %d\n", val);
 294                 return val;
 295         } else {
 296                 printf("Warning: SYS clock measurement is invalid, ");
 297                 printf("using value from brdcfg1.\n");
 298         }
 299 #endif
 300
 301         switch (sysclk_conf & 0x0F) {
 302         case QIXIS_SYSCLK_83:
 303                 return 83333333;
 304         case QIXIS_SYSCLK_100:
 305                 return 100000000;
 306         case QIXIS_SYSCLK_125:
 307                 return 125000000;
 308         case QIXIS_SYSCLK_133:
 309                 return 133333333;
 310         case QIXIS_SYSCLK_150:
 311                 return 150000000;
 312         case QIXIS_SYSCLK_160:
 313                 return 160000000;
 314         case QIXIS_SYSCLK_166:
 315                 return 166666666;
 316         }
 317         return 66666666;
 318 }
 319
 320 unsigned long get_board_ddr_clk(void)
 321 {
 322         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 323 #ifdef CONFIG_FSL_QIXIS_CLOCK_MEASUREMENT
 324         /* use accurate clock measurement */
 325         int freq = QIXIS_READ(clk_freq[2]) << 8 | QIXIS_READ(clk_freq[3]);
 326         int base = QIXIS_READ(clk_base[0]) << 8 | QIXIS_READ(clk_base[1]);
 327         u32 val;
 328
 329         val =  freq * base;
 330         if (val) {
 331                 debug("DDR Clock measurement is: %d\n", val);
 332                 return val;
 333         } else {
 334                 printf("Warning: DDR clock measurement is invalid, ");
 335                 printf("using value from brdcfg1.\n");
 336         }
 337 #endif
 338
 339         switch ((ddrclk_conf & 0x30) >> 4) {
 340         case QIXIS_DDRCLK_100:
 341                 return 100000000;
 342         case QIXIS_DDRCLK_125:
 343                 return 125000000;
 344         case QIXIS_DDRCLK_133:
 345                 return 133333333;
 346         }
 347         return 66666666;
 348 }
 349
 350 int misc_init_r(void)
 351 {
 352         return 0;
 353 }
 354
 355 void ft_board_setup(void *blob, bd_t *bd)
 356 {
 357         phys_addr_t base;
 358         phys_size_t size;
 359
 360         ft_cpu_setup(blob, bd);
 361
 362         base = getenv_bootm_low();
 363         size = getenv_bootm_size();
 364
 365         fdt_fixup_memory(blob, (u64)base, (u64)size);
 366
 367 #ifdef CONFIG_PCI
 368         pci_of_setup(blob, bd);
 369 #endif
 370
 371         fdt_fixup_liodn(blob);
 372         fdt_fixup_dr_usb(blob, bd);
 373
 374 #ifdef CONFIG_SYS_DPAA_FMAN
 375         fdt_fixup_fman_ethernet(blob);
 376         fdt_fixup_board_enet(blob);
 377 #endif
 378 }