board/gateworks/gw_ventana/gw_ventana.c

   1 /*
   2  * Copyright (C) 2013 Gateworks Corporation
   3  *
   4  * Author: Tim Harvey <tharvey@gateworks.com>
   5  *
   6  * SPDX-License-Identifier: GPL-2.0+
   7  */
   8
   9 #include <common.h>
  10 #include <asm/io.h>
  11 #include <asm/arch/clock.h>
  12 #include <asm/arch/imx-regs.h>
  13 #include <asm/arch/iomux.h>
  14 #include <asm/arch/mx6-pins.h>
  15 #include <asm/arch/mxc_hdmi.h>
  16 #include <asm/arch/crm_regs.h>
  17 #include <asm/arch/sys_proto.h>
  18 #include <asm/gpio.h>
  19 #include <asm/imx-common/iomux-v3.h>
  20 #include <asm/imx-common/mxc_i2c.h>
  21 #include <asm/imx-common/boot_mode.h>
  22 #include <asm/imx-common/sata.h>
  23 #include <asm/imx-common/video.h>
  24 #include <jffs2/load_kernel.h>
  25 #include <hwconfig.h>
  26 #include <i2c.h>
  27 #include <linux/ctype.h>
  28 #include <fdt_support.h>
  29 #include <fsl_esdhc.h>
  30 #include <miiphy.h>
  31 #include <mmc.h>
  32 #include <mtd_node.h>
  33 #include <netdev.h>
  34 #include <power/pmic.h>
  35 #include <power/ltc3676_pmic.h>
  36 #include <power/pfuze100_pmic.h>
  37 #include <fdt_support.h>
  38 #include <jffs2/load_kernel.h>
  39 #include <spi_flash.h>
  40
  41 #include "gsc.h"
  42 #include "ventana_eeprom.h"
  43
  44 DECLARE_GLOBAL_DATA_PTR;
  45
  46 /* GPIO's common to all baseboards */
  47 #define GP_PHY_RST      IMX_GPIO_NR(1, 30)
  48 #define GP_USB_OTG_PWR  IMX_GPIO_NR(3, 22)
  49 #define GP_SD3_CD       IMX_GPIO_NR(7, 0)
  50 #define GP_RS232_EN     IMX_GPIO_NR(2, 11)
  51 #define GP_MSATA_SEL    IMX_GPIO_NR(2, 8)
  52
  53 /* I2C bus numbers */
  54 #define I2C_GSC         0
  55 #define I2C_PMIC        1
  56
  57 #define UART_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  58         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  59         PAD_CTL_DSE_40ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  60
  61 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |             \
  62         PAD_CTL_PUS_47K_UP  | PAD_CTL_SPEED_LOW |               \
  63         PAD_CTL_DSE_80ohm   | PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
  64
  65 #define ENET_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |             \
  66         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED   |             \
  67         PAD_CTL_DSE_40ohm   | PAD_CTL_HYS)
  68
  69 #define SPI_PAD_CTRL (PAD_CTL_HYS |                             \
  70         PAD_CTL_PUS_100K_DOWN | PAD_CTL_SPEED_MED |             \
  71         PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
  72
  73 #define DIO_PAD_CTRL  (PAD_CTL_PKE | PAD_CTL_PUE |              \
  74         PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |               \
  75         PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST)
  76
  77 #define I2C_PAD_CTRL  (PAD_CTL_PUS_100K_UP |                    \
  78         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
  79         PAD_CTL_ODE | PAD_CTL_SRE_FAST)
  80
  81 /*
  82  * EEPROM board info struct populated by read_eeprom so that we only have to
  83  * read it once.
  84  */
  85 static struct ventana_board_info ventana_info;
  86
  87 int board_type;
  88
  89 /* UART1: Function varies per baseboard */
  90 iomux_v3_cfg_t const uart1_pads[] = {
  91         IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  92         IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  93 };
  94
  95 /* UART2: Serial Console */
  96 iomux_v3_cfg_t const uart2_pads[] = {
  97         IOMUX_PADS(PAD_SD4_DAT7__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  98         IOMUX_PADS(PAD_SD4_DAT4__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
  99 };
 100
 101 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 102
 103 /* I2C1: GSC */
 104 struct i2c_pads_info mx6q_i2c_pad_info0 = {
 105         .scl = {
 106                 .i2c_mode = MX6Q_PAD_EIM_D21__I2C1_SCL | PC,
 107                 .gpio_mode = MX6Q_PAD_EIM_D21__GPIO3_IO21 | PC,
 108                 .gp = IMX_GPIO_NR(3, 21)
 109         },
 110         .sda = {
 111                 .i2c_mode = MX6Q_PAD_EIM_D28__I2C1_SDA | PC,
 112                 .gpio_mode = MX6Q_PAD_EIM_D28__GPIO3_IO28 | PC,
 113                 .gp = IMX_GPIO_NR(3, 28)
 114         }
 115 };
 116 struct i2c_pads_info mx6dl_i2c_pad_info0 = {
 117         .scl = {
 118                 .i2c_mode = MX6DL_PAD_EIM_D21__I2C1_SCL | PC,
 119                 .gpio_mode = MX6DL_PAD_EIM_D21__GPIO3_IO21 | PC,
 120                 .gp = IMX_GPIO_NR(3, 21)
 121         },
 122         .sda = {
 123                 .i2c_mode = MX6DL_PAD_EIM_D28__I2C1_SDA | PC,
 124                 .gpio_mode = MX6DL_PAD_EIM_D28__GPIO3_IO28 | PC,
 125                 .gp = IMX_GPIO_NR(3, 28)
 126         }
 127 };
 128
 129 /* I2C2: PMIC/PCIe Switch/PCIe Clock/Mezz */
 130 struct i2c_pads_info mx6q_i2c_pad_info1 = {
 131         .scl = {
 132                 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL | PC,
 133                 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 | PC,
 134                 .gp = IMX_GPIO_NR(4, 12)
 135         },
 136         .sda = {
 137                 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA | PC,
 138                 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 139                 .gp = IMX_GPIO_NR(4, 13)
 140         }
 141 };
 142 struct i2c_pads_info mx6dl_i2c_pad_info1 = {
 143         .scl = {
 144                 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL | PC,
 145                 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 | PC,
 146                 .gp = IMX_GPIO_NR(4, 12)
 147         },
 148         .sda = {
 149                 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA | PC,
 150                 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 151                 .gp = IMX_GPIO_NR(4, 13)
 152         }
 153 };
 154
 155 /* I2C3: Misc/Expansion */
 156 struct i2c_pads_info mx6q_i2c_pad_info2 = {
 157         .scl = {
 158                 .i2c_mode = MX6Q_PAD_GPIO_3__I2C3_SCL | PC,
 159                 .gpio_mode = MX6Q_PAD_GPIO_3__GPIO1_IO03 | PC,
 160                 .gp = IMX_GPIO_NR(1, 3)
 161         },
 162         .sda = {
 163                 .i2c_mode = MX6Q_PAD_GPIO_6__I2C3_SDA | PC,
 164                 .gpio_mode = MX6Q_PAD_GPIO_6__GPIO1_IO06 | PC,
 165                 .gp = IMX_GPIO_NR(1, 6)
 166         }
 167 };
 168 struct i2c_pads_info mx6dl_i2c_pad_info2 = {
 169         .scl = {
 170                 .i2c_mode = MX6DL_PAD_GPIO_3__I2C3_SCL | PC,
 171                 .gpio_mode = MX6DL_PAD_GPIO_3__GPIO1_IO03 | PC,
 172                 .gp = IMX_GPIO_NR(1, 3)
 173         },
 174         .sda = {
 175                 .i2c_mode = MX6DL_PAD_GPIO_6__I2C3_SDA | PC,
 176                 .gpio_mode = MX6DL_PAD_GPIO_6__GPIO1_IO06 | PC,
 177                 .gp = IMX_GPIO_NR(1, 6)
 178         }
 179 };
 180
 181 /* MMC */
 182 iomux_v3_cfg_t const usdhc3_pads[] = {
 183         IOMUX_PADS(PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 184         IOMUX_PADS(PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 185         IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 186         IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 187         IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 188         IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)),
 189         /* CD */
 190         IOMUX_PADS(PAD_SD3_DAT5__GPIO7_IO00  | MUX_PAD_CTRL(NO_PAD_CTRL)),
 191 };
 192
 193 /* ENET */
 194 iomux_v3_cfg_t const enet_pads[] = {
 195         IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 196         IOMUX_PADS(PAD_ENET_MDC__ENET_MDC    | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 197         IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 198         IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 199         IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 200         IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 201         IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 202         IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL |
 203                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 204         IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK |
 205                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 206         IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 207         IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 208         IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 209         IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 210         IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3  | MUX_PAD_CTRL(ENET_PAD_CTRL)),
 211         IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL |
 212                    MUX_PAD_CTRL(ENET_PAD_CTRL)),
 213         /* PHY nRST */
 214         IOMUX_PADS(PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 215 };
 216
 217 /* NAND */
 218 iomux_v3_cfg_t const nfc_pads[] = {
 219         IOMUX_PADS(PAD_NANDF_CLE__NAND_CLE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 220         IOMUX_PADS(PAD_NANDF_ALE__NAND_ALE     | MUX_PAD_CTRL(NO_PAD_CTRL)),
 221         IOMUX_PADS(PAD_NANDF_WP_B__NAND_WP_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 222         IOMUX_PADS(PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL)),
 223         IOMUX_PADS(PAD_NANDF_CS0__NAND_CE0_B   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 224         IOMUX_PADS(PAD_SD4_CMD__NAND_RE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 225         IOMUX_PADS(PAD_SD4_CLK__NAND_WE_B      | MUX_PAD_CTRL(NO_PAD_CTRL)),
 226         IOMUX_PADS(PAD_NANDF_D0__NAND_DATA00   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 227         IOMUX_PADS(PAD_NANDF_D1__NAND_DATA01   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 228         IOMUX_PADS(PAD_NANDF_D2__NAND_DATA02   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 229         IOMUX_PADS(PAD_NANDF_D3__NAND_DATA03   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 230         IOMUX_PADS(PAD_NANDF_D4__NAND_DATA04   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 231         IOMUX_PADS(PAD_NANDF_D5__NAND_DATA05   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 232         IOMUX_PADS(PAD_NANDF_D6__NAND_DATA06   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 233         IOMUX_PADS(PAD_NANDF_D7__NAND_DATA07   | MUX_PAD_CTRL(NO_PAD_CTRL)),
 234 };
 235
 236 #ifdef CONFIG_CMD_NAND
 237 static void setup_gpmi_nand(void)
 238 {
 239         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 240
 241         /* config gpmi nand iomux */
 242         SETUP_IOMUX_PADS(nfc_pads);
 243
 244         /* config gpmi and bch clock to 100 MHz */
 245         clrsetbits_le32(&mxc_ccm->cs2cdr,
 246                         MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
 247                         MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
 248                         MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
 249                         MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
 250                         MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
 251                         MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
 252
 253         /* enable gpmi and bch clock gating */
 254         setbits_le32(&mxc_ccm->CCGR4,
 255                      MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
 256                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
 257                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
 258                      MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
 259                      MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
 260
 261         /* enable apbh clock gating */
 262         setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
 263 }
 264 #endif
 265
 266 static void setup_iomux_enet(void)
 267 {
 268         SETUP_IOMUX_PADS(enet_pads);
 269
 270         /* toggle PHY_RST# */
 271         gpio_direction_output(GP_PHY_RST, 0);
 272         mdelay(2);
 273         gpio_set_value(GP_PHY_RST, 1);
 274 }
 275
 276 static void setup_iomux_uart(void)
 277 {
 278         SETUP_IOMUX_PADS(uart1_pads);
 279         SETUP_IOMUX_PADS(uart2_pads);
 280 }
 281
 282 #ifdef CONFIG_USB_EHCI_MX6
 283 iomux_v3_cfg_t const usb_pads[] = {
 284         IOMUX_PADS(PAD_GPIO_1__USB_OTG_ID   | MUX_PAD_CTRL(DIO_PAD_CTRL)),
 285         IOMUX_PADS(PAD_KEY_COL4__USB_OTG_OC | MUX_PAD_CTRL(DIO_PAD_CTRL)),
 286         /* OTG PWR */
 287         IOMUX_PADS(PAD_EIM_D22__GPIO3_IO22  | MUX_PAD_CTRL(DIO_PAD_CTRL)),
 288 };
 289
 290 int board_ehci_hcd_init(int port)
 291 {
 292         struct ventana_board_info *info = &ventana_info;
 293
 294         SETUP_IOMUX_PADS(usb_pads);
 295
 296         /* Reset USB HUB (present on GW54xx/GW53xx) */
 297         switch (info->model[3]) {
 298         case '3': /* GW53xx */
 299                 SETUP_IOMUX_PAD(PAD_GPIO_9__GPIO1_IO09 |
 300                                 MUX_PAD_CTRL(NO_PAD_CTRL));
 301                 gpio_direction_output(IMX_GPIO_NR(1, 9), 0);
 302                 mdelay(2);
 303                 gpio_set_value(IMX_GPIO_NR(1, 9), 1);
 304                 break;
 305         case '4': /* GW54xx */
 306                 SETUP_IOMUX_PAD(PAD_SD1_DAT0__GPIO1_IO16 |
 307                                 MUX_PAD_CTRL(NO_PAD_CTRL));
 308                 gpio_direction_output(IMX_GPIO_NR(1, 16), 0);
 309                 mdelay(2);
 310                 gpio_set_value(IMX_GPIO_NR(1, 16), 1);
 311                 break;
 312         }
 313
 314         return 0;
 315 }
 316
 317 int board_ehci_power(int port, int on)
 318 {
 319         if (port)
 320                 return 0;
 321         gpio_set_value(GP_USB_OTG_PWR, on);
 322         return 0;
 323 }
 324 #endif /* CONFIG_USB_EHCI_MX6 */
 325
 326 #ifdef CONFIG_FSL_ESDHC
 327 struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR };
 328
 329 int board_mmc_getcd(struct mmc *mmc)
 330 {
 331         /* Card Detect */
 332         gpio_direction_input(GP_SD3_CD);
 333         return !gpio_get_value(GP_SD3_CD);
 334 }
 335
 336 int board_mmc_init(bd_t *bis)
 337 {
 338         /* Only one USDHC controller on Ventana */
 339         SETUP_IOMUX_PADS(usdhc3_pads);
 340         usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 341         usdhc_cfg.max_bus_width = 4;
 342
 343         return fsl_esdhc_initialize(bis, &usdhc_cfg);
 344 }
 345 #endif /* CONFIG_FSL_ESDHC */
 346
 347 #ifdef CONFIG_MXC_SPI
 348 iomux_v3_cfg_t const ecspi1_pads[] = {
 349         /* SS1 */
 350         IOMUX_PADS(PAD_EIM_D19__GPIO3_IO19  | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 351         IOMUX_PADS(PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 352         IOMUX_PADS(PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 353         IOMUX_PADS(PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL)),
 354 };
 355
 356 static void setup_spi(void)
 357 {
 358         gpio_direction_output(CONFIG_SF_DEFAULT_CS, 1);
 359         SETUP_IOMUX_PADS(ecspi1_pads);
 360 }
 361 #endif
 362
 363 /* configure eth0 PHY board-specific LED behavior */
 364 int board_phy_config(struct phy_device *phydev)
 365 {
 366         unsigned short val;
 367
 368         /* Marvel 88E1510 */
 369         if (phydev->phy_id == 0x1410dd1) {
 370                 /*
 371                  * Page 3, Register 16: LED[2:0] Function Control Register
 372                  * LED[0] (SPD:Amber) R16_3.3:0 to 0111: on-GbE link
 373                  * LED[1] (LNK:Green) R16_3.7:4 to 0001: on-link, blink-activity
 374                  */
 375                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 3);
 376                 val = phy_read(phydev, MDIO_DEVAD_NONE, 16);
 377                 val &= 0xff00;
 378                 val |= 0x0017;
 379                 phy_write(phydev, MDIO_DEVAD_NONE, 16, val);
 380                 phy_write(phydev, MDIO_DEVAD_NONE, 22, 0);
 381         }
 382
 383         if (phydev->drv->config)
 384                 phydev->drv->config(phydev);
 385
 386         return 0;
 387 }
 388
 389 int board_eth_init(bd_t *bis)
 390 {
 391         setup_iomux_enet();
 392
 393 #ifdef CONFIG_FEC_MXC
 394         cpu_eth_init(bis);
 395 #endif
 396
 397 #ifdef CONFIG_CI_UDC
 398         /* For otg ethernet*/
 399         usb_eth_initialize(bis);
 400 #endif
 401
 402         return 0;
 403 }
 404
 405 #if defined(CONFIG_VIDEO_IPUV3)
 406
 407 static void enable_hdmi(struct display_info_t const *dev)
 408 {
 409         imx_enable_hdmi_phy();
 410 }
 411
 412 static int detect_i2c(struct display_info_t const *dev)
 413 {
 414         return i2c_set_bus_num(dev->bus) == 0 &&
 415                 i2c_probe(dev->addr) == 0;
 416 }
 417
 418 static void enable_lvds(struct display_info_t const *dev)
 419 {
 420         struct iomuxc *iomux = (struct iomuxc *)
 421                                 IOMUXC_BASE_ADDR;
 422
 423         /* set CH0 data width to 24bit (IOMUXC_GPR2:5 0=18bit, 1=24bit) */
 424         u32 reg = readl(&iomux->gpr[2]);
 425         reg |= IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT;
 426         writel(reg, &iomux->gpr[2]);
 427
 428         /* Enable Backlight */
 429         SETUP_IOMUX_PAD(PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL));
 430         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 431 }
 432
 433 struct display_info_t const displays[] = {{
 434         /* HDMI Output */
 435         .bus    = -1,
 436         .addr   = 0,
 437         .pixfmt = IPU_PIX_FMT_RGB24,
 438         .detect = detect_hdmi,
 439         .enable = enable_hdmi,
 440         .mode   = {
 441                 .name           = "HDMI",
 442                 .refresh        = 60,
 443                 .xres           = 1024,
 444                 .yres           = 768,
 445                 .pixclock       = 15385,
 446                 .left_margin    = 220,
 447                 .right_margin   = 40,
 448                 .upper_margin   = 21,
 449                 .lower_margin   = 7,
 450                 .hsync_len      = 60,
 451                 .vsync_len      = 10,
 452                 .sync           = FB_SYNC_EXT,
 453                 .vmode          = FB_VMODE_NONINTERLACED
 454 } }, {
 455         /* Freescale MXC-LVDS1: HannStar HSD100PXN1-A00 w/ egalx_ts cont */
 456         .bus    = 2,
 457         .addr   = 0x4,
 458         .pixfmt = IPU_PIX_FMT_LVDS666,
 459         .detect = detect_i2c,
 460         .enable = enable_lvds,
 461         .mode   = {
 462                 .name           = "Hannstar-XGA",
 463                 .refresh        = 60,
 464                 .xres           = 1024,
 465                 .yres           = 768,
 466                 .pixclock       = 15385,
 467                 .left_margin    = 220,
 468                 .right_margin   = 40,
 469                 .upper_margin   = 21,
 470                 .lower_margin   = 7,
 471                 .hsync_len      = 60,
 472                 .vsync_len      = 10,
 473                 .sync           = FB_SYNC_EXT,
 474                 .vmode          = FB_VMODE_NONINTERLACED
 475 } } };
 476 size_t display_count = ARRAY_SIZE(displays);
 477
 478 static void setup_display(void)
 479 {
 480         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
 481         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
 482         int reg;
 483
 484         enable_ipu_clock();
 485         imx_setup_hdmi();
 486         /* Turn on LDB0,IPU,IPU DI0 clocks */
 487         reg = __raw_readl(&mxc_ccm->CCGR3);
 488         reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
 489         writel(reg, &mxc_ccm->CCGR3);
 490
 491         /* set LDB0, LDB1 clk select to 011/011 */
 492         reg = readl(&mxc_ccm->cs2cdr);
 493         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
 494                  |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
 495         reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
 496               |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
 497         writel(reg, &mxc_ccm->cs2cdr);
 498
 499         reg = readl(&mxc_ccm->cscmr2);
 500         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
 501         writel(reg, &mxc_ccm->cscmr2);
 502
 503         reg = readl(&mxc_ccm->chsccdr);
 504         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
 505                 <<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
 506         writel(reg, &mxc_ccm->chsccdr);
 507
 508         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
 509              |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
 510              |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
 511              |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
 512              |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
 513              |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
 514              |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
 515              |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
 516              |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
 517         writel(reg, &iomux->gpr[2]);
 518
 519         reg = readl(&iomux->gpr[3]);
 520         reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
 521             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
 522                <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
 523         writel(reg, &iomux->gpr[3]);
 524
 525         /* Backlight CABEN on LVDS connector */
 526         SETUP_IOMUX_PAD(PAD_SD2_CLK__GPIO1_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL));
 527         gpio_direction_output(IMX_GPIO_NR(1, 10), 0);
 528 }
 529 #endif /* CONFIG_VIDEO_IPUV3 */
 530
 531 /*
 532  * Baseboard specific GPIO
 533  */
 534
 535 /* common to add baseboards */
 536 static iomux_v3_cfg_t const gw_gpio_pads[] = {
 537         /* MSATA_EN */
 538         IOMUX_PADS(PAD_SD4_DAT0__GPIO2_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 539         /* RS232_EN# */
 540         IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 541 };
 542
 543 /* prototype */
 544 static iomux_v3_cfg_t const gwproto_gpio_pads[] = {
 545         /* PANLEDG# */
 546         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 547         /* PANLEDR# */
 548         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 549         /* LOCLED# */
 550         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 551         /* RS485_EN */
 552         IOMUX_PADS(PAD_SD3_DAT4__GPIO7_IO01 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 553         /* IOEXP_PWREN# */
 554         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 555         /* IOEXP_IRQ# */
 556         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 557         /* VID_EN */
 558         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 559         /* DIOI2C_DIS# */
 560         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 561         /* PCICK_SSON */
 562         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 563         /* PCI_RST# */
 564         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 565 };
 566
 567 static iomux_v3_cfg_t const gw51xx_gpio_pads[] = {
 568         /* PANLEDG# */
 569         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 570         /* PANLEDR# */
 571         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 572         /* IOEXP_PWREN# */
 573         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 574         /* IOEXP_IRQ# */
 575         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 576
 577         /* GPS_SHDN */
 578         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 579         /* VID_PWR */
 580         IOMUX_PADS(PAD_CSI0_DATA_EN__GPIO5_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 581         /* PCI_RST# */
 582         IOMUX_PADS(PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 583 };
 584
 585 static iomux_v3_cfg_t const gw52xx_gpio_pads[] = {
 586         /* PANLEDG# */
 587         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 588         /* PANLEDR# */
 589         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 590         /* IOEXP_PWREN# */
 591         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 592         /* IOEXP_IRQ# */
 593         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 594
 595         /* MX6_LOCLED# */
 596         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 597         /* GPS_SHDN */
 598         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 599         /* USBOTG_SEL */
 600         IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 601         /* VID_PWR */
 602         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 603         /* PCI_RST# */
 604         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 605 };
 606
 607 static iomux_v3_cfg_t const gw53xx_gpio_pads[] = {
 608         /* PANLEDG# */
 609         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 610         /* PANLEDR# */
 611         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 612         /* IOEXP_PWREN# */
 613         IOMUX_PADS(PAD_EIM_A19__GPIO2_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 614         /* IOEXP_IRQ# */
 615         IOMUX_PADS(PAD_EIM_A20__GPIO2_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 616         /* DIOI2C_DIS# */
 617         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 618
 619         /* MX6_LOCLED# */
 620         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 621         /* GPS_SHDN */
 622         IOMUX_PADS(PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 623         /* VID_EN */
 624         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 625         /* PCI_RST# */
 626         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 627 };
 628
 629 static iomux_v3_cfg_t const gw54xx_gpio_pads[] = {
 630         /* PANLEDG# */
 631         IOMUX_PADS(PAD_KEY_COL0__GPIO4_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 632         /* PANLEDR# */
 633         IOMUX_PADS(PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 634         /* MX6_LOCLED# */
 635         IOMUX_PADS(PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 636         /* MIPI_DIO */
 637         IOMUX_PADS(PAD_SD1_DAT3__GPIO1_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 638         /* RS485_EN */
 639         IOMUX_PADS(PAD_EIM_D24__GPIO3_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 640         /* IOEXP_PWREN# */
 641         IOMUX_PADS(PAD_KEY_ROW0__GPIO4_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 642         /* IOEXP_IRQ# */
 643         IOMUX_PADS(PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 644         /* DIOI2C_DIS# */
 645         IOMUX_PADS(PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 646         /* PCICK_SSON */
 647         IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 648         /* PCI_RST# */
 649         IOMUX_PADS(PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 650         /* VID_EN */
 651         IOMUX_PADS(PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 652 };
 653
 654 /*
 655  * each baseboard has 4 user configurable Digital IO lines which can
 656  * be pinmuxed as a GPIO or in some cases a PWM
 657  */
 658 struct dio_cfg {
 659         iomux_v3_cfg_t gpio_padmux[2];
 660         unsigned gpio_param;
 661         iomux_v3_cfg_t pwm_padmux[2];
 662         unsigned pwm_param;
 663 };
 664
 665 struct ventana {
 666         /* pinmux */
 667         iomux_v3_cfg_t const *gpio_pads;
 668         int num_pads;
 669         /* DIO pinmux/val */
 670         struct dio_cfg dio_cfg[4];
 671         /* various gpios (0 if non-existent) */
 672         int leds[3];
 673         int pcie_rst;
 674         int mezz_pwren;
 675         int mezz_irq;
 676         int rs485en;
 677         int gps_shdn;
 678         int vidin_en;
 679         int dioi2c_en;
 680         int pcie_sson;
 681         int usb_sel;
 682 };
 683
 684 struct ventana gpio_cfg[] = {
 685         /* GW5400proto */
 686         {
 687                 .gpio_pads = gw54xx_gpio_pads,
 688                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 689                 .dio_cfg = {
 690                         {
 691                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 692                                 IMX_GPIO_NR(1, 9),
 693                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 694                                 1
 695                         },
 696                         {
 697                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 698                                 IMX_GPIO_NR(1, 19),
 699                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 700                                 2
 701                         },
 702                         {
 703                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 704                                 IMX_GPIO_NR(2, 9),
 705                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 706                                 3
 707                         },
 708                         {
 709                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 710                                 IMX_GPIO_NR(2, 10),
 711                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 712                                 4
 713                         },
 714                 },
 715                 .leds = {
 716                         IMX_GPIO_NR(4, 6),
 717                         IMX_GPIO_NR(4, 10),
 718                         IMX_GPIO_NR(4, 15),
 719                 },
 720                 .pcie_rst = IMX_GPIO_NR(1, 29),
 721                 .mezz_pwren = IMX_GPIO_NR(4, 7),
 722                 .mezz_irq = IMX_GPIO_NR(4, 9),
 723                 .rs485en = IMX_GPIO_NR(3, 24),
 724                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 725                 .pcie_sson = IMX_GPIO_NR(1, 20),
 726         },
 727
 728         /* GW51xx */
 729         {
 730                 .gpio_pads = gw51xx_gpio_pads,
 731                 .num_pads = ARRAY_SIZE(gw51xx_gpio_pads)/2,
 732                 .dio_cfg = {
 733                         {
 734                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 735                                 IMX_GPIO_NR(1, 16),
 736                                 { 0, 0 },
 737                                 0
 738                         },
 739                         {
 740                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 741                                 IMX_GPIO_NR(1, 19),
 742                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 743                                 2
 744                         },
 745                         {
 746                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 747                                 IMX_GPIO_NR(1, 17),
 748                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 749                                 3
 750                         },
 751                         {
 752                                 { IOMUX_PADS(PAD_SD1_CMD__GPIO1_IO18) },
 753                                 IMX_GPIO_NR(1, 18),
 754                                 { IOMUX_PADS(PAD_SD1_CMD__PWM4_OUT) },
 755                                 4
 756                         },
 757                 },
 758                 .leds = {
 759                         IMX_GPIO_NR(4, 6),
 760                         IMX_GPIO_NR(4, 10),
 761                 },
 762                 .pcie_rst = IMX_GPIO_NR(1, 0),
 763                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 764                 .mezz_irq = IMX_GPIO_NR(2, 18),
 765                 .gps_shdn = IMX_GPIO_NR(1, 2),
 766                 .vidin_en = IMX_GPIO_NR(5, 20),
 767         },
 768
 769         /* GW52xx */
 770         {
 771                 .gpio_pads = gw52xx_gpio_pads,
 772                 .num_pads = ARRAY_SIZE(gw52xx_gpio_pads)/2,
 773                 .dio_cfg = {
 774                         {
 775                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 776                                 IMX_GPIO_NR(1, 16),
 777                                 { 0, 0 },
 778                                 0
 779                         },
 780                         {
 781                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 782                                 IMX_GPIO_NR(1, 19),
 783                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 784                                 2
 785                         },
 786                         {
 787                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 788                                 IMX_GPIO_NR(1, 17),
 789                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 790                                 3
 791                         },
 792                         {
 793                                 { IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 794                                 IMX_GPIO_NR(1, 20),
 795                                 { 0, 0 },
 796                                 0
 797                         },
 798                 },
 799                 .leds = {
 800                         IMX_GPIO_NR(4, 6),
 801                         IMX_GPIO_NR(4, 7),
 802                         IMX_GPIO_NR(4, 15),
 803                 },
 804                 .pcie_rst = IMX_GPIO_NR(1, 29),
 805                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 806                 .mezz_irq = IMX_GPIO_NR(2, 18),
 807                 .gps_shdn = IMX_GPIO_NR(1, 27),
 808                 .vidin_en = IMX_GPIO_NR(3, 31),
 809                 .usb_sel = IMX_GPIO_NR(1, 2),
 810         },
 811
 812         /* GW53xx */
 813         {
 814                 .gpio_pads = gw53xx_gpio_pads,
 815                 .num_pads = ARRAY_SIZE(gw53xx_gpio_pads)/2,
 816                 .dio_cfg = {
 817                         {
 818                                 { IOMUX_PADS(PAD_SD1_DAT0__GPIO1_IO16) },
 819                                 IMX_GPIO_NR(1, 16),
 820                                 { 0, 0 },
 821                                 0
 822                         },
 823                         {
 824                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 825                                 IMX_GPIO_NR(1, 19),
 826                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 827                                 2
 828                         },
 829                         {
 830                                 { IOMUX_PADS(PAD_SD1_DAT1__GPIO1_IO17) },
 831                                 IMX_GPIO_NR(1, 17),
 832                                 { IOMUX_PADS(PAD_SD1_DAT1__PWM3_OUT) },
 833                                 3
 834                         },
 835                         {
 836                                 {IOMUX_PADS(PAD_SD1_CLK__GPIO1_IO20) },
 837                                 IMX_GPIO_NR(1, 20),
 838                                 { 0, 0 },
 839                                 0
 840                         },
 841                 },
 842                 .leds = {
 843                         IMX_GPIO_NR(4, 6),
 844                         IMX_GPIO_NR(4, 7),
 845                         IMX_GPIO_NR(4, 15),
 846                 },
 847                 .pcie_rst = IMX_GPIO_NR(1, 29),
 848                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 849                 .mezz_irq = IMX_GPIO_NR(2, 18),
 850                 .gps_shdn = IMX_GPIO_NR(1, 27),
 851                 .vidin_en = IMX_GPIO_NR(3, 31),
 852         },
 853
 854         /* GW54xx */
 855         {
 856                 .gpio_pads = gw54xx_gpio_pads,
 857                 .num_pads = ARRAY_SIZE(gw54xx_gpio_pads)/2,
 858                 .dio_cfg = {
 859                         {
 860                                 { IOMUX_PADS(PAD_GPIO_9__GPIO1_IO09) },
 861                                 IMX_GPIO_NR(1, 9),
 862                                 { IOMUX_PADS(PAD_GPIO_9__PWM1_OUT) },
 863                                 1
 864                         },
 865                         {
 866                                 { IOMUX_PADS(PAD_SD1_DAT2__GPIO1_IO19) },
 867                                 IMX_GPIO_NR(1, 19),
 868                                 { IOMUX_PADS(PAD_SD1_DAT2__PWM2_OUT) },
 869                                 2
 870                         },
 871                         {
 872                                 { IOMUX_PADS(PAD_SD4_DAT1__GPIO2_IO09) },
 873                                 IMX_GPIO_NR(2, 9),
 874                                 { IOMUX_PADS(PAD_SD4_DAT1__PWM3_OUT) },
 875                                 3
 876                         },
 877                         {
 878                                 { IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10) },
 879                                 IMX_GPIO_NR(2, 10),
 880                                 { IOMUX_PADS(PAD_SD4_DAT2__PWM4_OUT) },
 881                                 4
 882                         },
 883                 },
 884                 .leds = {
 885                         IMX_GPIO_NR(4, 6),
 886                         IMX_GPIO_NR(4, 7),
 887                         IMX_GPIO_NR(4, 15),
 888                 },
 889                 .pcie_rst = IMX_GPIO_NR(1, 29),
 890                 .mezz_pwren = IMX_GPIO_NR(2, 19),
 891                 .mezz_irq = IMX_GPIO_NR(2, 18),
 892                 .rs485en = IMX_GPIO_NR(7, 1),
 893                 .vidin_en = IMX_GPIO_NR(3, 31),
 894                 .dioi2c_en = IMX_GPIO_NR(4,  5),
 895                 .pcie_sson = IMX_GPIO_NR(1, 20),
 896         },
 897 };
 898
 899 /* setup board specific PMIC */
 900 int power_init_board(void)
 901 {
 902         struct pmic *p;
 903         u32 reg;
 904
 905         /* configure PFUZE100 PMIC */
 906         if (board_type == GW54xx || board_type == GW54proto) {
 907                 power_pfuze100_init(I2C_PMIC);
 908                 p = pmic_get("PFUZE100");
 909                 if (p && !pmic_probe(p)) {
 910                         pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
 911                         printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 912
 913                         /* Set VGEN1 to 1.5V and enable */
 914                         pmic_reg_read(p, PFUZE100_VGEN1VOL, &reg);
 915                         reg &= ~(LDO_VOL_MASK);
 916                         reg |= (LDOA_1_50V | LDO_EN);
 917                         pmic_reg_write(p, PFUZE100_VGEN1VOL, reg);
 918
 919                         /* Set SWBST to 5.0V and enable */
 920                         pmic_reg_read(p, PFUZE100_SWBSTCON1, &reg);
 921                         reg &= ~(SWBST_MODE_MASK | SWBST_VOL_MASK);
 922                         reg |= (SWBST_5_00V | SWBST_MODE_AUTO);
 923                         pmic_reg_write(p, PFUZE100_SWBSTCON1, reg);
 924                 }
 925         }
 926
 927         /* configure LTC3676 PMIC */
 928         else {
 929                 power_ltc3676_init(I2C_PMIC);
 930                 p = pmic_get("LTC3676_PMIC");
 931                 if (p && !pmic_probe(p)) {
 932                         puts("PMIC:  LTC3676\n");
 933                         /* set board-specific scalar to 1225mV for IMX6Q@1GHz */
 934                         if (is_cpu_type(MXC_CPU_MX6Q)) {
 935                                 /* mask PGOOD during SW1 transition */
 936                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 937                                 pmic_reg_write(p, LTC3676_DVB1B, reg);
 938                                 /* set SW1 (VDD_SOC) to 1259mV */
 939                                 reg = 0x1d;
 940                                 pmic_reg_write(p, LTC3676_DVB1A, reg);
 941
 942                                 /* mask PGOOD during SW3 transition */
 943                                 reg = 0x1d | LTC3676_PGOOD_MASK;
 944                                 pmic_reg_write(p, LTC3676_DVB3B, reg);
 945                                 /*set SW3 (VDD_ARM) to 1259mV */
 946                                 reg = 0x1d;
 947                                 pmic_reg_write(p, LTC3676_DVB3A, reg);
 948                         }
 949                 }
 950         }
 951
 952         return 0;
 953 }
 954
 955 /* setup GPIO pinmux and default configuration per baseboard */
 956 static void setup_board_gpio(int board)
 957 {
 958         struct ventana_board_info *info = &ventana_info;
 959         const char *s;
 960         char arg[10];
 961         size_t len;
 962         int i;
 963         int quiet = simple_strtol(getenv("quiet"), NULL, 10);
 964
 965         if (board >= GW_UNKNOWN)
 966                 return;
 967
 968         /* RS232_EN# */
 969         gpio_direction_output(GP_RS232_EN, (hwconfig("rs232")) ? 0 : 1);
 970
 971         /* MSATA Enable */
 972         if (is_cpu_type(MXC_CPU_MX6Q) &&
 973             test_bit(EECONFIG_SATA, info->config)) {
 974                 gpio_direction_output(GP_MSATA_SEL,
 975                                       (hwconfig("msata")) ?  1 : 0);
 976         } else {
 977                 gpio_direction_output(GP_MSATA_SEL, 0);
 978         }
 979
 980         /*
 981          * assert PCI_RST# (released by OS when clock is valid)
 982          * TODO: figure out why leaving this de-asserted from PCI scan on boot
 983          *       causes linux pcie driver to hang during enumeration
 984          */
 985         gpio_direction_output(gpio_cfg[board].pcie_rst, 0);
 986
 987         /* turn off (active-high) user LED's */
 988         for (i = 0; i < 4; i++) {
 989                 if (gpio_cfg[board].leds[i])
 990                         gpio_direction_output(gpio_cfg[board].leds[i], 1);
 991         }
 992
 993         /* Expansion Mezzanine IO */
 994         gpio_direction_output(gpio_cfg[board].mezz_pwren, 0);
 995         gpio_direction_input(gpio_cfg[board].mezz_irq);
 996
 997         /* RS485 Transmit Enable */
 998         if (gpio_cfg[board].rs485en)
 999                 gpio_direction_output(gpio_cfg[board].rs485en, 0);
1000
1001         /* GPS_SHDN */
1002         if (gpio_cfg[board].gps_shdn)
1003                 gpio_direction_output(gpio_cfg[board].gps_shdn, 1);
1004
1005         /* Analog video codec power enable */
1006         if (gpio_cfg[board].vidin_en)
1007                 gpio_direction_output(gpio_cfg[board].vidin_en, 1);
1008
1009         /* DIOI2C_DIS# */
1010         if (gpio_cfg[board].dioi2c_en)
1011                 gpio_direction_output(gpio_cfg[board].dioi2c_en, 0);
1012
1013         /* PCICK_SSON: disable spread-spectrum clock */
1014         if (gpio_cfg[board].pcie_sson)
1015                 gpio_direction_output(gpio_cfg[board].pcie_sson, 0);
1016
1017         /* USBOTG Select (PCISKT or FrontPanel) */
1018         if (gpio_cfg[board].usb_sel)
1019                 gpio_direction_output(gpio_cfg[board].usb_sel, 0);
1020
1021         /*
1022          * Configure DIO pinmux/padctl registers
1023          * see IMX6DQRM/IMX6SDLRM IOMUXC_SW_PAD_CTL_PAD_* register definitions
1024          */
1025         for (i = 0; i < 4; i++) {
1026                 struct dio_cfg *cfg = &gpio_cfg[board].dio_cfg[i];
1027                 unsigned ctrl = DIO_PAD_CTRL;
1028                 unsigned cputype = is_cpu_type(MXC_CPU_MX6Q) ? 0 : 1;
1029
1030                 sprintf(arg, "dio%d", i);
1031                 if (!hwconfig(arg))
1032                         continue;
1033                 s = hwconfig_subarg(arg, "padctrl", &len);
1034                 if (s)
1035                         ctrl = simple_strtoul(s, NULL, 16) & 0x3ffff;
1036                 if (hwconfig_subarg_cmp(arg, "mode", "gpio")) {
1037                         if (!quiet) {
1038                                 printf("DIO%d:  GPIO%d_IO%02d (gpio-%d)\n", i,
1039                                        (cfg->gpio_param/32)+1,
1040                                        cfg->gpio_param%32,
1041                                        cfg->gpio_param);
1042                         }
1043                         imx_iomux_v3_setup_pad(cfg->gpio_padmux[cputype] |
1044                                                MUX_PAD_CTRL(ctrl));
1045                         gpio_direction_input(cfg->gpio_param);
1046                 } else if (hwconfig_subarg_cmp("dio2", "mode", "pwm") &&
1047                            cfg->pwm_padmux) {
1048                         if (!quiet)
1049                                 printf("DIO%d:  pwm%d\n", i, cfg->pwm_param);
1050                         imx_iomux_v3_setup_pad(cfg->pwm_padmux[cputype] |
1051                                                MUX_PAD_CTRL(ctrl));
1052                 }
1053         }
1054
1055         if (!quiet) {
1056                 if (is_cpu_type(MXC_CPU_MX6Q) &&
1057                     (test_bit(EECONFIG_SATA, info->config))) {
1058                         printf("MSATA: %s\n", (hwconfig("msata") ?
1059                                "enabled" : "disabled"));
1060                 }
1061                 printf("RS232: %s\n", (hwconfig("rs232")) ?
1062                        "enabled" : "disabled");
1063         }
1064 }
1065
1066 #if defined(CONFIG_CMD_PCI)
1067 int imx6_pcie_toggle_reset(void)
1068 {
1069         if (board_type < GW_UNKNOWN) {
1070                 uint pin = gpio_cfg[board_type].pcie_rst;
1071                 gpio_direction_output(pin, 0);
1072                 mdelay(50);
1073                 gpio_direction_output(pin, 1);
1074         }
1075         return 0;
1076 }
1077 #endif /* CONFIG_CMD_PCI */
1078
1079 #ifdef CONFIG_SERIAL_TAG
1080 /*
1081  * called when setting up ATAGS before booting kernel
1082  * populate serialnum from the following (in order of priority):
1083  *   serial# env var
1084  *   eeprom
1085  */
1086 void get_board_serial(struct tag_serialnr *serialnr)
1087 {
1088         char *serial = getenv("serial#");
1089
1090         if (serial) {
1091                 serialnr->high = 0;
1092                 serialnr->low = simple_strtoul(serial, NULL, 10);
1093         } else if (ventana_info.model[0]) {
1094                 serialnr->high = 0;
1095                 serialnr->low = ventana_info.serial;
1096         } else {
1097                 serialnr->high = 0;
1098                 serialnr->low = 0;
1099         }
1100 }
1101 #endif
1102
1103 /*
1104  * Board Support
1105  */
1106
1107 /* called from SPL board_init_f() */
1108 int board_early_init_f(void)
1109 {
1110         setup_iomux_uart();
1111         gpio_direction_output(GP_USB_OTG_PWR, 0); /* OTG power off */
1112
1113 #if defined(CONFIG_VIDEO_IPUV3)
1114         setup_display();
1115 #endif
1116         return 0;
1117 }
1118
1119 int dram_init(void)
1120 {
1121         gd->ram_size = imx_ddr_size();
1122         return 0;
1123 }
1124
1125 int board_init(void)
1126 {
1127         struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
1128
1129         clrsetbits_le32(&iomuxc_regs->gpr[1],
1130                         IOMUXC_GPR1_OTG_ID_MASK,
1131                         IOMUXC_GPR1_OTG_ID_GPIO1);
1132
1133         /* address of linux boot parameters */
1134         gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
1135
1136 #ifdef CONFIG_CMD_NAND
1137         setup_gpmi_nand();
1138 #endif
1139 #ifdef CONFIG_MXC_SPI
1140         setup_spi();
1141 #endif
1142         if (is_cpu_type(MXC_CPU_MX6Q)) {
1143                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info0);
1144                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info1);
1145                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c_pad_info2);
1146         } else {
1147                 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info0);
1148                 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info1);
1149                 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c_pad_info2);
1150         }
1151
1152 #ifdef CONFIG_CMD_SATA
1153         setup_sata();
1154 #endif
1155         /* read Gateworks EEPROM into global struct (used later) */
1156         board_type = read_eeprom(I2C_GSC, &ventana_info);
1157
1158         /* board-specifc GPIO iomux */
1159         SETUP_IOMUX_PADS(gw_gpio_pads);
1160         if (board_type < GW_UNKNOWN) {
1161                 iomux_v3_cfg_t const *p = gpio_cfg[board_type].gpio_pads;
1162                 int count = gpio_cfg[board_type].num_pads;
1163
1164                 imx_iomux_v3_setup_multiple_pads(p, count);
1165         }
1166
1167         return 0;
1168 }
1169
1170 #if defined(CONFIG_DISPLAY_BOARDINFO_LATE)
1171 /*
1172  * called during late init (after relocation and after board_init())
1173  * by virtue of CONFIG_DISPLAY_BOARDINFO_LATE as we needed i2c initialized and
1174  * EEPROM read.
1175  */
1176 int checkboard(void)
1177 {
1178         struct ventana_board_info *info = &ventana_info;
1179         unsigned char buf[4];
1180         const char *p;
1181         int quiet; /* Quiet or minimal output mode */
1182
1183         quiet = 0;
1184         p = getenv("quiet");
1185         if (p)
1186                 quiet = simple_strtol(p, NULL, 10);
1187         else
1188                 setenv("quiet", "0");
1189
1190         puts("\nGateworks Corporation Copyright 2014\n");
1191         if (info->model[0]) {
1192                 printf("Model: %s\n", info->model);
1193                 printf("MFGDate: %02x-%02x-%02x%02x\n",
1194                        info->mfgdate[0], info->mfgdate[1],
1195                        info->mfgdate[2], info->mfgdate[3]);
1196                 printf("Serial:%d\n", info->serial);
1197         } else {
1198                 puts("Invalid EEPROM - board will not function fully\n");
1199         }
1200         if (quiet)
1201                 return 0;
1202
1203         /* Display GSC firmware revision/CRC/status */
1204         i2c_set_bus_num(I2C_GSC);
1205         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_FWVER, 1, buf, 1)) {
1206                 printf("GSC:   v%d", buf[0]);
1207                 if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, buf, 4)) {
1208                         printf(" 0x%04x", buf[2] | buf[3]<<8); /* CRC */
1209                         printf(" 0x%02x", buf[0]); /* irq status */
1210                 }
1211                 puts("\n");
1212         }
1213         /* Display RTC */
1214         if (!gsc_i2c_read(GSC_RTC_ADDR, 0x00, 1, buf, 4)) {
1215                 printf("RTC:   %d\n",
1216                        buf[0] | buf[1]<<8 | buf[2]<<16 | buf[3]<<24);
1217         }
1218
1219         return 0;
1220 }
1221 #endif
1222
1223 #ifdef CONFIG_CMD_BMODE
1224 /*
1225  * BOOT_CFG1, BOOT_CFG2, BOOT_CFG3, BOOT_CFG4
1226  * see Table 8-11 and Table 5-9
1227  *  BOOT_CFG1[7] = 1 (boot from NAND)
1228  *  BOOT_CFG1[5] = 0 - raw NAND
1229  *  BOOT_CFG1[4] = 0 - default pad settings
1230  *  BOOT_CFG1[3:2] = 00 - devices = 1
1231  *  BOOT_CFG1[1:0] = 00 - Row Address Cycles = 3
1232  *  BOOT_CFG2[4:3] = 00 - Boot Search Count = 2
1233  *  BOOT_CFG2[2:1] = 01 - Pages In Block = 64
1234  *  BOOT_CFG2[0] = 0 - Reset time 12ms
1235  */
1236 static const struct boot_mode board_boot_modes[] = {
1237         /* NAND: 64pages per block, 3 row addr cycles, 2 copies of FCB/DBBT */
1238         { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) },
1239         { NULL, 0 },
1240 };
1241 #endif
1242
1243 /* late init */
1244 int misc_init_r(void)
1245 {
1246         struct ventana_board_info *info = &ventana_info;
1247         unsigned char reg;
1248
1249         /* set env vars based on EEPROM data */
1250         if (ventana_info.model[0]) {
1251                 char str[16], fdt[36];
1252                 char *p;
1253                 const char *cputype = "";
1254                 int i;
1255
1256                 /*
1257                  * FDT name will be prefixed with CPU type.  Three versions
1258                  * will be created each increasingly generic and bootloader
1259                  * env scripts will try loading each from most specific to
1260                  * least.
1261                  */
1262                 if (is_cpu_type(MXC_CPU_MX6Q) ||
1263                     is_cpu_type(MXC_CPU_MX6D))
1264                         cputype = "imx6q";
1265                 else if (is_cpu_type(MXC_CPU_MX6DL) ||
1266                          is_cpu_type(MXC_CPU_MX6SOLO))
1267                         cputype = "imx6dl";
1268                 if (8 << (ventana_info.nand_flash_size-1) >= 2048)
1269                         setenv("flash_layout", "large");
1270                 else
1271                         setenv("flash_layout", "normal");
1272                 memset(str, 0, sizeof(str));
1273                 for (i = 0; i < (sizeof(str)-1) && info->model[i]; i++)
1274                         str[i] = tolower(info->model[i]);
1275                 if (!getenv("model"))
1276                         setenv("model", str);
1277                 if (!getenv("fdt_file")) {
1278                         sprintf(fdt, "%s-%s.dtb", cputype, str);
1279                         setenv("fdt_file", fdt);
1280                 }
1281                 p = strchr(str, '-');
1282                 if (p) {
1283                         *p++ = 0;
1284
1285                         setenv("model_base", str);
1286                         if (!getenv("fdt_file1")) {
1287                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1288                                 setenv("fdt_file1", fdt);
1289                         }
1290                         str[4] = 'x';
1291                         str[5] = 'x';
1292                         str[6] = 0;
1293                         if (!getenv("fdt_file2")) {
1294                                 sprintf(fdt, "%s-%s.dtb", cputype, str);
1295                                 setenv("fdt_file2", fdt);
1296                         }
1297                 }
1298
1299                 /* initialize env from EEPROM */
1300                 if (test_bit(EECONFIG_ETH0, info->config) &&
1301                     !getenv("ethaddr")) {
1302                         eth_setenv_enetaddr("ethaddr", info->mac0);
1303                 }
1304                 if (test_bit(EECONFIG_ETH1, info->config) &&
1305                     !getenv("eth1addr")) {
1306                         eth_setenv_enetaddr("eth1addr", info->mac1);
1307                 }
1308
1309                 /* board serial-number */
1310                 sprintf(str, "%6d", info->serial);
1311                 setenv("serial#", str);
1312         }
1313
1314
1315         /* setup baseboard specific GPIO pinmux and config */
1316         setup_board_gpio(board_type);
1317
1318 #ifdef CONFIG_CMD_BMODE
1319         add_board_boot_modes(board_boot_modes);
1320 #endif
1321
1322         /*
1323          *  The Gateworks System Controller implements a boot
1324          *  watchdog (always enabled) as a workaround for IMX6 boot related
1325          *  errata such as:
1326          *    ERR005768 - no fix
1327          *    ERR006282 - fixed in silicon r1.3
1328          *    ERR007117 - fixed in silicon r1.3
1329          *    ERR007220 - fixed in silicon r1.3
1330          *  see http://cache.freescale.com/files/32bit/doc/errata/IMX6DQCE.pdf
1331          *
1332          * Disable the boot watchdog and display/clear the timeout flag if set
1333          */
1334         i2c_set_bus_num(I2C_GSC);
1335         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1)) {
1336                 reg |= (1 << GSC_SC_CTRL1_WDDIS);
1337                 if (gsc_i2c_write(GSC_SC_ADDR, GSC_SC_CTRL1, 1, &reg, 1))
1338                         puts("Error: could not disable GSC Watchdog\n");
1339         } else {
1340                 puts("Error: could not disable GSC Watchdog\n");
1341         }
1342         if (!gsc_i2c_read(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1)) {
1343                 if (reg & (1 << GSC_SC_IRQ_WATCHDOG)) { /* watchdog timeout */
1344                         puts("GSC boot watchdog timeout detected\n");
1345                         reg &= ~(1 << GSC_SC_IRQ_WATCHDOG); /* clear flag */
1346                         gsc_i2c_write(GSC_SC_ADDR, GSC_SC_STATUS, 1, &reg, 1);
1347                 }
1348         }
1349
1350         return 0;
1351 }
1352
1353 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
1354
1355 /* FDT aliases associated with EEPROM config bits */
1356 const char *fdt_aliases[] = {
1357         "ethernet0",
1358         "ethernet1",
1359         "hdmi_out",
1360         "ahci0",
1361         "pcie",
1362         "ssi0",
1363         "ssi1",
1364         "lcd0",
1365         "lvds0",
1366         "lvds1",
1367         "usb0",
1368         "usb1",
1369         "mmc0",
1370         "mmc1",
1371         "mmc2",
1372         "mmc3",
1373         "uart0",
1374         "uart1",
1375         "uart2",
1376         "uart3",
1377         "uart4",
1378         "ipu0",
1379         "ipu1",
1380         "can0",
1381         "mipi_dsi",
1382         "mipi_csi",
1383         "tzasc0",
1384         "tzasc1",
1385         "i2c0",
1386         "i2c1",
1387         "i2c2",
1388         "vpu",
1389         "csi0",
1390         "csi1",
1391         NULL,
1392         NULL,
1393         NULL,
1394         NULL,
1395         NULL,
1396         NULL,
1397         "spi0",
1398         "spi1",
1399         "spi2",
1400         "spi3",
1401         "spi4",
1402         "spi5",
1403         NULL,
1404         NULL,
1405         "pps",
1406         NULL,
1407         NULL,
1408         NULL,
1409         "hdmi_in",
1410         "cvbs_out",
1411         "cvbs_in",
1412         "nand",
1413         NULL,
1414         NULL,
1415         NULL,
1416         NULL,
1417         NULL,
1418         NULL,
1419         NULL,
1420         NULL,
1421 };
1422
1423 /*
1424  * called prior to booting kernel or by 'fdt boardsetup' command
1425  *
1426  * unless 'fdt_noauto' env var is set we will update the following in the DTB:
1427  *  - mtd partitions based on mtdparts/mtdids env
1428  *  - system-serial (board serial num from EEPROM)
1429  *  - board (full model from EEPROM)
1430  *  - peripherals removed from DTB if not loaded on board (per EEPROM config)
1431  */
1432 void ft_board_setup(void *blob, bd_t *bd)
1433 {
1434         int bit;
1435         struct ventana_board_info *info = &ventana_info;
1436         struct node_info nodes[] = {
1437                 { "sst,w25q256",          MTD_DEV_TYPE_NOR, },  /* SPI flash */
1438                 { "fsl,imx6q-gpmi-nand",  MTD_DEV_TYPE_NAND, }, /* NAND flash */
1439         };
1440         const char *model = getenv("model");
1441
1442         if (getenv("fdt_noauto")) {
1443                 puts("   Skiping ft_board_setup (fdt_noauto defined)\n");
1444                 return;
1445         }
1446
1447         /* Update partition nodes using info from mtdparts env var */
1448         puts("   Updating MTD partitions...\n");
1449         fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
1450
1451         if (!model) {
1452                 puts("invalid board info: Leaving FDT fully enabled\n");
1453                 return;
1454         }
1455         printf("   Adjusting FDT per EEPROM for %s...\n", model);
1456
1457         /* board serial number */
1458         fdt_setprop(blob, 0, "system-serial", getenv("serial#"),
1459                     strlen(getenv("serial#")) + 1);
1460
1461         /* board (model contains model from device-tree) */
1462         fdt_setprop(blob, 0, "board", info->model,
1463                     strlen((const char *)info->model) + 1);
1464
1465         /*
1466          * Peripheral Config:
1467          *  remove nodes by alias path if EEPROM config tells us the
1468          *  peripheral is not loaded on the board.
1469          */
1470         for (bit = 0; bit < 64; bit++) {
1471                 if (!test_bit(bit, info->config))
1472                         fdt_del_node_and_alias(blob, fdt_aliases[bit]);
1473         }
1474 }
1475 #endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
1476